JPH0473797A - Liquid crystal driving circuit and semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To check the occurrence of a through current in the case of changing a clock signal by controlling the actions of 1st and 2nd circuits which control to switch level voltage with a control signal having a specified logical value so that the level voltage of both circuits may be temporarily in a non-selective state. CONSTITUTION:Driving buffers DBUF1-DBUF110 are provided for respective output terminals S1-S110. In the P channel type MOSFET P1 and P2 and N channel type MOSFET N1and N2 of the respective buffers DBUF1-FBUF110,the through current is surely prevented from occurring when the switching state of the P channel type MOSFET and the N channel type MOSFET is inverted, because what should be turned on it turned on after what should be turned off is turned off by the level inversion of a frame switching signal FRM.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a liquid crystal drive circuit, particularly a liquid crystal drive circuit that drives signal electrodes of a dot matrix type liquid crystal display. The present invention relates to a technique that is effective when applied to a liquid crystal drive circuit formed into a semiconductor integrated circuit and having a large number of output terminals for supplying the same.

[Prior Art] A dot-matrix type liquid crystal display in which liquid crystal display elements are arranged in a matrix has a plurality of scanning electrodes and a plurality of signal electrodes that are arranged intersectingly with the scanning electrodes, and a scanning voltage is sequentially applied to the scanning electrodes. When the signal is applied, a display signal is applied to the signal electrode in synchronization with this, thereby performing display. In this display drive, so-called AC drive is performed to prevent deterioration of the liquid crystal display element. That is, in a liquid crystal drive circuit for applying a display signal to a signal electrode, the level voltage for driving the liquid crystal display element is alternately switched between a high level side and a low level side for each display frame, and the level at that time is changed. The lighting level or non-lighting level of the voltage is selected based on the display data and is supplied to the signal electrode. For example, as shown in Figure 6, the level voltage on the high level side is 20
V and 24V, and the level voltage on the low level side is Ov and 4V, the operation of the Nant gates NAI and NA2 can be selected during the period when the frame switching signal FRM is set to high level, and at this time, the display data DATA1 lights up. When this means, the complementary output signal of the level shift circuit LS2 makes the output of the Nant game 1-N A 1 low level, and thereby the display signal output terminal S1 receives 2.4 V via the I] channel type MO3FETP1. voltage is supplied. When the display data means non-lighting, the display signal output terminal S1 is a P-channel type MO8F1ΣT.
A voltage of 20V is supplied via P2. On the other hand, during the period when the frame switching signal FRM is at low level,
When the operations of the NOR gates NRI and NR2 are made selectable and the display data DATA1 instructs lighting, the NOR gates NRI and NR2 are switched on by the complementary output signal of the level shift circuit LS2.
The output of is set to a low level, whereby a voltage of Ov is supplied to the display signal output terminal S1 via the N-channel type MO3FETN2. When the display data instructs non-lighting, the display signal output terminal S1 is connected to an N-channel MO
A voltage of 4v is supplied via 5FETNI. At this time, 4■ and 20V are applied to the common electrode of the liquid crystal display.
Intermediate levels between are given in order.

An example of a document describing the liquid crystal drive circuit is "Microcomputer Handbook" published by Ohm Publishing, December 25, 1985, pages 412 and 413.

[Problem to be solved by the invention]

The inventor studied the power consumption of a liquid crystal drive circuit as shown in FIG. 6, and found that the frame switching signal F
It has been found that a particularly large amount of power is consumed when the RM level is inverted. When the level of the frame switching signal FRM is inverted, MO5FETPI, P2. N1. N
The level voltage to be selected by 2 is 24V or 20V on the relatively high level side and Ov on the relatively low level side.
or 4v, but M○5F for that
During the transient response period of ETPl or P2 and MO3FETNI or N2, a through current is generated from the high level side to the low level side level power supply, and this through current is caused by the buffer circuit corresponding to all the parallel output terminals. This is because they can occur simultaneously. Furthermore, since only one frame switching signal FRM controls the operation of numerous NOR gates and Nant gates corresponding to all output terminals,
The further away from the drive end of the frame switching signal RRM, the slower the change in the signal FRM becomes due to signal delay, and the through current increases further. In particular, in battery-powered laptop-type personal computers, electronic notebooks, etc., the lifespan of the charged battery is significantly reduced.
It is expected that the usability will deteriorate.

An object of the present invention is to provide a liquid crystal drive circuit that can significantly reduce the generation of through current that occurs when a clock signal for AC driving the liquid crystal drive circuit changes.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the first circuit and the second circuit alternately select the level pressure for driving the liquid crystal display element between the high level side and the low level side according to the level change of the clock signal, depending on the level change of the clock signal. A signal generating means is provided for generating operation control signals for the first circuit and the second circuit by performing phase control to temporarily bring both circuits into a non-selected state.

In addition, as another or similar signal generation means, the first circuit and the second circuit may be mutually changed to one non-selected control state and then changed to the other selected control state in response to a level change of the clock signal. The first
It is also possible to adopt a configuration in which a phase-controlled switching control signal for the second circuit is generated based on the clock signal.

In these means, as a signal delay for phase control, the control signal of a large number of parallel first circuits is fed back from the terminal end to the base end side of the control signal line for the second circuit, for example, by folding wiring, and the like. It is possible to employ folded wiring for feeding back the control signals of a large number of parallel second circuits to the base end of the control signal line for the first circuit, for example, from the terminal end thereof. for example,
a control signal wiring coupled to a control terminal of the first circuit;
A control signal wiring coupled to a control terminal of a circuit is connected back to the drive end side logic gate of the other wiring, and a change in state of one can be detected by the other by a signal on the looped back route. Accordingly, each logic gate can mutually allow one to change to a non-selected state and then the other to change to a selected state.

Further, when using the logic operation or operation delay of a gate as a signal delay for phase control, the output of the gate is used as the control input of the first circuit and the second circuit.

These liquid crystal drive circuits can be implemented as semiconductor integrated circuits, and in that case, a dual-port buffer memory that stores display data supplied from an external terminal through one port, and a dual-port buffer memory that stores display data supplied from an external terminal through one port, and a A latch circuit that holds display data read from the port and outputs it to the liquid crystal drive circuit at a predetermined timing can be included.

[For production]

According to the above means, when switching between a high level voltage and a low level voltage used for AC driving of a liquid crystal display element, both level voltages are temporarily controlled to a non-selected state, This suppresses the generation of through current from the high level side to the low level side during a transient response of level voltage switching.

Obtaining a predetermined phase difference between the selection control signals for the first circuit and the second circuit by using the delay of the folded wiring is as follows:
Compared to the case of using gate logic operation or operation delay delay, it becomes unnecessary to set an operation margin for delay time, contributes to a reduction in the number of circuit elements, and suppresses the occurrence of the through current with ease and high reliability. do.

〔Example〕

FIG. 5 shows an example of a liquid crystal display system to which a liquid crystal drive circuit according to an embodiment of the present invention is applied.

In the figure, reference numeral 1 denotes a dot matrix type liquid crystal display, in which a plurality of liquid crystal display elements are arranged in a matrix, a plurality of scanning electrodes are arranged in the horizontal direction of the figure, and a plurality of scanning electrodes are arranged in a crosswise manner. When a scanning voltage is sequentially applied to the scanning electrodes, display is performed by applying a display signal to the signal electrodes in synchronization with this.

In FIG. 5, 2 is a common driver implemented as a semiconductor integrated circuit for applying an operating voltage to the scanning electrode of the liquid crystal display 1, and 3 is a common driver implemented as a semiconductor integrated circuit for applying a display signal to the signal electrode of the liquid crystal display 1. The common driver 2 provides a frame switching signal FRM, a line synchronization signal LSY, etc. to the segment driver 3 to synchronize the drive of the signal electrode with the drive of the scan electrode.The common driver 2 and the segment The display of the driver 3 is controlled by a processor 5 connected to a common bus 4.

The segments 1 to driver 3 each include a frame buffer memory 10 having dual ports, and a data latch circuit 11 composed of at least two stages in series, an input stage and an output stage.
The liquid crystal drive circuit 12 according to the present invention is included.

The frame buffer memory 10 has a port to which display data is supplied from the common bus side under access control of the processor 5, etc., and a port connected to the input terminal of the data latch circuit 11, and controls input/output of data to both ports. is performed by the processor 5.

FIG. 1 shows an example of the liquid crystal drive circuit 12. As shown in FIG.

This liquid crystal drive circuit 12 sets level voltages for driving the liquid crystal display elements to high level sides Vl and V3 for each display frame.
and low level side V2. V4, and the lighting level or non-lighting level of the level voltage at that time is selected based on the display data DATA1 to DATA1], O, and is supplied to the signal electrode. It is driven by

In FIG. 1, 81 to 5110 are liquid crystal displays l.
These are a plurality of output terminals for outputting parallelized display signals to be supplied to the signal electrodes.

Drive buffer D B for each output terminal 81 to 5110
UF1 to DBUFIIO are provided.

Although FIG. 1 typically shows the configuration of the first-stage drive buffer DBUF1 in detail, the rest is the same. The individual output terminals 81 to 5ilo are supplied with a high level voltage Vl for driving the liquid crystal display element to turn on or off.
, V3 and the lower level side level voltage V2. P-channel type MO8FETPI, P2 as an example of a high-level side selection switch element for supplying V4, and N-channel type MO3 as an example of a low-level side selection switch element.
FETNI and N2 are connected.

Switch control of the MO3FETPI and P2 is performed by two-manual type Nantes gates NAI and NA2, which are an example of high-level side selection control gates, and MO3FETNI and N2
The switch control is performed by two-manual NOR gates NRI and NR2, which are examples of low-level side selection control gates. Nantes Gate NAI.

The signal FRM is connected to one input of NA2 via the signal line 20.
-NA is applied, and a signal FRM-NR is applied via the signal line 21 to one input of the NOR gates NRI and NR2. Also, gate NAI.

The other input of NRI is given the normal output of the level shifter LS2, and the gate NA2. The other input of NR2 is given the inverted output of level shifter LS2. The level shifter LS2 level-converts the display data DATA1 and outputs a complementary normal level and an inverted level. For example, if the display data DATAI of logic 1, which means lighting, is 5V, the level shifter LS2 is set to the normal rotation level of 24V and the output voltage of 24V.
If the display data DATA1 of logic O, which means non-lighting, is Ov, the level shifter LS2 outputs the normal level of Ov and the inverted level of 24,V.

The signals FRM-NA and FRM-NR are output from the timing generation circuit TO which inputs the frame switching signal FRM. The reached levels of both the signals FRM-NA and FRM-NR are the same, and the reached levels are alternately changed to high and low levels in synchronization with changes in the frame switching signal FRM. Signal FRM-NA and F
When RM-NR is high level, Nant Gate NAI
Alternatively, NA2 selectively outputs a low level in response to the lighting or non-lighting instruction of display data DATA1, and MO8FET
Level voltage V1 or ■3 is set to terminal S1 by P1 or P2.
supply to. At this time, the NOR gates NRI and NR2 both output low level, and the low level side level voltage V2. V
Do not select 4 at all.

Furthermore, when the signals FRM-NA and FRM-NR are at low level, the NOR gate NRI or NR2 is connected to the display data D.
It selectively outputs a high level in response to an instruction to turn on or off ATAI, and supplies level voltage v2 or ■4 to terminal S1 by MO3FETN1 or N2. At this time, the Nant gates NAI and NA2 both output high level and do not select the high level side level voltages V1 and V3 at all.

In this way, each drive buffer DBUFI to DBUF11
o gates NAI, NA2. NRI and NR2 alternately switch and select the level voltage between the high level side and the low level side according to the level of the frame switching signal FRM, and display the lighting level or non-lighting level of the level voltage to be selected. Let them choose based on data.

At this time, the timing generation circuit TG and the signal FRM
-NA, FRM-NR transmission path connects all drive buffers DBU in synchronization with changes in frame switching signal FRM.
Selection control gate NAI included in FI to DBUFIIO
, NA2. N.R.I.

The level voltage of NR2 is temporarily controlled to a non-selected state.

That is, the base end of the signal line 20 is connected to the output terminal of an AND gate AND1 composed of a two-man NAND gate and an inverter, and the base end of the signal line 21 is connected to
OR gate O consisting of a human gate and an inverter
The output terminal of the RI is coupled, and the terminal end of the signal line 20 is coupled to a folded signal line 22, which is connected to an OR gate O via a waveform type circuit DN20 consisting of an even number of stages of inverters.
The terminal end of the signal line 21 is connected to the folded signal line 23, and the terminal of the signal line 21 is connected to one input of the AND gate AND1 via a delay circuit or waveforming circuit DNIO consisting of an even number of stages of inverters. Combined with the input. AND GATE A N i) 1 and OR GATE ○R1
The output of a level thick LSI that converts the frame switching signal FRM to a level suitable for internal operation is given to the other input of the FRM.

The operation of this drive circuit will be explained with reference to FIG. 4 as well.

In the state before time 1, the signals FRM-NR and FRM-NA have reached the low level, and in this state, MO8FETN1 or N2 is turned on according to the display data DATA1, and the low level side level voltage v2 or ■It is possible to output 4.

When the frame switching signal FRM is changed from a low level to a high level at time t1, the OR gate ORI inverts the level of its output signal FRM-NR, and this change is transmitted from the drive buffer DBUFI to the DBUFI via the signal line 21.
Transferred to IO.

This signal change corresponds to each drive buffer DBUFI~DB.
Noah Gate NRI included in UF110.

It is transmitted to the drive buffer DBUF110 at the end with a delay due to the influence of the input gate capacitance of NR2, the parasitic capacitance of the wiring, the wiring resistance, etc., and it is not until this state is detected by the waveforming circuit DNIO through the folded wiring 23 that it is transmitted to the opposite side. Output signal FRM- of AND gate AND1
The level of NA is inverted (time t2). In this way, when the frame switching signal FRM is inverted to high level, all MOSFETs PI and P2 are cut off until all MO3FETNI and N2 included in drive buffers DBUF1 to DBUF1.10 are cut off. maintain the condition.

When both signals FRM-NR and FRM-NA reach a high level, MOSFET PI or P2 is turned on according to display data DATAI, and it becomes possible to output high-level side level voltage ■1 or ■3. There is.

Next, when the frame switching signal FRM is changed from high level to low level at time t3, AND gate A
ND1 inverts the level of its output signal FRM-NA, and this change is transmitted via signal line 20 from drive buffer DBUF1 to DBUFIIO. This signal change is caused by the respective drive buffers D F3 UF 1 to DBUFIIO
The state is transmitted to the drive buffer DBUFIIO at the end with a delay due to the influence of the input gate capacitance of the Nant gates NAI and NA2 included in the circuit, the parasitic capacitance of the wiring, and the wiring resistance, and this state is transmitted to the waveforming circuit DN20 through the folded wiring 22. Only after detection, the level of the output signal FRM-NR of the OR gate ORI on the opposite side is inverted (
Time t4). In this way, the frame switching signal FRM
When DBU is inverted to low level, the drive buffer DBU
All MOSFETs included in FI~DBUF110
All MO5F until I and P2 are cut off
ETNI and N2 remain cut off.

Therefore, in response to the level inversion of the frame switching signal FRM, MO5FETPI, P2. When the switch states of N1 and N2 are changed, the P-channel type MO8FE
TPI, P2 and N-channel type MO, 5FETNI, N
2 never assume the ON state at the same time, and reliably prevents a through current from flowing from the high level side level voltage to the low level side level voltage during the transient response. For example, time t
Assuming that the last display data DATA1 of one frame up to 3 is at a high level, immediately before time t3, M
O8FETPI is turned on and terminal S1 has 2
When the level of the frame switching signal FRM is inverted in this state where a level voltage of 4V is supplied, this time M
O8FETN2 is selected and a level voltage of Ov is supplied to the output terminal S1. At this time MO8FET
Since MO8FETN2 does not turn on until PI is cut off, no current flows through it from 24V to 0■.

According to the above embodiment, the following effects are obtained.

(1) P of each drive buffer DBUP1 to DBUFIIO
Channel type MO8FETPI, P2 and N-channel type MO8FETNI, N2 are frame switching signals FR.
By reversing the level of M, things that should be turned on are turned off, and then those that should be turned on are turned on, so it is possible to prevent through current from occurring when the switch states of the P-channel type MO8FET and the N-channel type MO8FET are reversed. This can be reliably prevented.

(2) In particular, wasteful power consumption of the entire segment driver, which is a semiconductor integrated circuit with a large number of parallel output signals and a relatively high operating voltage, can be suppressed, making it ideal for battery-powered display devices.

(3) Signals FRM-NA and FRAM-NR are used as a means to feed back the turned-off state of something that should be turned off to the control of the MOSFET that should be turned on.
By using the return wiring 22 and 23, there is no need to secure an operating margin for the amount of delay compared to the case where the transmission time of the return signal is replaced exclusively with gate delay, which simplifies the design and process. This has the effect of eliminating the influence of variations and guaranteeing operational reliability.

FIG. 2 shows another example of a liquid crystal drive circuit.

The example in the figure uses the signals FRM-NA and FRM-NA as in the above embodiment.
Instead of wrapping the RM-NR itself with wiring, the NOR gate N included in the final stage drive buffer DBUFIIO
A NOR gate NR3 that requires the output of RI and NR2 to be powered by two people, and a Nant gate N that requires the output of the Nant gates NAI and NA2 included in the drive buffer DBUFIIO to be powered by two people.
A3 is provided, and the output of the NOR gate NR3 is fed back to the input of the AND gate ANDI, and the output of the NAND gate NA3 is fed back to the input of the OR gate ORI. In this configuration as well, the signal FRM-N
A and FRM-NR are changed with the same timing as in FIG. 4 to prevent the generation of through current.

FIG. 3 shows yet another example of the liquid crystal drive circuit.

In the example shown in the figure, one system of signal FRM-C output from the level shifter LSI is sent to each drive buffer DBUFI to DBU.
This is an example of supplying to the Nant gates NAI, NA2 and Noah gates NRI, NR2 included in FIIO.
I, NR2 are three-man powered, and each Nantes gate NAI,
The added input of NA2 is the NOR gate NR3.
The outputs of the NOR gates NR1, N
The added input of R2 has the said Nantes gate NA3.
The outputs of are connected in common. In this example as well, each drive buffer DBUF1 to DBUF110 (7) P channel type MO8FETPI, P2 and N channel type MO8FE
TNI and N2 turn off what should be turned off by the level inversion of the frame switching signal FRM, and then turn on what should be turned on.
It is possible to reliably prevent a through current from occurring when the switch state of the 5FET is reversed.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. .

For example MO5FETPI, P2 and N4. The selection control gate that switches and controls N2 is not limited to the Nant gate and the Norr gate, and can be changed as appropriate.The key is to have logic that can drive the liquid crystal display element in an alternating current manner based on the frame switching signal FRM and display data. Bye. Also,
The number of drive buffers and the number of display signal output terminals can also be changed as appropriate. Furthermore, in the configuration of FIG. 1, the waveforming circuits DNIO and DN20 can be omitted. Furthermore, in the configuration shown in FIG. 2, the drive buffer coupled to the input of the NOR gate NR3 and the NAND gate NA3 is not limited to the one at the final stage, and other gates that can manage the delay time are connected to the NOR gate NR3 and the NAND gate 1-N A 3
It may be placed at any position as long as it is interposed on the input or output side of the input or output side.

In the above explanation, the invention made by the present inventor was mainly applied to a dedicated segment driver implemented in a semiconductor integrated circuit, which is the background field of application, but the present invention is not limited thereto. The present invention can also be applied to a single-chip microcomputer with a built-in liquid crystal drive circuit. The present invention can be applied at least to conditions where a liquid crystal display element is driven in an alternating current manner.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, when switching between a high-level level voltage and a low-level level voltage used for alternating current driving of a liquid crystal display element, the operations of the first circuit and the second circuit for controlling the switching of the level voltage are controlled, respectively. By temporarily controlling both level voltages to a non-selected state using a control signal that is phase-controlled or a control signal that has a predetermined logical value based on an operation delay or logic operation, it is possible to This has the effect of suppressing the generation of through current from the high level side to the low level side.

By using the delay of the folded wiring to obtain a predetermined phase difference between the selection control signals for the first circuit and the second circuit, the delay time is reduced compared to the case where the logic operation of the gate or the operation delay is used. This eliminates the need to set an operating margin for the current, contributes to a reduction in the number of circuit elements, and makes it possible to easily and reliably prevent the occurrence of the through current.

In addition, it is possible to suppress wasteful power consumption of the entire liquid crystal drive circuit, which is a semiconductor integrated circuit with a large number of parallel output signals and a relatively high operating voltage, and is optimized for battery-powered liquid crystal display devices. be able to.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a liquid crystal drive circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the liquid crystal drive circuit, and FIG. 3 is a circuit diagram of yet another embodiment of the liquid crystal drive circuit. FIG. 4 is a timing chart for explaining the operation of the liquid crystal drive circuit shown in FIG. 1, and FIG. 5 is a block diagram of a segment driver implemented as a semiconductor integrated circuit to which the liquid crystal drive circuit is applied, and a display system to which the same is applied. FIG. 6 is a partial circuit diagram of an example of a conventional liquid crystal drive circuit. 1...Liquid crystal display, 2...Common driver, 3
...Segment driver, 10-mount frame buffer memory, 11...Data latch circuit, 12...Liquid crystal drive circuit, Vl, V3...High level side level voltage, V2
．． V4...Low level side level voltage, DATAI~DA
TA110--Display data, 81-5110--Display signal output terminal, DBUFI-DBUFIIO--Drive buffer, PL, P2--P channel type MO8F
ET (high level side selection switch element), Nl, N2・
・・N-channel type MO5FET (low level side selection switch element), NAI, NA2 ・Nant gate (high level side selection gate), NR1゜NR2...Nor gate (low level side selection gate), TG...timing generation Circuit, FRM...Frame switching signal, FRM-
NA, FRM-NR...signal, NR3...Nor gate, NA3...Nant gate.

Claims (1)

[Claims] 1. Alternately selecting the level voltage for driving the liquid crystal display element between the high level side and the low level side according to the level change of the clock signal, and selecting the level voltage to be selected. A liquid crystal drive circuit that selects a lighting level or a non-lighting level based on display data and outputs display signals to be supplied to signal electrodes of a matrix type liquid crystal display in parallel, a first circuit for selective control; a second circuit for selectively controlling a level voltage on the low level side; and a temporary non-selection state of both the first circuit and the second circuit in response to a level change of the clock signal. A liquid crystal drive circuit comprising: signal generation means for performing phase control to generate operation control signals for the first circuit and the second circuit. 2. Multiple output terminals for outputting parallel signals to be supplied to the signal electrodes of the matrix type liquid crystal display, and high level side level voltage and low level voltage for driving the liquid crystal display element to turn on and off. a high level side selection switch element and a low level side selection switch element for supplying level side level voltages to respective output terminals; and a high level side selection switch element and a low level side selection switch element for supplying level side level voltages to respective output terminals; A high level side selection control gate and a low level side selection control gate that switch and select between the high level side and the low level side, and select the lighting level or non-lighting level of the level voltage to be selected based on display data. and causing the high level side selection control gate and the low level side selection control gate to mutually change one of them to a non-selected control state and then change to the other selected control state in accordance with a level change of the clock signal. a signal generating means for generating a phase-controlled switching control signal for both selection control gates based on a clock signal to allow the selection control gate. 3. The signal generation means includes a first signal generator coupled to a control terminal of a high level side selection control gate.
a second wire coupled to the control terminal of the low level side selection control gate;
wiring; a first folded wiring for folding back and extending the first wiring towards the driving end side of the second wiring; a second folding wiring for folding and extending the second wiring towards the driving end side of the first wiring; and the clock signal. a first gate circuit that inputs the clock signal and the signal from the second folded wiring and provides an output to the first wiring; and a first gate circuit that receives the clock signal and the signal from the first folded wiring and provides an output to the second wiring. 3. The liquid crystal drive circuit according to claim 2, comprising: a two-gate circuit. 4. Alternately select the level voltage for driving the liquid crystal display element between the high level side and the low level side according to the level change of the clock signal, and set the lighting level or non-lighting level of the level voltage to be selected. A liquid crystal drive circuit that selects a level based on display data and outputs display signals to be supplied to signal electrodes of a matrix type liquid crystal display in parallel, the first circuit selectively controlling a level voltage on the high level side. a second circuit that selectively controls a level voltage on the low level side; a first detection circuit that detects a change to a non-selected control state of the first circuit based on its output; and a non-selected control state of the second circuit. a second detection circuit that detects a change in the state based on its output; a first logic circuit that inverts the second circuit to a selected control state based on the detection result of the first detection circuit; a second logic circuit that inverts the first circuit to a selected control state based on a detection result. 5. Alternately select the level voltage for driving the liquid crystal display element between the high level side and the low level side according to the level change of the clock signal, and select the lighting level or non-lighting level of the level voltage to be selected. A liquid crystal drive circuit that selects a level based on display data and outputs display signals to be supplied to signal electrodes of a matrix liquid crystal display in parallel, the first circuit selectively controlling a level voltage on the high level side. a second circuit that selectively controls the level voltage on the low level side; and a second circuit that detects the output change to the non-selected control state of the first circuit.
a third logic circuit that inverts the circuit to a selected control state; and a first logic circuit that detects a change in the output of the second circuit to a non-selected control state.
A liquid crystal drive circuit comprising: a fourth logic circuit that inverts the circuit to a selected control state; 6. an external terminal for inputting the display data; a dual-port buffer memory for storing display data supplied from the external terminal through one port; and a dual-port buffer memory for storing display data supplied from the external terminal through the other port; 6. A semiconductor integrated circuit comprising: a latch circuit that holds display data and outputs it at a predetermined timing; and a liquid crystal drive circuit according to claim 1, which receives an output of the latch circuit.