JPH0473650B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to an echo removal method and apparatus capable of removing asymmetric components of positive and negative transmitted pulses for realizing two-wire bidirectional data transmission. (Prior art and its problems) An echo canceller is known as a well-known technology for realizing two-wire bidirectional data transmission using paired wires. The echo canceller operates to suppress echo by using an adaptive digital filter to generate a pseudo echo (echo replica) corresponding to a transmission data sequence corresponding to the length of the echo impulse response. At this time, each tap coefficient of the adaptive digital filter is successively corrected by correlating the error signal obtained by subtracting the echo replica from the echo with the transmitted data. now,
When targeting baseband data transmission, AMI (Altenate Mark) is generally used as the transmission path code.
A code with good DC balance, such as an inversion code or a biphase code, is used. for example
In the AMI code, in unipolar/bipolar conversion, when the binary value is "0", a 0 level is output, and when the binary value is "1", pulses of +V level and -V level (however, V > 0) are output alternately. is assigned to. +V level positive pulse and -
Ideally, the pulse waveform of the V level negative pulse should be symmetrical, but in reality, the positive symmetry is slightly distorted. At this time, in an echo canceller using a conventional adaptive digital filter, which assumes symmetry of the positive and negative pulse waveforms, the existence of the asymmetric component of the positive and negative pulses causes an increase in the residual echo level, and the desired degree of echo suppression can be achieved. becomes impossible to obtain. That is, if we pay attention to the convergence of the n-th tap coefficient of the adaptive digital filter, the magnitude of the impulse response of the echo at the corresponding time point is +V' for positive pulses and -(V'+β) for negative pulses. ) (where β
≠), the coefficient of the nth tap is {V′+(V′+β)}/
It will converge to 2=V'+β/2. Therefore,
The nth tap coefficient will cause an error of β/2. This fact holds true for all tap coefficients, so if the sent pulses are asymmetrical, the residual echo level will increase, making it impossible to obtain the desired degree of echo suppression. For example, when implementing baseband data transmission using a pair of telephone lines installed between a station and a subscriber, an echo suppression level of about 50 dB is required. 50dB
In order to obtain a degree of echo suppression of , it is necessary to achieve symmetry between positive and negative pulses with an accuracy of 99.997% or higher. In order to realize a circuit for generating positive and negative pulses with such highly accurate symmetry, a complex circuit is required, and there are many adjustment points in the circuit. Therefore, the circuit size increases and a large number of man-hours are required for circuit adjustment, resulting in an increase in cost. (Object of the Invention) An object of the present invention is to provide a method and apparatus for removing asymmetric components of positive and negative pulses of an echo canceller, which has a small circuit scale and does not require circuit adjustment.
In other words, in the pulse generation circuit, for ease of implementation, the accuracy of the symmetry of the generated positive and negative pulses is set to 99%.
It is allowed to occur to a certain extent. Under such conditions, the conventional echo canceller device produces a large residual echo after removing the echo, making it impossible to obtain the required degree of echo suppression. Therefore, an object of the present invention is to obtain a desired degree of echo suppression by generating a pseudo echo taking into account the asymmetry of positive and negative pulses. (Structure of the Invention) According to the present invention, echoes leaking from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire/4-wire conversion circuit are suppressed using pseudo echoes generated by an adaptive filter with multiple taps. An echo cancellation method comprising: a plurality of first tap outputs that receive transmission data and provide a plurality of delays of the transmission data period units; and an output pulse generated by the transmission circuit based on the transmission data. A plurality of second tap outputs which receive a polarity signal representing the polarity and which provide a plurality of delays in units of the transmitted data period, generate a plurality of tap coefficients, and generate a plurality of tap coefficients corresponding to each of the tap coefficients. When obtaining the pseudo echo by summing the products with the plurality of first tap outputs, in generating the tap coefficient, A tap coefficient of 1 is held, a correction coefficient corresponding to the other polarity signal is held in response to the second tap output, and a second tap coefficient is obtained by adding the first tap coefficient and the correction coefficient. After getting
receiving the second tap output, selecting either the first or second tap coefficient to generate the tap coefficient, and determining a difference signal between the pseudo echo and the received signal;
Based on a correlation value between the polarity of the difference signal and the polarity of the pseudo echo, if the correlation value is smaller than a predetermined value, the correlation between the difference signal and the first tap output is calculated; The retained first tap coefficient and the retained correction coefficient are individually adapted in correspondence with the polarity signal, and when the correlation value is greater than or equal to a predetermined value, the retained first tap coefficient and the retained correction coefficient are individually adapted. An echo cancellation method is obtained, which is characterized in that the adaptation of the correction coefficients is stopped. Further, according to the present invention, the 4 wires of the 2-wire/4-wire conversion circuit
An echo canceling device that suppresses echoes leaking from a transmitting circuit to a receiving circuit on the line side using pseudo echoes generated by an adaptive filter with multiple taps, which receives transmitted data and suppresses echoes leaking from the transmitting circuit to the receiving circuit. a plurality of first tapped delay circuits that provide a delay of , and a polarity signal representing the polarity of an output pulse generated based on the transmission data in the transmission circuit, and provides a plurality of delays in units of the transmission data period. a second tapped delay circuit; and the first and second tapped delay circuits;
a plurality of tap coefficient generating circuits receiving outputs from the same tap position of each of the tapped delay circuits; a plurality of product circuits; an adder for adding outputs of the plurality of product circuits to obtain the pseudo echo; a subtracter for obtaining a difference signal between the pseudo echo and the received signal; A correlator for obtaining a correlation value between the polarity of the signal and the polarity of the pseudo echo; and the output of the correlator is compared with a predetermined value, and the result is transmitted to the plurality of tap coefficient generating circuits. means for receiving a tap output from the second tapped delay circuit in the tap coefficient generating circuit and holding a first tap coefficient corresponding to either one of the polarity signals; , means for receiving the tap output of the second tapped delay circuit and holding a correction coefficient corresponding to the other polarity signal; and adding the first tap coefficient and the correction coefficient to obtain a second tap coefficient. means for receiving the tap output of the second tapped delay circuit and selecting either the first or second tap coefficient as the output of the tap coefficient generating circuit; and the determining circuit. If it is determined that the output of the correlator is smaller than a predetermined value, the correlation between the difference signal and the first tapped delay circuit is obtained by the means for holding the first tapped coefficient. and means for individually adapting the obtained first tap coefficient and the correction coefficient obtained by the means for holding the correction coefficient, respectively, in correspondence with the polarity signal, and the determination circuit is configured to adjust the output of the correlator. There is obtained an echo canceling device characterized in that, when it is determined that the correction coefficient is equal to or greater than a predetermined value, adaptation of the correction coefficient obtained by the means for holding the correction coefficient is stopped. (Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Now, the circuit shown in Figure 1 consists of two-wire transmission line 1
It is assumed that the two terminals are connected to each other via the terminals 6 and 6. For subscriber cables, one is installed on the central office side and the other on the subscriber side. Here, in order to simplify the explanation, baseband data transmission will be assumed and FIG. 1 will be explained as a subscriber side circuit.
Furthermore, in the embodiment of the present invention shown in FIG. 1, an AMI code will be explained as a transmission line code, but
As will be described later, the present invention is also applicable to other transmission line codes. In FIG. 1, a binary code series 12 supplied to an input terminal 1 is transmitted to a code conversion circuit 3 which is a transmitting circuit.
and adaptive digital filter (ADF)
6 is input. The code conversion circuit 3 converts the binary code into an AMI code and outputs it. That is, the binary code "0" has a function of outputting a zero level, and the binary code "1" has a function of outputting positive pulses and negative pulses alternately in the order of occurrence of the "1". At this time, the code bit 13, which indicates in binary terms whether a positive pulse or a negative pulse was output with respect to the binary code "1", is supplied to the adaptive digital filter 6. It is assumed here that the values "0" and "1" of the sign bit correspond to positive pulses and negative pulses, respectively. Further, the pulse width of the positive and negative pulses is usually selected to be T/2. Here, T is the data rate of the binary code sequence 12, and the unit is seconds. The output of the code conversion circuit 3 is sent to a two-wire transmission line 16 via a hybrid transformer (HYB) 4. On the other hand, a signal sent from the station is input to a low pass filter (LPF) 5 via a two-wire transmission line 16 and a hybrid transformer 4. Here the hybrid
Due to circuit failure or impedance mismatch in the transformer 4, the output signal of the code conversion circuit 3 becomes an echo, which appears at the output of the hybrid transformer 4. That is, the input signal to the reduction pass filter 5 is a mixed signal containing a received signal and an echo. Reduction passing filter 5
serves to remove noise existing in high frequencies other than the required band. Adaptive digital filter 6, D/A converter (DAC) 7, subtracter 8,
A closed-loop circuit consisting of a sample-and-hold circuit (SH) 9, an analog-to-digital converter (ADC) 10, and a multiplier 17 for multiplying by a constant 2α adapts the reduced pass filter 5 by adaptively generating an echo replica 15. It operates to suppress echo components contained in the output mixed signal. Here, the adaptive digital filter 6 is
An adaptive operation is performed to reduce the level of the error signal 14 obtained by weighting the output of the A/D converter 10 by a constant 2α. On the other hand, the sign bit 18 of the echo replica 15, which is the output signal of the adaptive digital filter 6, and the sign bit 19 of the output of the A/D converter 10 are both supplied to the correlator 20, and the correlation between both input signals is calculated. Ru.
The output of the correlator 20 passes through a determination circuit 21, becomes a determination output 22, and is supplied to the adaptive digital filter 6. The determination circuit 22 functions to output "1" when the absolute value of the code supplied as input is smaller than a certain predetermined value, and output "0" when it is larger. Therefore, the determination output 22 is a binary value. The role of the determination output 22 in the adaptive digital filter 6 will be explained in detail later. Figure 1 assumes AMI code,
Since the signal band can be considered to be approximately 1/THz, the sampling frequency of the adaptive digital filter 6 may be 2/THz. Along with this,
The sampling frequency of the D/A converter 7, sample hold circuit 9, and A/D converter 10 must also be 2/THz. When the adaptive digital filter 6 is in a converged state, the echo signal at the output of the sample and hold circuit 9 is sufficiently suppressed compared to the received signal, and the receiving circuit 11
is supplied to In the receiving circuit 11, after compensating for line loss, the AMI code is input to the identification circuit, where the AMI code is converted into a binary code and appears at the output terminal 2. Next, the adaptive digital filter 6 will be explained in detail. FIG. 2 is a block diagram showing an example of the configuration of the adaptive digital filter 6 of FIG. 1. In the figure, it is assumed that the part surrounded by the dotted line indicated by the reference numeral 100' and the part surrounded by the dotted line indicated by the reference numeral 100'' have exactly the same functional blocks.Reference numerals 14, 15 and 22
correspond to the signals indicated by the same reference numerals in FIG. 1, and indicate the error signal, echo replica, and decision output, respectively. Here, the sampling frequency of the error signal 14 and the echo replica 15 are both 2/T.
It is Hz. Therefore, the switch shown in FIG. 2 decomposes the error signal 14 into two error signals 14' and 14'' with a sampling frequency of 1/THz. 15' and 15'' are interleaved by a switch and the sampling frequency is 2/THz.
This becomes echo replica 15. In the example in Figure 2,
A transversal filter with N (positive integer) taps is shown. Here, N is determined by the impulse response length of the echo. It is an integer value. Reference numbers 100' and 100'' have equivalent functions, so here we will focus on the part with reference number 100' and explain its operation.Each tap coefficient of the filter is generated by coefficient generation circuits 151, 152, ..., 15N-
Generated at 115N. The binary code series 121 and code bits 131 shown in FIG.
Delay elements 101 and 11 correspond to reference numerals 12 and 13 in the figure and provide a delay of T seconds, respectively.
1. Delay element 1 giving a delay of T seconds
01, 103, ..., 10N-1 are connected in series in this order, and N binary code sequences 12i (i = 1, 2, ..., N) are input and output from each tap.
is supplied to the signed data generation circuit 18i.
Similarly, delay element 111,1 giving a delay of T seconds
12,..., 11N-1 are also connected in series in this order, and the N sign bits 13i (i=1, 2,..., N), which are the input and output of each tap, are connected to the signed data generation circuit 18i and the coefficients, respectively. Generation circuit 15
i. Here, signed data generation circuit 1
8i is a binary code sequence 12i and code bit 13
This is a circuit for generating signed data 19i from i. As previously assumed, sign bit 13
Since the values "0" and "1" of i indicate positive and negative, respectively, the signed data 191 is expressed as shown in Table 1.

[Table] On the other hand, multipliers 141, 142,..., 14N-
All of the outputs of 1 and 14N are supplied to an adder 170 to become an echo replica 15' and supplied to the switch. Further, the error signal 14' is transmitted to the coefficient generation circuit 1
51, 152, . . . , 15N-1, 15N. Furthermore, the determination output 22 corresponds to the signals with the same numbers in FIG. 1, and is similarly supplied to the coefficient generation circuits 151, 152, . . . , 15N-1, 15N. Coefficient generation circuit 15i (however, i=1,
2, . . . N), the coefficients are successively modified based on the values of the four types of signals supplied, namely, the signed data 19i, the sign bit 13i, the error signal 14', and the judgment output 22. Each coefficient 16i obtained by the coefficient generation circuit 15i is converted into signed data 1 by the multiplier 14i.
After being multiplied by 9i, the signal is supplied to an adder 170.
The operation of the block designated by the reference numeral 100'' is exactly similar to the block designated by the reference numeral 100', but
It should be noted that these phases are shifted by T/2 seconds. Next, the coefficient generation circuit 15i will be explained in detail. FIG. 3 is a block diagram showing an example of the configuration of the coefficient generating circuit 15i of FIG. 2. In the figure, the part surrounded by the dotted line is the coefficient generation circuit 15i in FIG.
Furthermore, its input/output signals, such as error signal 14', signed data 19i, sign bit 13i, judgment output 22, and coefficient 16i, respectively correspond to the signals indicated by the same reference numerals in FIG. are doing. In Figure 3, error signal 1
4' and the signed data 19i are multiplied by a multiplier 200, and the multiplication output is applied to an AND gate 600.
is supplied as one input of and at the same time
It is also supplied as one input of gate 601.
On the other hand, the sign bit 13i is a signal indicating the polarity of the signed data 19i input at the same time, and it is assumed that when the sign bit is "0" it corresponds to positive and when it is "1" it corresponds to negative. There is. Sign bit 13i is input as a selection signal to selection circuit 300, and at the same time, it is input to NAND gate 700 and AND gate 8.
00. Further, the output of AND gate 800 is supplied as one input of AND gate 601. On the other hand, the judgment output 22 is supplied as an input to one of the NAND gate 700 and the AND gate 800. Further, the output of the NAND gate 700 is connected to the AND gate 6, respectively.
00 as one input. Here, a delay element 400 and an adder 5 giving a delay of T seconds
The closed loop circuit consisting of 00 is a circuit for generating coefficients corresponding to positive pulses, and the adder 5
Successive corrections are made by the output of AND gate 600, which is fed to 00. On the other hand, a closed loop circuit consisting of a delay element 401 that provides a delay of T seconds and an adder 501 is a circuit for generating a correction coefficient corresponding to a negative pulse, and the adder 501
The successive corrections are made by the output of AND gate 601, which is supplied to . Furthermore, the delay element 400
The output of is supplied to adder 900. adder 90
0 is also supplied with the output of the delay element 401,
The sum with the output value of the delay element 400 is calculated. This sum indicates a coefficient corresponding to a negative pulse and is supplied as one input of the selection circuit 300.
According to an embodiment of the invention, the output of delay element 400 is a tap coefficient corresponding to the positive pulse of the transmission;
The output of adder 900 is the tap coefficient corresponding to the negative pulse of the transmission. Here, the present invention is characterized in that the tap coefficient corresponding to the negative pulse is obtained by correcting the value of the tap coefficient corresponding to the positive pulse. Next, the role of the determination output 22 shown in FIG. 3 will be explained in detail with reference to FIG. 1. Considering the absolute value of the output of the correlator 20 in FIG.
The value during the convergence process of the adaptive digital filter is larger than the value at the time of convergence. This is because, during the convergence process, code bits 18 and 19 input to the correlator have a strong correlation, but at the time of convergence, the degree of correlation between the two becomes extremely small. Therefore, if the determination circuit 21 is configured to output "1" when the absolute value of the output of the correlator 20 is smaller than a predetermined value, and output "0" when it is larger, Judgment output 2
When the value of 2 is "1", it means that the echo canceller has converged, and when the value is "0", it means that the echo canceller is in the process of convergence. Now, in FIG. 3, when the judgment output 22 is "0", that is, when the echo canceller is in the convergence process, the output of the NAND gate 700 is "1", so the output of the multiplier 200 is the AND gate. 600 directly to adder 500. Therefore, delay element 400 and adder 5
In a closed loop consisting of 00, sign bit 13
Adaptation takes place regardless of the value of i. On the other hand, since the output of the AND gate 601 is "0" and therefore one of the inputs of the adder 501 is "0", the closed loop circuit consisting of the delay element 401 and the adder 501 cannot adapt. It becomes stopped. For example, if the initial value of the delay element 401 is zero, the output value of the adder 900 supplied as one input of the selection circuit 300 will be the same as the output value of the delay element 400 supplied as the other input of the selection circuit 300. The values will be the same. Therefore, the value of coefficient 16i is equal to the value of sign bit 13i input as a selection signal.
It is unrelated to the value "0" or "1". Therefore, when the echo canceller is in the convergence state, convergence is performed without distinction between positive and negative pulses. Next, as the echo canceller converges, the determination output 22 changes from "0" to "1". At this time, and gate 6
00 and the NAND gate 700, the output of the AND gate 600 has meaning only when the sign bit 13i is "0", that is, a positive pulse. In the closed-loop circuit consisting of , adaptation takes place only for positive pulses. Further, when the judgment output 22 is "1", in the logic circuit consisting of AND gates 601 and 800, the sign bit 13i
Since the output of the AND gate 601 has meaning only for negative pulses, as described above, the closed loop circuit consisting of the delay element 401 and the adder 501 can only be adapted for negative pulses. It is done. In the selection circuit 300, in accordance with the value of the sign bit 13i inputted as a selection signal, when the sign bit 13i is "0", the output of the delay element 400 is selected and appears as a coefficient 16i. Further, when the sign bit 13i is "1", the adder 900
The output of is selected and appears as coefficient 16i.
Note that the closed loop circuit consisting of the delay element 401 and the adder 501 serves to generate a value that corrects the asymmetric component of the positive and negative sent pulses, and the tap coefficient corresponding to the negative pulse is the same as the tap coefficient corresponding to the positive pulse. obtained by adding this correction value. As described in detail above, the coefficient generation circuit 15i
has a first coefficient corresponding to one polarity of the transmitted pulse and a correction coefficient corresponding to the other polarity, and each adaptation method can be switched depending on the degree of convergence of the echo canceller. It is possible to solve the problem of echo suppression caused by the asymmetry of positive and negative pulses without unnecessarily lengthening the time. In addition, in the embodiment of the present invention, the transmission line code is
Although the explanation has been made assuming an AMI code, the present invention is also effective for binary codes such as bi-phase codes. This case can be realized by modifying the embodiment as follows, for example. In FIG. 1, the binary code sequence 12 of the signals input to the adaptive digital filter is omitted. Accordingly, since the signal 121 in FIG. 2 becomes unnecessary, the delay elements 101, 102, . . . , 10N-1 are omitted. Therefore, the signed data generators 171, 172,...,
At the same time as omitting 17N, signed data 19i
uses the same code bit as the sign bit 13i. Similarly, in FIG. 3, the signed data 19i is the same as the sign bit 13i. Finally, in order to change the sampling rate of the adaptive digital filter 6 according to the signal band of the adopted transmission code, it is sufficient to prepare as many circuits as shown by the dotted line in Fig. 2. . It is clear that the present invention can also be applied to binary codes such as bi-phase codes by performing the above modification operations. In one embodiment of the present invention shown in FIG. 1, the line loss compensation function, which is part of the function of the receiving circuit 11, is
It is also possible to insert it between the reduced pass filter 5 and the adder 8. Of course, it is also possible to reduce the number of bits of the A/D converter 10 to 1 bit. Furthermore, it is also possible to arrange the sample and hold circuit 9 immediately before the receiving circuit 11. Also, instead of omitting the sample and hold circuit 9,
A reducing pass filter can also be inserted between the D/A converter 7 and the subtracter 8. Furthermore, it is also possible to replace the adaptive digital filter 6 with an adaptive analog filter. In this case, the D/A converter 7, sample hold circuit 9, and A/D converter 10 are omitted. (Effects of the Invention) As described above in detail, according to the present invention, each tap coefficient of the adaptive filter includes a first coefficient corresponding to one polarity of the sending pulse;
By preparing correction coefficients corresponding to the other polarity and switching each adaptation method according to the degree of convergence of the echo canceller, the convergence time can be avoided unnecessarily, and the problem caused by the asymmetry of the positive and negative pulses can be corrected. This can prevent deterioration of the echo suppression degree. Therefore, since no complicated circuit is required to generate positive and negative pulses, it is possible to provide an echo canceller with a small circuit scale and no circuit adjustment required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference numerals 1 and 2 are an input terminal and an output terminal, respectively, reference numeral 3 is a code conversion circuit, reference numeral 4 is a hybrid transformer,
Reference numeral 5 is a reducing pass filter, reference numeral 6 is an adaptive digital filter, reference numeral 7 is a D/A converter, reference numeral 8 is a subtracter, reference numeral 9 is a sample and hold circuit, reference numeral 10 is an A/D converter, Reference numeral 11 is a receiving circuit, reference numeral 12 is a binary code series, reference numeral 13 is a code bit, reference numeral 14 is an error signal, reference numeral 15 is a pseudo echo, reference numeral 16 is a two-wire transmission line, reference numeral 17 is a multiplication Reference numerals 18 and 19 are both sign bits, Reference numeral 20 is a correlator, Reference numeral 21
Reference numeral 22 indicates a judgment circuit, and reference numeral 22 indicates a judgment output. FIG. 2 is a detailed block diagram showing an example of the configuration of the adaptive digital filter 6 shown in FIG.
..., N-1) is a delay element, reference number 14i (where i=1, 2,...N) is a multiplier, reference number 15i is a coefficient generation circuit, reference number 170 is an adder, reference number 18i is signed data. Each generation circuit is shown. FIG. 3 shows the coefficient generation circuit 15i in FIG.
This shows the detailed block of
00 is a multiplier, reference numeral 300 is a selection circuit, reference numerals 400 and 401 are delay elements, reference numeral 50
0 and 501 are adders, reference numbers 600, 601
and 800 represent an AND gate, reference numeral 700 represents a NAND gate, and reference numeral 900 represents an adder.

Claims (1)

[Claims] 1. Echo cancellation that suppresses echoes leaking from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire/4-wire conversion circuit by using pseudo echoes generated by an adaptive filter with multiple taps. a plurality of first tap outputs that receive transmission data and provide a plurality of delays of the transmission data period units; and a polarity of an output pulse generated by the transmission circuit based on the transmission data. It receives a polarity signal and receives a plurality of second tap outputs that provide a plurality of delays in units of the transmission data period, generates a plurality of tap coefficients, and generates a plurality of tap coefficients corresponding to each of the tap coefficients. When the pseudo echo is obtained by summing the products of the first tap output and the first tap output, in generating the tap coefficient, the first tap corresponding to one of the polarity signals receiving the second tap output holding a correction coefficient corresponding to the other polarity signal in response to the second tap output, and adding the first tap coefficient and the correction coefficient to obtain a second tap coefficient. rear,
receiving the second tap output, selecting either the first or second tap coefficient to generate the tap coefficient, and determining a difference signal between the pseudo echo and the received signal;
Based on a correlation value between the polarity of the difference signal and the polarity of the pseudo echo, if the correlation value is smaller than a predetermined value, the correlation between the difference signal and the first tap output is calculated; The retained first tap coefficient and the retained correction coefficient are individually adapted in correspondence with the polarity signal, and when the correlation value is greater than or equal to a predetermined value, the retained first tap coefficient and the retained correction coefficient are individually adapted. An echo cancellation method characterized in that adaptation of correction coefficients is stopped. 2. An echo cancellation device that suppresses echoes leaking from the transmitting circuit to the receiving circuit on the 4-wire side of a 2-wire/4-wire conversion circuit by using pseudo echoes generated by an adaptive filter with multiple taps, the transmitter a first tapped delay circuit that receives data and provides a plurality of delays in units of the transmission data period; and a first tapped delay circuit that receives data and provides a plurality of delays in units of the transmission data period; a second tapped delay circuit that provides a plurality of unit delays; a plurality of tap coefficient generation circuits that receive outputs from the same tap position of each of the first and second tapped delay circuits; a plurality of product circuits for obtaining the product of the output of the circuit and the tap output of the first tapped delay circuit; and an adder for adding the outputs of the plurality of product circuits to obtain the pseudo echo. a subtracter for obtaining a difference signal between the pseudo echo and the received signal; a correlator for obtaining a correlation value between the polarity of the difference signal and the polarity of the pseudo echo; and a correlator for receiving the output of the correlator. a determination circuit for comparing the magnitude with a predetermined value and supplying the result to the plurality of tap coefficient generation circuits, in the tap coefficient generation circuit, the tap output of the second delay circuit with taps; means for receiving the tap output of the second tapped delay circuit and holding a first tap coefficient corresponding to one of the polarity signals; and means for receiving the tap output of the second tapped delay circuit and holding a correction coefficient corresponding to the other polarity signal. and means for obtaining a second tap coefficient by adding the first tap coefficient and the correction coefficient; means for selecting one of the two as the output of the tap coefficient generation circuit; A first tap coefficient obtained by the means for holding the first tap coefficient and a correction coefficient obtained by the means for holding the correction coefficient are made to correspond to the polarity signal. and means for individually adapting the correction coefficients obtained by the means for holding the correction coefficients when the determination circuit determines that the output of the correlator is equal to or greater than a predetermined value. An echo canceling device characterized by stopping oxidation.