JPH0472818A - Serial/parallel analog/digital converter - Google Patents

Abstract

PURPOSE:To obtain a serial parallel A/D converter with high speed and high accuracy suitable for monolithic IC with simple constitution by comparing a voltage divided by a voltage division means with a voltage selected by a 2nd selection means to apply low-order A/D conversion. CONSTITUTION:The A/D converter is provided with a differential conversion circuit array 1 comprising plural differential conversion circuits numbered in order of levels of reference voltages to apply subtraction and differential amplification to an analog input signal and each reference voltage. Moreover, a selection means to select a specific output current among plural output currents and a switch means 7 to switch the selected output current and to supply it to a load resistor are provided to generate a voltage required for low-order A/D conversion. Furthermore, the low-order A/D conversion is implemented by comparing an output voltage selected by a selection means selecting a specific output voltage from voltages generated across a load resistor with a voltage divided by a voltage division means 10 dividing the output voltage of the load resistor. Thus, the serial/parallel A/D converter with high speed and high accuracy suitable for monolithic IC with simple constitution is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a series/parallel type analog-to-digital converter.

Conventional technology FIG. 8 shows a typical conventional series-parallel type A/D converter.

The analog input signal 2 is roughly subjected to upper A/D conversion in the upper A/D conversion circuit 13 to produce an upper A/D conversion converter cuff. Furthermore, this upper A/D conversion output is D/A converted by the D/A conversion circuit 14 and returned to an analog voltage.
The subtracter 15 performs subtraction and amplification between the analog input signal 2 and the output of this D/A conversion, and this subtracted amplified output is further finely converted into a lower A/D in the lower A/D conversion circuit 16. /D conversion output 12 is obtained.

Such a series/parallel type A/D converter has the advantage that the circuit scale is extremely small compared to the conventionally used parallel type A/D converter. For example, in a configuration with a resolution of 10 bits, the number of comparators is extremely small to one-sixteenth, making it possible to significantly reduce power consumption and depth size.

Problems to be Solved by the Invention However, in such a conventional series-parallel type A/D converter, the gain and offset voltage of the subtracter 15 are not controlled by the lower A/D converter.
It is necessary to accurately match the full scale voltage and offset voltage of the D conversion circuit 16, and the internal D/
Since it is necessary to match the full-scale voltage and offset voltage of the A conversion circuit 14, there are many adjustment points, and the conversion accuracy lacks stability, making monolithic implementation particularly difficult.

The difficulty in satisfying the DC precision of such a conventional series/parallel type A/D converter will be explained in more detail using FIG. 9.

FIG. 9 shows the voltage relationship of each part of the series-parallel type A/D converter shown in FIG.

The first required voltage accuracy is the relative accuracy between the reference voltage of the upper A/D conversion circuit and the output voltage of the D/A conversion circuit. From the principle of conversion, suppose that when the analog input signal Vin is greater than the reference voltage Vr,i of the upper A/D converter circuit and smaller than r,i+1, the output of the D/A converter circuit generates Vd,i. , the error between these two voltages △Vo,i (-
Vd, 1-Vr, i) usually needs to satisfy the final accuracy of a serial-parallel type A/D converter. For example, in the case of a 10-bit viscosity A/D converter, this voltage error △■o, i is D/
0.05% of the full scale voltage of the A conversion circuit output
accuracy is required. This kind of accuracy is difficult to achieve without some kind of voltage adjustment means, and moreover,
It is desirable that the reference voltage of the conversion circuit can be varied by an external signal, but even if certain conditions are satisfied, when the reference voltage is varied by an external signal, it is more difficult to follow this signal and ensure accuracy.

The second required voltage accuracy is the relative accuracy between the voltage obtained by multiplying the unit voltage of the output voltage of the D/A conversion circuit by the gain of the subtracter and the reference voltage of the lower A/D conversion circuit.

Now let us consider the gain of the subtracter, the unit voltage of the output voltage of the D/A conversion circuit as Vu (= Vd, i+1-Vcl, i), and the full-scale voltage of the reference voltage of the lower A/D conversion circuit as vf.
S, the error between these two voltages Δ■02(2■f
s-Vu) must have an accuracy at least commensurate with the resolution of the lower A/D converter circuit; for example, if the lower A/D converter circuit has a resolution of 5 bits, ΔVo2 is the full-scale voltage Vfs of the lower A/D converter circuit. It is necessary to set the value within 1.5%. This is not necessarily easy because it is necessary to match three variables: the unit voltage Vu of the output voltage of the D/A conversion circuit, the gain K of the subtracter, and the full-scale voltage Vfs of the lower A/D conversion circuit.

The offset voltage of the [k subtracter is also a series-parallel type A/D.
It is necessary to satisfy the final accuracy of the converter.

Next, it is necessary to satisfy AC accuracy, so this will be briefly explained using FIG. 10. Figure 1O is lower A
It shows the transient response of the input voltage of the /D conversion circuit. The input terminal has a power level that falls within a certain voltage range over time.A certain settling time is required.The subtracter in particular is an operational amplifier with a large amount of negative feedback, so it has poor phase characteristics and tends to take a long settling time. . This slows down the conversion speed of the series-parallel A/D converter (1) In some cases, this may cause oscillation, and noise such as system noise leaking from the lower A/D conversion circuit may enter, reducing conversion accuracy. The present invention has been made in view of the above problem, and aims to provide a high-speed, high-precision series-parallel type A/D converter with a simple configuration and suitable for use in monolithic ICs. The purpose is

Means for Solving the Problems The present invention includes a reference voltage generating means that generates a plurality of reference voltages, and an analog input signal input common to one input terminal (each reference voltage is input to the other input terminal). There are multiple differential conversion circuits numbered in order of reference voltage magnitude that convert the potential difference between the input terminals into an output current (however, the comparison polarity is the even-numbered differential conversion circuit and the odd-numbered differential conversion circuit). The analog input signal and the reference voltage are directly or indirectly compared with a differential conversion circuit array consisting of a differential conversion circuit (which is the opposite) and a load resistance array that loads the output current of the differential conversion circuit, and the upper an upper A/D conversion circuit that performs conversion; a first selection means that selects output currents of a plurality of differential conversion circuits to which specific consecutive numbers are attached from among the plurality of output currents; a first switching means for switching an output current and supplying it to the load resistance string; a second selection means for selecting a specific output voltage from among the voltages generated in the load resistance string; and a selected output voltage. a voltage dividing means for dividing the voltage between the output voltages of the load resistor array, and a voltage divided by the voltage dividing means and the second selecting means. This is a series/parallel type A/D converter having a lower A/D conversion circuit that performs lower A/D conversion by comparing the voltages selected by the lower A/D converters.

Operation In the present invention, upper A/D conversion is performed in the same manner as in the conventional example. However, a D/A conversion circuit and a subtracter are not provided, and the analog input signal is commonly input to one input terminal, and each reference voltage is input to the other input terminal, and the potential difference between one input terminal and the other input terminal is From a plurality of differential conversion circuits numbered in order of magnitude of the reference voltage that is converted into an output current (however, the comparison polarity cL is reversed for even-numbered differential conversion circuits and odd-numbered differential conversion circuits). a selection means for subtracting and differentially amplifying the analog input signal and each reference voltage by providing a differential conversion circuit array, and selecting a specific output current from among the plurality of output currents;
A voltage necessary for lower-order A/D conversion is generated by providing a switch means for switching a selected output current and supplying it to a load resistor. Even worse, the voltage divided by the voltage dividing means that divides the voltage between the output voltage selected by the selection means that selects a specific output voltage from among the voltages generated in the load resistor and the output voltage of the load resistor string. By comparing and performing lower-order A/D conversion, a special reference voltage for lower-order A/D conversion is unnecessary, and the influence of the gain accuracy of the differential conversion circuit on conversion accuracy is eliminated. In addition, the differential conversion circuit does not need to be a negative feedback type circuit such as an operational amplifier, but a non-negative feedback type circuit such as a differential amplifier circuit is sufficient, so it is a series-parallel type A/D converter that is very stable and high speed without adjustment. A converter can be realized.

Embodiment A circuit diagram of a series-parallel type A/D converter according to a first embodiment of the present invention is shown in FIG. An analog input signal 2 is commonly input to one input terminal of a differential conversion circuit array 1 consisting of conversion circuits.
Each reference voltage generated by dividing the voltage of the reference voltage 3 constituting the reference voltage generating means by a reference resistor 4 is input to the other input terminal. It has an upper comparator array 5, and one input terminal of each comparator has the voltage level at each voltage division point of the reference resistor 4, and the other input terminal commonly inputs the analog input signal 2, and its comparison output. is upper logic circuit 6
When the output of the upper logic circuit 6 is determined? Q
A voltage is generated across the load resistor array 8 by applying a signal to the first switch means 7 to select a specific output current from among the plurality of output currents.

The generated voltage is sent to voltage dividing means 1o and divided there. Each of the comparators constituting the lower comparator array 12 has a divided voltage and an upper logic circuit 6 which includes as a part a second selection means for selecting a specific voltage from the divided voltage. The output voltage of the second switching means 11 which is switched by the output is compared, and the comparison output is input to the lower logic circuit 13 to determine the output of the lower logic circuit 13. By adding the outputs in an adder 14, an A/D conversion output 15 is obtained.

Next, the operation of the first embodiment of the present invention will be explained in detail with reference to FIG.

FIG. 2 shows (a) each differential conversion circuit AO, A4 . ..., A16 output ■aO,
Ia4. ..., Iala, and each differential conversion circuit A2. A6. ..., output I of A18
b2. Ib6゜..., Ibl& (b) Comparison output of each comparator co-07, (c) Switch Sad,
Sc4. -・-, 5a16. Sb2,
Sb6. ...+, 5b18. Sca, Sc
b shows the selected state.

As shown in FIG. 2(a), each differential conversion circuit AO,
A2. ...t, A18 reference voltage is VO, V2
゜..., Vi8, each output IaO, Ia4 .
...Ia16. Ib2. Ib6.・・＋
, Ib181 friend L(1
-1) and (]-2).

Iai= g (Vs-Vi) +Ib (i=
o.

4,...,16) (1-1) Ibi=-g (Vs-Vi) +Ib (i=2
゜6,...,18) (1-2) However, in the above equation, g is the mutual conductance of the differential conversion circuit, and Ib is the bias current.

The comparison outputs of the comparators 02 to C16 forming the upper comparator array 5 shown in FIG. 2(b) are given by the following equation (2).

Ci=sgn (Vs-Vi) (i= 2, 4,..., 16) (2)
However, in the above equation, the sgn function is defined and used as follows: sgn(x)=1 :x≧O sgn(x) =O: x<0 From equation (2), it is clear that the comparison output of each comparator takes ζζ [1] when the input signal is larger than each reference voltage.

Therefore, if these comparison outputs are input to the logic circuit 6,
Upper A/D conversion output can be obtained.

(3) ti in FIG. 2 shows the open/close states of each switch of the switch means 7 and the connection state of each switch of the switch means 11. In the figure, [1] indicates the ON state, [
0] indicates the OFF state, [+] indicates the connection state to the 10th terminal, and [-] indicates the connection state to the 1st terminal'? l-0 As described above, the differential conversion circuit generates a linear output current and is selectively switched depending on the voltage level of the analog input signal.

Apparatus A method for performing lower A/D conversion using the output current generated as described above will be described.

The output current of the differential conversion circuit is guided to a load resistor by the first switch means 7 and converted into a voltage.

FIG. 3 shows the voltage at each node within the voltage dividing means for the analog input signal 2. In this example, the resolution of the lower A/D conversion is assumed to be 3 bits, and the case where the voltage of the analog input signal 2 is between V2 and Vs is shown. As the voltage dividing means, the same resistors are connected in series. The output currents of four selected adjacent differential conversion circuits are converted into voltages by load resistances, and a voltage division L is established between them.
Generate VAI-VA3 and VBI-VB3. V.A.
The increasing/decreasing polarity of O-VA4 and the increasing/decreasing polarity of VBO-Vs4 are uniquely determined by the level of the analog input signal.

VA over the entire input terminal range, taking into account its increase/decrease polarity.
The states of O to VA4 and VBO to VB4 are shown in FIG. As described above, the configuration difference can realize a series-parallel type A/D converter that doubles the minimum voltage range of binary A/D conversion and performs 3-bit lower A/D conversion.

As shown in Figure 5, the load resistor string 8 and voltage dividing means IO
In the case of a configuration in which a buffer means 9 is inserted between
By inserting the buffer means 9 in addition to the method shown in the figure, the output voltage of the load resistor string 8 is reduced by the voltage dividing means 1o.
This makes it possible to obtain a series-parallel type A/D converter with higher accuracy than the series-parallel type A/D converter having the configuration shown in FIG. 1.

Next, FIG. 7 shows a circuit diagram of a series-parallel type A/D converter according to a second embodiment of the present invention. This has the same configuration as the A/D converter of the first embodiment of the present invention except for the presence or absence of a load resistor, and the effect of current/voltage conversion by the load resistor in the A/D converter of the first embodiment. can be considered as having been omitted.

Next, a third embodiment will be explained using FIG. 11. In the circuits of FIGS. 1 and 5, an upper comparator row and a lower comparator row are respectively provided. As shown in FIG. 11, the third switch means 104 controlled by the third selection means is Voltage dividing point of resistor 4, voltage dividing means 10 and comparator array 10
5, the comparator array can be used time-divisionally for upper and lower conversions, so the number of comparators can be reduced compared to the circuits shown in Figures 1 and 5. D
The circuit scale of the converter can be reduced. The third switch means 104 (song)
The conversion logic circuit 106 includes the functions of the upper logic circuit 6, the lower logic circuit 13, and the adder 14 in the first embodiment.

Finally, the fourth embodiment will be described using Figures 1-6. When performing low-order conversion in each of the circuit configurations shown in Figs. In the present invention, the input voltage of the comparator for interpolation is generated using the outputs of a plurality of differential circuits. According to one of the ideas of may be given as the input of the comparator.Since the voltage at each voltage dividing point of the voltage dividing means 10 is used as the input of the lower comparator, the second switch in the embodiments of FIGS. Means 11 becomes unnecessary.

Effect of the invention According to the present invention, the following effects can be obtained.

(1) It is not necessary to match the full-scale voltage of the D/A converter circuit and the full-scale voltage of the host A/D converter circuit as in the past, so high-precision A/D conversion can be achieved. This method simplifies the configuration because no circuit means is required for this purpose, and it is convenient because the reference voltage can be freely varied by an external signal.

(2) The power of using conventional high-precision operational amplifiers and differential conversion circuit arrays (relative gain accuracy between adjacent differential conversion circuits is necessary, but absolute accuracy is not required). Therefore, a normal emitter-coupled transistor pair is sufficient for the differential conversion circuit without using an operational amplifier.In addition, the relative gain accuracy of the differential amplifier circuit can be sufficiently achieved by using integrated circuit technology.High precision By not using an operational amplifier, there is no need for adjustment points, so it is possible to construct a series-parallel type A/D converter that is suitable for integrated circuits and is faster than the conventional one.

(3) Furthermore, there is no need to match the full-scale voltage of the reference voltage of the lower A/D conversion circuit as in the conventional case.

This is due to the lower A/D conversion power of this embodiment (without using a fixed reference voltage as in the conventional case). This is to compare the voltages and perform lower A/D conversion.In other words, the reference voltage for the input analog signal of the lower A/D conversion is the same voltage divided between the reference voltages of the upper A/D conversion. This is because the lower A/D
The compatibility between the conversion and the upper A/D conversion is extremely good, making it possible to perform conversion with higher precision.

(4) In addition, in this example, the input signal of the lower A/D conversion is in a differential format, which has the effect of removing common mode noise such as power supply noise, and provides a more accurate and stable direct signal than before. A parallel A/D converter can be realized.

(5) Set the conversion voltage range of the lower A/D converter to the upper comparator 1.
By including and widening the comparison range of units, more accurate conversion can be performed even for input signals that fluctuate over time, and further stability of A/D conversion (L
High speed and high precision can be achieved.

(6) Furthermore, since the input voltage of the differential amplifier circuit that is switched when the input signal changes between adjacent upper comparator units is the voltage that is farthest from the adjacent voltage, Lower A at both ends of the comparison range
Since the method of generating the input voltage of the /D conversion comparator is guaranteed to be unique, it is possible to ensure uniformity (i.e., uniqueness) of the conversion output code between adjacent upper comparator units. can.

[Brief explanation of the drawing]

FIG. 1 shows the circuit configuration diagram of the first embodiment of the present invention.
(a) is an explanatory diagram showing the output of the differential conversion circuit inside the A/D converter of the example. (b) in Figure 2 is an explanation diagram showing the comparison output of each comparator. Figure 3 shows the state of the lower A/D conversion in the embodiment @ Figure 4 shows the state of the lower conversion over the entire input terminal range @ Figure 5 shows the state of the lower A/D conversion in the example 1 A circuit configuration diagram of an embodiment including a voltage buffer means. FIG. 6 is an explanation of the case where the intersection of the input terminals of the comparator for lower conversion is set at a different point from the embodiment shown in FIG. 1. @ FIG. 7 is the invention of the present invention. the second of
The circuit configuration of the example shown in Figure 8 is a conventional series-parallel type A/D.
Converter circuit diagram Figure 9 is a voltage relationship diagram of each part of a conventional series-parallel type A/D converter Figure 1O is a conventional series-parallel type A/D converter
Voltage waveform showing the transient response of the input voltage of the lower A/D conversion circuit of the /D converter @ Fig. 11 is a circuit diagram of the embodiment of Invention Box 3 Fig. 12 is the circuit of the embodiment of Invention Box 4 FIG. 1... Differential conversion circuit 14... Reference resistance redundancy 5... Binary comparison processing 6... Upper logic circuit, 7.
...First switch hand R10... Voltage dividing means, 1
1... Second switch means, 12... Lower comparator L13... Lower logical port Ii & 14... Addition a

Claims (2)

[Claims] (1) Reference voltage generation means that generates a plurality of reference voltages;
A common analog input signal is input to one input terminal, and each reference voltage is input to the other input terminal.The reference voltages, which convert the potential difference between the input terminals into an output current, are numbered in order of magnitude. (However, the comparison polarity is reversed between the even-numbered differential conversion circuit and the odd-numbered differential conversion circuit) and the differential conversion circuit. A load resistor string that acts as a load for the output current of a first selection means for selecting an output current of a plurality of numbered differential conversion circuits; a first switch means for switching the selected output current and supplying the selected output current to the load resistor string; a second selection means for selecting a specific output voltage from among the voltages generated in the resistor string; a second switch means for switching the selected output voltage and sending it to the next stage; and an output voltage of the load resistance string. and lower A/D conversion for performing lower A/D conversion by comparing the voltage divided by the voltage dividing means and the voltage selected by the second selection means. A series-parallel A/D converter with a circuit (2) reference voltage generation means that generates a plurality of reference voltages;
A common analog input signal is input to one input terminal, and each reference voltage is input to the other input terminal.The reference voltages are numbered in order of magnitude, converting the potential difference between the input terminals into an output voltage. A differential conversion circuit array consisting of a plurality of differential conversion circuits (however, the comparison polarity is reversed for even-numbered differential conversion circuits and odd-numbered differential conversion circuits), and an analog input signal and reference Select the output voltages of the upper A/D conversion circuit that directly or indirectly compares the voltages and performs higher conversion, and of the multiple differential conversion circuits that are given specific consecutive numbers from among these multiple output voltages. a first selection means for switching the selected output voltage and supplying it to the next stage; and a second selection means for selecting a specific output voltage from among the plurality of selected output voltages. means, and second switch means for switching the selected output voltage to the next stage;
Voltage dividing means divides the output voltages selected by the first selecting means, and compares the voltage divided by the voltage dividing means and the voltage selected by the second selecting means, A serial-parallel type A/D converter having a lower A/D conversion circuit that performs A/D conversion.