JPH0472638U - - Google Patents
Info
- Publication number
- JPH0472638U JPH0472638U JP11519490U JP11519490U JPH0472638U JP H0472638 U JPH0472638 U JP H0472638U JP 11519490 U JP11519490 U JP 11519490U JP 11519490 U JP11519490 U JP 11519490U JP H0472638 U JPH0472638 U JP H0472638U
- Authority
- JP
- Japan
- Prior art keywords
- convex mounting
- metal base
- package
- semiconductor elements
- mounting portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 239000011247 coating layer Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990115194U JP2515672Y2 (ja) | 1990-10-31 | 1990-10-31 | 半導体素子収納用パッケージ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990115194U JP2515672Y2 (ja) | 1990-10-31 | 1990-10-31 | 半導体素子収納用パッケージ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0472638U true JPH0472638U (US07179912-20070220-C00144.png) | 1992-06-26 |
| JP2515672Y2 JP2515672Y2 (ja) | 1996-10-30 |
Family
ID=31862938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990115194U Expired - Lifetime JP2515672Y2 (ja) | 1990-10-31 | 1990-10-31 | 半導体素子収納用パッケージ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2515672Y2 (US07179912-20070220-C00144.png) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6450438U (US07179912-20070220-C00144.png) * | 1987-09-24 | 1989-03-29 | ||
| JPH0187547U (US07179912-20070220-C00144.png) * | 1987-12-02 | 1989-06-09 |
-
1990
- 1990-10-31 JP JP1990115194U patent/JP2515672Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6450438U (US07179912-20070220-C00144.png) * | 1987-09-24 | 1989-03-29 | ||
| JPH0187547U (US07179912-20070220-C00144.png) * | 1987-12-02 | 1989-06-09 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2515672Y2 (ja) | 1996-10-30 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |