JPH0471267A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the density of semiconductor layers making use of the thin film technology by a method wherein the thin film semiconductor layers having adjacent P type semiconductor regions and N type semiconductor regions through the intermediary of channel regions are formed in a pair of two layers while respective P type and N type semiconductor regions are arranged in the positions to be opposed to one another and an insulating layer is interposed between both semiconductor layers. CONSTITUTION:Thin film semiconductor layers having adjacent P type semiconductor regions 2A, 2B and N type semiconductor regions 3A, 3B through the intermediary of channel regions 6A, 6B are formed in a pair of layers while both semiconductor layers are arranged in the positions wherein respective P type semiconductor regions 2A, 2B and the N type semiconductor regions 3A, 3B are opposed to one another with an insulating layer 4 interposed between both semiconductor layers. When respective P type semiconductor regions of respective semiconductor layers are charged with positive potential while respective N type semiconductor regions are charged with negative potential, the charges in mutually inverse polarity are generated in the opposite surface side of the channel region of respective semiconductors. Resultantly, the signal logic to be memorized can be written-in and read-out by controlling the potentials in the channel regions thereby enabling said logic to be used as a memory cell of a SRAM.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology (Figures 15 to 18) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples Principle (Figures 2 to 4) First embodiment (Figure 5) Second embodiment (Figure 6) Third embodiment (Figure 7) Fourth embodiment (Figure 8) Fifth embodiment (Figure 9) Sixth embodiment (Figure 10) Seventh embodiment (Figure 11) Eighth embodiment (Figure 12) Ninth embodiment (Figure 13) Tenth embodiment (Figure 14) Effects of the invention [Summary] LSI (LaBe 5cale InteH+
atiop) Pertains to semiconductor storage devices such as memories, especially thin film transistors (TFTs).
am+i+te+) technology using S RAM (S+
a+i+ Raodom Accz+ Memory
), the purpose is to provide a semiconductor memory device that can achieve high density using thin film technology, and to
A pair of thin film semiconductor layers each having a type semiconductor region are formed as a pair of two layers, and the amphibian conductor layer is disposed at a position where each of the P-type semiconductor region and the N-type semiconductor region faces each other,
Further, the structure is such that an insulating layer 4 is interposed between both the semiconductor layers.

[Industrial application field]

The present invention is based on L Si (Large 5cale I
(integration) memory and other semiconductor storage devices, especially thin film transistors (TFTs: Tb1n Fi
S RAM using lmTram+1ste+) technology
(Static Ramdom Access Me
Regarding mo ``y''.

SRAM as an LSI memory has a feature of low power consumption when holding data, and is used in various computer systems.

LSI memory requires smaller chip size, lower power consumption,
Larger capacity is required. Accordingly, it is necessary to miniaturize the flip-flop circuit, which is the storage unit (memory cell) of the SRAM.

[Conventional technology]

Conventionally, the following types of SRAM memory cells are known.

(1) CMO3 type cell This is a CMOS inverter consisting of a PMOS transistor T2 and an NMO8h transistor T3, and a PMOS
This is a 6-transistor type memory cell (FIG. 15) in which a flip-flop is formed using two CMOS inverters, a CMOS inverter consisting of a transistor T4 and an NMOS transistor T5, and transfer gates T and T6 are combined with this flip-flop (FIG. 15).

(2) NMO3 load type cell This is a memory cell that uses an NMo5 transistor as a load element. There are two types of NMOS transistors: enhancement type MO3) transistors T and T8 (FIG. 16(a)) and depletion type MOS transistors T9 and TII.

(3) Resistive load type cell This is a load element made of polysilicon (PolySi).
2 is a memory cell using resistance elements R1R2 (FIG. 17).

(4) Thin-film PMOS transistor cell This is a memory cell that combines ordinary bulk-type MOS transistors T and T5 and thin-film transistors T and T (FIG. 18).

[Problem to be solved by the invention]

The above CMO8 type cell (Fig. 15) has advantages such as a wide operating margin (and low data retention current), but it has a large number of elements and NMO3 and PMO3 are formed in the same memory cell, so the elements are separated. Therefore, it is difficult to reduce the cell area.

The NMO8 load cell (Fig. 16 (a) (b)) and the resistive load cell (Fig. 17) must have a large channel length in order to reduce power consumption (that is, reduce data retention current). There is a limit to the reduction in cell area. Furthermore, it is difficult to reduce the cell area due to the necessity of element isolation.

The thin film PMO8) transistor cell (FIG. 18) can reduce the data retention current, but since it includes the bulk type MOS transistor TST, the cell area is required to be about the same as that of the resistive load type cell.

Note that there are other memories such as EEPROM and EPROM, which have a small cell area per storage unit or are fast (
There is a drawback that a write operation of 10 ns) cannot be performed.

An object of the present invention is to provide a semiconductor memory device that can achieve high density using thin film technology.

[Means to solve the problem]

In order to solve the above problem, as shown in FIG.
A pair of thin film semiconductor layers having P-type semiconductor regions 2A, 2B and N-type semiconductor regions 3A, 3B that are adjacent to each other via the respective P-type semiconductor regions 2A are formed.

2B and N-type semiconductor regions 3A, 3B are arranged at positions facing each other, and an insulating layer 4 is provided between the two semiconductor layers.
It is composed by intervening.

In this case, in a more specific embodiment, the semiconductor layer and the insulating layer are formed of thin films. Further, the semiconductor memory device is formed on the lower surface of the insulating substrate 1. The semiconductor memory devices are formed by being stacked in a direction perpendicular to the insulating substrate 1, or formed in parallel in a direction parallel to the direction in which the insulating substrate 1 extends. On the other hand, the semiconductor layer 2.3 and the insulating layer 4 have a disk shape, and are laminated to form a columnar shape as a whole. Furthermore, the semiconductor memory device can also be embedded inside the insulating substrate 1.

The second invention described in claim 7 provides a channel region 68 to
Semiconductor layers having P-type semiconductor regions 2A to 2D and N-type semiconductor regions 3A to 3D adjacent to each other via 6D are formed as a pair of two layers, and both semiconductor layers have respective P-type semiconductor regions 2A to 2D and N-type semiconductor regions 2A to 2D. A semiconductor memory device in which the semiconductor regions 3A to 3D are arranged at positions facing each other and an insulating layer 4 is interposed between the two semiconductor layers is provided in the stacking direction of the semiconductor layers with an insulating layer 4' interposed therebetween. It is constructed by laminating multiple layers. In this second invention, in a more specific state, a conductive shield layer 10 is provided in the second insulating layer 4'.
is formed.

A third invention described in claim 9 provides a channel region 6A,
A pair of semiconductor layers having P-type semiconductor regions 2A, 2B and N-type semiconductor regions 3A, 3B adjacent to each other via 6B are formed as a pair of two layers, and both semiconductor layers are connected to the respective P-type semiconductor regions 2A, 2B and N-type semiconductor regions. The channel region 6A is arranged at a position where the semiconductor regions 3A and 3B face each other, an insulating layer 4 is interposed between the two semiconductor layers, and the channel region 6A is on the outer surface of one or both of the semiconductor layers.

A gate electrode 11 is placed at a position facing 6B via an insulating layer 4.
A, form and configure IIB.

A fourth invention described in claim 10 provides a channel region 6A.
, 6B are formed as a pair of two-layer semiconductor layers having P-type semiconductor regions 2A, 2B and N-type semiconductor regions 3A, 3B adjacent to each other via the respective P-type semiconductor regions 2A, 2B and N. A semiconductor memory device is constructed by arranging the shaped semiconductor regions 3A and 3B at positions facing each other and interposing an insulating layer 4 between the two semiconductor layers, and forming a semiconductor memory device on the side of one of the semiconductor layers. Field effect transistors 8A and 8B are formed such that their channel regions face the channel region 6A of the semiconductor layer with an insulating layer interposed therebetween.

According to a more specific aspect of the fourth invention, the field effect transistors 8A and 8B are bulk type field effect transistors. Or the field effect transistor 8A,
8B is a thin film field effect transistor.

A fifth invention described in claim 13 provides a channel region 6A.
, 6B are formed as a pair of two-layer semiconductor layers having P-type semiconductor regions 2A, 2B and N-type semiconductor regions 3A, 3B adjacent to each other via P-type semiconductor regions 2B, 6B, and 6B. The N-type semiconductor regions 3A and 3B are arranged at positions facing each other, and an insulating layer 4 is placed between the two semiconductor layers.
A conductive layer 7 for charge extraction is provided between the channel regions 6A and 6B or both of the channel regions 6A and 6B.
It is configured by electrically connecting A and 7B.

[Effect]

According to the first invention described in claim 1, when a positive potential is applied to each of the P-type semiconductor regions of each semiconductor layer, and a negative potential is applied to each of the N-type semiconductor regions of each semiconductor layer, the channel of each semiconductor layer is Charges of opposite polarity are generated on opposing surfaces of the regions, that is, positive charges (holes) in one channel region and negative charges (electrons) in the other channel region. This state is equivalent to the mutually opposing semiconductor layers acting as gates, and since the charge in each channel region is held, a memory function is performed. As a result, by controlling the potential of the channel region in some way,
Since the signal logic to be stored can be written and read, the pair of two semiconductor layers can be used as a 1-bit storage element, that is, a memory cell of an SRAM.

According to the second invention described in claim 7, by stacking the semiconductor storage devices having the configuration described in claim 1 in the stacking direction of the semiconductor layers, a conventional semiconductor storage device regulated in a two-dimensional plane can be obtained. In addition to this, flexibility in the layout of memory cells in the stacking direction is ensured, making integration in three dimensions possible.

According to the third invention described in claim 9, the gate electrode is disposed facing the channel region of the semiconductor memory device having the structure described in claim 1, so that the charge or discharge of electric charge to the channel region, that is, Specific means for writing or reading signals are disclosed, allowing operation as a memory cell.

According to a fourth invention described in claim 10, there is disclosed a configuration in which the semiconductor memory device having the configuration described in claim 1 and a field effect transistor are combined, and the writing and reading of charges to and from the channel region is performed by field effect. It can be controlled by the switching action of transistors.

According to a fifth invention described in claim 11, there is disclosed a configuration in which the semiconductor memory device having the configuration described in claim 1 and a gate electrode are combined, and writing and reading of charges to and from the channel region is performed using a conductive material. can be controlled.

〔Example〕

Next, each embodiment of the present invention will be described based on the drawings.

Principle First, the principle of the semiconductor memory device according to each invention of the present application will be explained. Now, consider a thin film semiconductor memory device having the structure shown in FIG. A semiconductor layer having a P region 2 and an N region 3 adjacent to each other with a channel region 6 interposed therebetween is formed on the lower surface of a glass substrate 1 such as PSG (silicon phosphide glass), and a gate electrode is formed on the lower surface thereof with an insulating layer 4 interposed therebetween. 5 is formed. Gate electrode 5 is laid out at a position facing channel region 6 . The channel region 6 is a so-called non-doped region that is not doped with any impurity.

Now, as shown in FIG. 2(a), the extraction electrode EL
A high potential side power supply voltage ■C6 is applied to the P region 2 through the P region 2, and a low potential side power supply voltage ■C6 is applied to the N region 3 through the extraction electrode EL3.
When the high-potential side power supply voltage voo is applied to the gate electrode 5 via the extraction electrode EL2 while SS is applied, negative charges are attracted to the channel region 6, which is a non-doped region where no charge existed until then. to form a channel CH. At this time, the N region 3 and the channel region 6 have an excess of electrons, so they have the same potential (V ss).

On the contrary, as shown in FIG. 2(b), the low potential side power supply voltage ■ is applied to the gate electrode 5 via the arched electrode E L 2.
When 5S is added, positive charges (holes) are attracted to the non-doped channel region 6 to form a channel.

At this time, the P region 2 and the channel region 6 are at the same potential (Vcc) due to excess holes.

In this way, the charge in the channel region 6 can be reduced by forming the semiconductor layers of the P region 2, the channel region 6, and the N region 3, and by arranging the gate electrode 5 to face the channel region 6 and controlling the potential of the gate electrode 5. The accumulation state can be controlled.

Next, consider the structure shown in FIG. That is, the semiconductor layers of P region 2, channel region 6, and N region 3 are formed as a pair of two layers on the lower surface of substrate 1 with insulating layer 4 interposed therebetween.

The insulating layer 4 has a thickness comparable to that of a gate oxide film of a normal IC. In this way, when semiconductor layers are formed as a pair of two layers, the second channel region 6B of one semiconductor layer is connected to the first channel region 6B of the other semiconductor layer.
It functions as a gate for the channel region 6A (or vice versa). That is, as shown in FIG. 4, the high potential side power supply voltage ■ is applied to the first P region 2A and the second P region 2B.
A low potential side power supply voltage is applied to the first N region 3A and second N region 3BCC. , the first channel region 6A has an electron channel CH and the second channel region 6B
A hole channel CH is formed in each of the first channel region 6A and the second channel region 6A, the first channel region 6A has a low potential side power supply voltage
B becomes the potential of the high potential side power supply voltage SS oo, and each acts as a gate in the direction of further strengthening the charge state of the other channel, and as a result, the potential of each first channel region 6A and second channel region 6B becomes Retained. This means that the semiconductor memory device of FIG. 3 operates as a memory element (memory cell). A semiconductor memory device having such a configuration can be called a "thin film mutual memory element."

First example FIG. 5 shows a first embodiment (claims 1 to 3).

In order to clarify the laminated state of the semiconductor layers, FIG. 5 shows the vertical relationship reversed from that in FIG. 3. This vertical relationship is determined by the manufacturing process.
The opposite is true if the process is reversed. The operation is the same no matter what.

The embodiment shown in FIG.
An example will be disclosed in which the stacking direction of the semiconductor layers in the channel region 6B and the second N region 3B is perpendicular to the lower surface of the substrate 1. Amorphous silicon is generally used as the semiconductor material, and the substrate 1 is a glass substrate such as PSG. This material is the same in each of the following Examples unless otherwise specified. By adopting such a structure, it is possible to stack the stacked state shown in FIG. It is possible to integrate the memory into the memory and improve the storage density. Incidentally, since a conventional IC memory forms a transistor on an St substrate, it can be expanded only in a two-dimensional plane direction, that is, in the direction of extension of the plane of the substrate 1.

Second Embodiment FIG. 6 shows a second embodiment (claim 4). Similarly, FIG. 6 also shows the vertical relationship reversed. In this embodiment, the first P area 2A1 and the first channel area 6A.

The semiconductor layer of the first N region 3A and the second P region 2B.

An example will be disclosed in which the stacking direction of the second channel region 6B and the second N region 3B with the semiconductor layer is parallel to the direction in which the plane of the substrate 1 extends. Semiconductor materials are also amorphous.
Silicon, SiO for the insulating layer 4, PSG for the substrate 1, etc. can be used. With such a structure, layout in the tertiary direction is possible, and the integration density is improved.

Third Embodiment FIG. 7 shows a third embodiment. In this example, P region 2Δ
, 2B, N area 3A, 3. An example is disclosed in which the B semiconductor layer, channel regions 6A, 6B, and insulating layer 4 are formed in a columnar or cylindrical shape. That is, the ring-shaped P region 2A.

It has a sandwich-like structure in which a ring-shaped channel region (non-dope region) 6A16B is also interposed between 2B and N regions 3A and 3B. The hollow portion is formed as necessary due to the convenience of the manufacturing process or the extraction of electrodes.

The structure shown in FIG. 7 is used as the minimum unit memory cell,
A rod-shaped semiconductor memory device is formed by sequentially stacking them in the axial direction with insulating layers interposed therebetween. By arranging a plurality of memory units in parallel using the rods, a three-dimensionally integrated semiconductor memory device can be formed.

Fourth Embodiment A fourth embodiment is shown in FIG. In this embodiment, the assembly of the semiconductor layer of the first P region 2A, the first channel region 6A, the semiconductor layer of the first N region 3A, the semiconductor layer of the second P region 2B, the second channel region 6B, the second N region 3B, and the insulating layer 4 is carried out on a substrate. 1
Disclose an example embedded within. The stacking direction of the assembly can be either in the direction in which the plane of the substrate 1 extends, as shown in FIG. 6, or in the vertical direction, as shown in FIG. By embedding the assembly in the substrate 1 in this manner, the functional strength of the entire semiconductor memory device can be improved.

Further, by stacking a plurality of substrates 1 in which this assembly is embedded, three-dimensional integration becomes possible.

Fifth Embodiment FIG. 9 shows a fifth embodiment. This embodiment discloses an example in which storage signals are indirectly written and read.

That is, as shown in FIG. 9, S, a substrate (not shown)
, the drain D (8A) of the bulk type MOS transistor
; Forming a diffusion layer for the source 5 (8B), and forming a first semiconductor layer opposing the channel region and consisting of a first P region 2A, a first channel region 6A, and a first N region 3A with an insulating layer 4 interposed therebetween; , then the second P region 2B via the insulating layer 4,
A second semiconductor layer consisting of a second channel region 6B and a second N region 3B is formed.

There are two possible writing methods:

One is the first channel region 6A, the second channel region 6
This method utilizes capacitive coupling between channel regions of B and MoS transistors. In this method, a high potential side power supply voltage V (or a low potential side power supply voltage 8.) is applied to both the drain D and the source D, and the high potential side power supply voltage V at that time is applied. Charges of the opposite polarity of C are induced in the first channel region 6A to form a channel, and charges of the opposite polarity are induced in the second channel region 6B to form a channel of opposite polarity. Another method is to apply a write voltage higher than the high potential side power supply voltage vcC to the drain D. (For example, 10
v), OV is applied to the source S, and hot electrons generated from the channel region of the bulk MOS transistor are caused to jump into the first channel region 6A of the first layer to charge and form a channel; This is a method of forming a channel of opposite polarity in the second channel region 6B by charging the channel region 6A. In either method, after writing, the drain D1 and the source S are left floating, and the states of the first channel region 6A and the second channel region 6B are maintained and stored.

The reading method is 1/2vco between drain D and source S.
is gradually applied, the first channel region 6A of the -th layer at that time acts as the gate of a MOS transistor, and the drain D.
The stored contents are read by measuring the current change due to conduction/non-conduction (ONloFF) between the sources S.

Sixth Embodiment FIG. 10 shows a sixth embodiment. Similar to the fifth embodiment, this embodiment discloses an example in which storage signals are indirectly written and read.

That is, as shown in FIG. 10, a first gate 11A is formed on the outside of the semiconductor layer of the first P region 2A, first channel region 6A, and first N region 3A through the insulating layer 4, facing the first channel region 6A. , and the second P region 2B, the second
Channel area 6B.

A second channel region 6 is located outside the semiconductor layer of the second N region 3B.
A second gate 11B is formed opposite to B with an insulating layer 4 interposed therebetween.

At the time of writing, write voltage 2. is applied to the first gate lIA. (
For example, 10 V) is applied to form a hole channel in the first channel region 6A, and Ov is applied to the second gate 11B.
is added to form an electron channel in the second channel region 6B. After writing, first gate 11A1 second gate 11B
Both are floating, or 1/2vcC is applied to hold the memory.

Seventh Embodiment FIG. 11 shows a seventh embodiment. This embodiment discloses an example in which writing to and reading from the first channel region 6A and the second channel region 6B is performed by a direct method.

As shown in FIG. 11, the first channel region 6 of each semiconductor layer
Terminals 7A and 7B made of thin film conductive layers having the same thickness as those of A and second channel region 6B are connected to terminals 7A and 7B in first channel region 6A.
, are formed in a state of being electrically connected to the second channel region 6B.

For writing, for example, the low potential side power supply voltages 1 and 5 are applied to the terminal 7B. Then, the first channel region 6A receives the low potential side power supply voltage v8. In response to this, the second channel region 6B becomes the high potential side power supply voltage oc, so that the memory is retained by retaining the charge in this state.

Reading is performed by measuring the potential of terminal 7A or terminal 7B. For example, the terminal 7A (or 7B) on the hole channel side is floating, and the terminal 7B (or 7A) on the electron channel side is at the low potential side power supply voltage vss.
Therefore, measure this potential. Alternatively, the direction in which the current flows at the terminals 7A and 7B may be measured.

Eighth Embodiment FIG. 12 shows an eighth embodiment. This example discloses an example of a multilayer structure of an assembly of semiconductor layers.

As shown in FIG. 12, the semiconductor layer of the first P region 2A, the first channel region 6A, the first N region 3A, the insulating layer 4, the second P region 2B, the second channel region 6B, the second N region 3
an assembly consisting of a semiconductor layer B, a third P region 2C,
Third channel region 6C, semiconductor layer of JII3N region 3C, insulating layer 4 and fourth P region 2D, fourth channel region 6
D, an assembly consisting of semiconductor layers in the fourth N region 3D are stacked in the vertical direction of the substrate 1 with an insulating layer 4 in between. In this structure, the second channel region 6B and the third channel region 6C further form a memory unit, and when the amount of electrons and holes in the entire channel is constant, the area of the device is reduced, and the vertically stacked structure Show what you can do. Although this example shows a four-layer multilayer structure, it is theoretically possible to laminate a considerable number of layers. Integration in the stacking direction becomes possible.

Ninth Embodiment FIG. 13 shows a ninth embodiment. This embodiment is based on the structure shown in FIG. 3, and discloses an example in which a conductive shield layer 10 is interposed within the insulating layer 4 to provide electrostatic shielding in order to prevent interference between each assembly. . Other components are the same as those in FIG. 13.

10th example The t411 embodiment is shown in FIGS. 14(a) to 14(V).

This embodiment discloses an example of a manufacturing process for the semiconductor memory device shown in FIG. 5, for example. However, for the sake of explanation, the substrate 1 is not a glass substrate and is indicated by 5i02. The process will be explained below in order.

(a) 5 in a wet atmosphere at 900°C by thermal oxidation method
A silicon oxide film 21 of 00 OA is grown on the St substrate.

(b) CVD method, 11. ? ) Grow 400 first semiconductor layers 23 at 520°C.

(C) A first semiconductor layer 23 is formed using a mask.

(d) A gate oxide film 24 of 150 Å is grown using the CVD method.

(e) A contact hole 25 is opened in the gate oxide film 24 using a mask.

(f) A 100 OA second polysilicon layer 26 (for lead electrode) is grown by CVD.

(g) A hole is opened in the dose portion 27 (used for forming the p region) using a mask.

Plantation.

Hereafter, the 14th
A semiconductor memory device shown in FIG. 3(V) is formed. (i)～
The step (V) is as follows.

(i) Remove the resist.

(j) A dose portion for forming an N region is opened using a mask.

(k) Next, As (arsenic) is ion-implanted at IE14 (arsenic particles/cm2) with an acceleration energy of 20K.

(Remove the resist.

(m) Form an extraction electrode using a mask.

(n) Grow a gate oxide film 28 of 150 Å using the CVD method.

(0) Open a contact hole using a mask.

(p) Second layer of polysilicon (32,
33,34) Grow ゛.

(Q) Form a second channel using a mask.

(r) Oxide film (S io 2 ) of 1000% by CVD method
A.Grow.

(8) Grow 3,500 passivation films.

(1) The first polysilicon and the second polysilicon are annealed and diffused from the drawn polysilicon, and the first and second polysilicon are P” (P region) and N+ (N region).
form.

(U) Open a contact hole for an extraction electrode.

(v) Form a wiring layer 35 using a mask.

〔Effect of the invention〕

As described above, according to the inventions set forth in the claims of the present application, it is possible to highly integrate semiconductor memory devices using thin film technology.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention. FIG. 2 is an explanatory diagram of the structural principle of the semiconductor memory device of the present invention. FIG. 3 is a diagram of the basic structure of the semiconductor memory device of the present invention. FIG. 4 is an explanation of channel formation operation. Figure 5 is a perspective view of the first embodiment, Figure 6 is a perspective view of the second embodiment, Figure 7 is a partially cutaway perspective view of the third embodiment, and Figure 8 is a perspective view of the fourth embodiment. Figure 9 is a perspective view of the fifth embodiment, Figure 10 is a perspective view of the sixth embodiment, Figure 11 is a perspective view of the seventh embodiment, Figure 12 is a sectional view of the eighth embodiment, Fig. 13 is a cross-sectional view of the ninth embodiment, Fig. 14 is a process diagram of the tenth embodiment (manufacturing process), Fig. 15 is a circuit diagram of a CMO8 type cell, and Fig. 16 is a circuit diagram of an NMO8 load type cell. , FIG. 17 is a circuit diagram of a resistive load type cell, and FIG. 18 is a circuit diagram of a thin film PMOS transistor cell. 1... Substrate 2... P area 2A... First P area 2B... Second P area 2C... Third P area 2D... Fourth P area 3... N area 3A... 1N region 3B...second N region 3c...third N region 3D...fourth N region 4...insulating layer 4A...first insulating layer 4B...second insulating layer 4C...th 3 insulating layer 4D...Fourth insulating layer 5...Gate electrode 6...Channel 6A...First channel 6B...Second channel 6C...Third channel 6D...Fourth channel 7A... Terminal 7B... Terminal 8A... Diffusion region (drain) 8B... Diffusion region (source) 9... Burying recess 10... Shield layer 11A... First gate 11B. ...Second gate 20...Si substrate 21...Silicon oxide film (SiO2) 22...First polysilicon layer (Poly23...First semiconductor layer 24...Gate oxide film (1) 25...Contact hole 26...Second polysilicon layer (Poly27...Dose part 28...Silicon oxide film (S L O2) 29...
First P region 30...first channel 31...first N region 32...second channel 33...second channel 34...second N region 35...Al electrode 36...passivation film ■o,...High potential side power supply voltage Si) St) ■8. ...Low potential side power supply voltage E L t...Extracting electrode EL2...Extracting electrode EL3...Extracting electrode CH...Channel

Claims (1)

[Claims] 1. P-type semiconductor regions (2A, 2B) and N-type semiconductor regions (3A, 2B) adjacent to each other via channel regions (6A, 6B)
, 3B) are formed as a pair of two layers, and both semiconductor layers have respective P-type semiconductor regions (2A, 3B).
2B) and N-type semiconductor regions (3A, 3B) are arranged at positions facing each other, and an insulating layer (4) is interposed between the two semiconductor layers. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed on the lower surface of an insulating substrate (1). 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is formed by being stacked vertically to an insulating substrate (1). 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory devices are formed in parallel in a direction parallel to the extending direction of the insulating substrate (1). 5. The semiconductor memory device according to claim 1, wherein the semiconductor layers (2, 3) and the insulating layer (4) have a disk shape and are stacked in a columnar shape as a whole. Device. 6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is embedded within an insulating substrate (1). 7. P-type semiconductor regions (2A-2D) and N-type semiconductor regions (3A
~3D) are formed as a pair of two layers, and both semiconductor layers have respective P-type semiconductor regions (2A~2D).
and a semiconductor memory device in which N-type semiconductor regions (3A to 3D) are arranged at positions facing each other, and an insulating layer (4) is interposed between the two semiconductor layers, in the stacking direction of the semiconductor layers. A semiconductor memory device characterized in that a plurality of layers are stacked on each other with an insulating layer (4) interposed therebetween. 8. The semiconductor memory device according to claim 7, wherein the second
A semiconductor memory device characterized in that a conductive shield layer (10) is formed within an insulating layer (4). 9. P-type semiconductor regions (2A, 2B) and N-type semiconductor regions (3A) adjacent to each other via channel regions (6A, 6B)
, 3B) are formed as a pair of two layers, and both semiconductor layers have respective P-type semiconductor regions (2A, 2B).
and N-type semiconductor regions (3A, 3B) are arranged at positions facing each other, and an insulating layer (4) is disposed between the two semiconductor layers.
are interposed, and a gate electrode (11A, 11B) is formed at a position facing the channel region (6A, 6B) on the outer surface of one or both of the above with an insulating layer (4) interposed therebetween. A semiconductor memory device characterized by: 10. Adjacent P via channel regions (6A, 6B)
type semiconductor region (2A, 2B) and N type semiconductor region (3
A, 3B) semiconductor layers are formed as a pair of two layers, and both semiconductor layers have respective P-type semiconductor regions (2A, 2B).
) and N-type semiconductor regions (3A, 3B) are arranged in positions facing each other, and an insulating layer (4) is interposed between both the semiconductor layers, A field effect transistor (8A) is disposed on the semiconductor layer side so that its channel region faces the channel region (6A) of the semiconductor layer via an insulating layer.
, 8B) are formed. 11. The semiconductor memory device according to claim 10, wherein the field effect transistors (8A, 8B) are bulk type field effect transistors. 12. The semiconductor memory device according to claim 10, wherein the field effect transistors (8A, 8B) are thin film field effect transistors. 13. Adjacent P via channel region (6A, 6B)
type semiconductor region (2A, 2B) and N type semiconductor region (3
A, 3B) semiconductor layers are formed as a pair of two layers, and both semiconductor layers have respective P-type semiconductor regions (2A, 2B).
) and N-type semiconductor regions (3A, 3B) are arranged at positions facing each other, and an insulating layer (4
) is interposed, and the channel region (6A, 6B)
A semiconductor memory device characterized in that a conductive layer (7A, 7B) for extracting charges is electrically connected to one or both of them.