JPH0471021U - - Google Patents

Info

Publication number
JPH0471021U
JPH0471021U JP11523990U JP11523990U JPH0471021U JP H0471021 U JPH0471021 U JP H0471021U JP 11523990 U JP11523990 U JP 11523990U JP 11523990 U JP11523990 U JP 11523990U JP H0471021 U JPH0471021 U JP H0471021U
Authority
JP
Japan
Prior art keywords
converter
output
amplifier
whose input
amplification factor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11523990U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11523990U priority Critical patent/JPH0471021U/ja
Publication of JPH0471021U publication Critical patent/JPH0471021U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案による多段増幅器のレンジ切
換回路の構成図、第2図は第1図のフローチヤー
ト、第3図は従来技術による多段増幅器のレンジ
切換回路の構成図、第4図は第3図のフローチヤ
ートである。 1……入力端子、2〜4……増幅器、5……A
/D変換器、6……レンジ判定回路、7……CP
U、8……制御手段。
Fig. 1 is a block diagram of a range switching circuit for a multi-stage amplifier according to this invention, Fig. 2 is a flowchart of Fig. 1, Fig. 3 is a block diagram of a range switching circuit for a multi-stage amplifier according to the prior art, and Fig. 4 is a block diagram of a range switching circuit for a multi-stage amplifier according to the prior art. This is a flow chart of Figure 3. 1...Input terminal, 2-4...Amplifier, 5...A
/D converter, 6... Range determination circuit, 7... CP
U, 8...control means.

Claims (1)

【実用新案登録請求の範囲】 縦続される増幅率可変の多段増幅器と、 前記増幅器の最終段出力を入力とするA/D変
換器と、 前記A/D変換器出力を入力とし、前記A/D
変換器データの設定電圧を0dBとし、前記A/
D変換器出力と前記設定電圧を比較し、前記増幅
器の増幅率を数〜数10dB幅ごとに1レンジず
つ加減し、前記A/D変換器出力を0dBにする
制御手段とを備える多段増幅器のレンジ切換回路
[Claims for Utility Model Registration] A cascaded multi-stage amplifier with a variable amplification factor, an A/D converter whose input is the output of the final stage of the amplifier, and an A/D converter whose input is the output of the A/D converter, and the A/D converter whose input is the output of the A/D converter. D
The setting voltage of the converter data is 0 dB, and the above A/
A multi-stage amplifier comprising: a control means that compares the output of the D converter with the set voltage, adjusts the amplification factor of the amplifier by one range every several to several tens of dB, and sets the output of the A/D converter to 0 dB. Range switching circuit.
JP11523990U 1990-11-01 1990-11-01 Pending JPH0471021U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11523990U JPH0471021U (en) 1990-11-01 1990-11-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11523990U JPH0471021U (en) 1990-11-01 1990-11-01

Publications (1)

Publication Number Publication Date
JPH0471021U true JPH0471021U (en) 1992-06-23

Family

ID=31862993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11523990U Pending JPH0471021U (en) 1990-11-01 1990-11-01

Country Status (1)

Country Link
JP (1) JPH0471021U (en)

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