JPH0470972A - Fault simulating device - Google Patents

Abstract

PURPOSE:To improve the reliability of a fault classification, and to realize the easy improving operation of the test pattern of a designer by using the inside information of a logic block from a library used for the preparation of a logic circuit net list, and discriminating multiple faults and a single fault. CONSTITUTION:A fault definition is realized by obtaining a library 12 in addition to a logic circuit unit list 11 or the inside information of the logical block. Then, the multiple faults are identified and resolved S2 into the single fault from this fault definition, and the corresponding information is stored 15. A fault simulation S3 is operated by using this information 15 resolved into the single fault and the test pattern 13, and a fault classification S4 is operated after getting the resolved single fault back to the original multiple faults, based on both the simulation result 14 and the stored corresponding information 15. Thus, the fault definition can be obtained after adding the inside information of the logical block from the library, the reliability of the fault classification can be improved, and the improving operation of the test pattern of the designer can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is utilized in a failure simulation device used for designing integrated circuits. The present invention particularly relates to a failure simulation device that performs failure processing for LSI (Large Scale Integrated Circuit).

〔overview〕

The present invention provides a fault simulation device that performs fault simulation using test patterns from a logic circuit netlist designed by a semi-custom method, which uses internal information of a logic block using a library used to create a logic circuit netlist. By making it possible to distinguish between multiple failures and single failures, this system not only increases the reliability of failure classification, but also makes it easier for designers to improve test patterns.

[Conventional technology]

Conventionally, in the logic circuit netlist of a logically designed LSI in a semi-custom method such as a gate array or standard cell method, the internal circuit of a logic block selected from a library and used is not generally disclosed. Therefore, when performing failure simulation,
Designers often create test patterns only for faults defined for input and output terminals of logic blocks.

Currently, fault models for fault simulations commonly performed assume a stuck-at fault group and a stuck-at fault group at the input terminal or output terminal of a logic gate. In this case, when defining a fault in the input terminal 101 of the logic block 20 in FIG. 3(a), if there are multiple logic gates inside the logic block that receive or receive that input terminal, like,
Fault simulation may be performed using a multiple fault definition that simultaneously inserts stuck-at faults into the input terminals 102 and 103 of each logic gate 21 and 22 of the logic block 20.

At this time, among the logic blocks in the library, only those whose input terminals are connected to many internal logic gates have a higher fault density than other logic blocks, and the interaction between faults within the same logic block increases. The effect is also complicated. In addition, the third
In FIGS. (a) and (b), 23 is another logic gate section.

Therefore, if a failure is specified in the input terminal 201 of the logic block 30 in FIG. 4(a),
), attempts have been made to perform fault simulation by defining a single fault in each logic gate, such as the input terminals 202 and 203 of the internal logic gates that receive the input terminals. In addition, in FIGS. 4(a), 4(a) and 4(c), 33 is another logic gate section.

The fault simulation results are classified into detected and undetected faults, and the designer improves the test patterns created based on the classification results to increase the fault detection rate.

[Problem to be solved by the invention]

By the way, when a designer improves a test pattern, he or she uses the fault classification based on the fault simulation results and works to make the undetected faults detectable. Third
In handling multiple faults related to the input terminal 101 of the logic block 20 shown in Figures (a) and (a), the number of faults is 1'l based on the logic block name and the input terminal name named by the designer in the logic circuit netlist. However, as mentioned above, the reliability of fault classification is low due to the fault density regarding the input terminals.

In addition, when handling the fault related to the input terminal 201 of the logic block 30 shown in FIGS. 4(a), (b), and (C) by breaking it down into single faults, the name of the logic gate inside the logic block Even if a failure classification list is created by taking these factors into consideration, there is a drawback that it is difficult for designers to improve test patterns in the current situation where the connection information of logic gates inside the logic block is not made publicly available.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault simulation device that can output a fault classification list that has high reliability in fault classification and facilitates the designer's task of improving test patterns by eliminating the above-mentioned drawbacks. be.

[Means of fishing to solve problems]

The present invention provides a fault simulation device equipped with means for performing fault simulation using a test pattern from a logic circuit netlist designed by a semi-custom method, which uses the logic circuit list and the library used to design the logic circuit unit. A fault definition means that defines faults at the input terminals and output terminals of the logic blocks in this library, identifies a multiple fault definition from this defined fault, decomposes it into a single fault, outputs it, and decomposes it into this multiple fault. A multiple fault extraction and decomposition means that generates correspondence information with a single fault, a correspondence information storage means that stores the generated correspondence information, and a fault simulation using the test pattern and the output from the multiple fault extraction and decomposition means. fault simulation means for performing fault simulation and outputting fault simulation results; and fault classification for determining whether the output fault simulation results are multiple faults or single faults based on correspondence information stored in the correspondence information storage means. The present invention is characterized by comprising a classification processing means.

Further, in the present invention, when at least one single fault decomposed from multiple faults based on the correspondence information is detected, the fault classification processing means determines that multiple faults are detected in the corresponding logical block. The present invention is also characterized in that it includes means for determining that the corresponding logic block has no faults detected when no single fault has been detected.

[Effect]

Fault definition is performed by obtaining the internal information of the logic block from the library in addition to the IJ strike (logic circuit unit).

Then, from this fault definition, multiple faults are identified and decomposed into single faults, and the corresponding information is stored.Fault simulation is performed using the information decomposed into single faults and the test pattern. Based on the correspondence information stored for the simulation results, the decomposed single fault is returned to the original multiple fault and fault classification is performed.

Therefore, since the fault definition is performed by adding the internal information of the logical block from the library, it is possible to increase the reliability of fault classification and to facilitate the designer's task of improving the test pattern.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment is a fault simulation device equipped with a means for performing fault simulation using a test pattern 13 from a logic circuit netlist 11 designed by a semi-custom method such as gate array and mask slicing. However, based on the logic circuit netlist 11 and the library 12 used for designing this logic circuit unit, the fault definition means 1 that defines faults at the input terminals and output terminals of the logic blocks in this library 12, and this definition. a multiple information extracting and decomposing means 2 for identifying multiple faults from the detected faults, decomposing them into single faults and outputting them, and generating correspondence information 15a between the multiple faults and the decomposed single faults; and the generated correspondence information. 15a as a correspondence information storage means, a failure simulation means 3 that performs a failure simulation using the test pattern 13 and the output of the multiple fault extraction and decomposition means 2, and outputs a staining result 14; The output simulation result 14 is converted into the correspondence information 15 stored in the correspondence information file 15.
Fault classification processing means 4 that determines whether it is a multiple fault or a single fault based on a, performs fault classification, and creates a fault classification list 16.
It is equipped with

Next, the operation of this embodiment will be explained with reference to the flowchart shown in FIG.

First, in step S1, the fault definition means 1
A fault definition is generated for the logic circuit portion that the designer intends to test. At this time, the internal information of the logical block is obtained from the library 12.

Next, in step S2, the multiple fault extraction and decomposition means 2 defines faults for the input terminals and output terminals of the logic blocks used in the logic circuit netlist 11. At this time, failures that appear to be multiple failures are decomposed into single failures based on the input terminal layout. At the same time, correspondence information 15a between this multiple failure and the decomposed single failure is created and stored in the correspondence information file 15.

Next, in step S3, in order to detect a fault defined in the logic circuit netlist 11, the fault simulation means 3 uses the test pattern 13 created by the designer, the logic circuit netlist 11, and the library. 12 and the fault definition, fault simulation is performed to obtain a simulation result 14.

Next, in step S4, the fault classification processing means 4 uses the simulation result 14 and the correspondence information 15a of multiple faults and single faults stored in the correspondence information file 15 to identify at least one of the decomposed single faults. When a fault is detected, it is assumed that a fault at the input terminal of the corresponding logic block, that is, a multiple fault has been detected, and outputted to the fault classification list 16 as a fault at the input terminal of this logic block is detected. Furthermore, if all the decomposed single faults are undetected, the input terminal fault of the logic block corresponding to the single fault is also output to the fault classification list 16 as being undetected. Here, for a normal single fault that does not correspond to multiple faults, its detection or non-detection is simply output to the fault classification list 16.

[Effects of the Invention] As explained above, the present invention provides an LSI that is designed by selecting and combining necessary logic blocks from libraries such as gate arrays and standard cells. Since internal logic information is also used, the reliability of the classification of faults detected and undetected obtained from fault classification processing is improved. Furthermore, it is possible to output a failure classification list that makes it easier for designers to improve test patterns.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a flowchart showing the operation. Figures 3(a) and 3) are processing examples (1) in the conventional example.
An explanatory diagram showing. FIGS. 4A, 4B, and 4C are explanatory diagrams showing processing example (2) in the conventional example. DESCRIPTION OF SYMBOLS 1... Fault definition means, 2... Multiple fault extraction and decomposition means, 3... Fault simulation means, 4... Fault classification processing means, 11... Logic circuit netlist, 12.
...Library, 13...Test pattern, 14...
・Simulation results, 15... Correspondence information file, 15a... Correspondence information, Engineering 6... Failure classification list,
20.30...Logic block, 21.22.31.3
2...Logic gate, 23.33...Other logic gate section, 101.102.103.201.202.203.
...Input terminal.

Claims (1)

[Scope of Claims] 1. In a fault simulation device equipped with means for performing fault simulation using a test pattern from a logic circuit netlist designed by a semi-custom method, the logic circuit list and the logic circuit unit used in designing the logic circuit unit are provided. The library includes a fault definition means that defines faults at the input terminals and output terminals of logic blocks in this library, and identifies multiple fault definitions from the defined faults, decomposes them into single faults, and outputs them. multiple fault extraction and decomposition means for generating correspondence information between the test pattern and the decomposed single fault; a correspondence information storage means for storing the generated correspondence information; and an output from the test pattern and the multiple fault extraction and decomposition means. a fault simulation means for performing a fault simulation and outputting a fault simulation result; 1. A failure simulation device comprising: failure classification processing means for performing classification. 2. The fault classification processing means determines that multiple faults have been detected in the corresponding logical block when at least one single fault that has been decomposed from multiple faults based on the correspondence information is detected, and 2. The fault simulation apparatus according to claim 1, further comprising means for determining that no fault has been detected in the corresponding logic block when no single fault has been detected.