JPH0470931A - Arithmetic allocation method for logical synthesization - Google Patents

Abstract

PURPOSE:To perform the arithmetic allocation in a short time by dividing an intermediate code to attain the parallel processing of the arithmetic allocation. CONSTITUTION:A source interpreting part 1 is provided to evolve a source program into an intermediate code together with a block dividing part 2 which divides the intermediate code into blocks, and a scheduling part 3 which applies the arithmetic allocation to each divided block, and a block integrating part 4 which collects the divided blocks into a single body. Therefore an intermediate code is divided into blocks that have the reduced interactions as much as possible. The arithmetic allocation is carried out to the divided blocks in parallel with each other by means of plural processors. Then these blocks undergone the arithmetic allocation can be collected into a single body. Thus the arithmetic allocation is attained in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a logic synthesis operation allocation method for extracting parallelism in a logic synthesis algorithm.

Conventional technology Recently, in the field of logic synthesis, in order to synthesize hardware that executes in parallel from sequential programs such as C language, calculation assignment that extracts the parallelism of algorithms has become popular. .

Conventional methods for allocating operations in logic synthesis include, for example, a method using simulated rad annealing. A method using simulated rad annealing will be described below.

First, the current temperature is set, and the cost for the current operation allocation is calculated. Next, an operation is selected at random, and the cost when the allocated operation units and steps are changed is calculated. Then, when the cost is lower than the current cost, the allocation of operations is actually changed. If the cost is higher than the current cost, it is determined based on the difference in cost and temperature whether or not to actually make the change. The temperature is high;
The smaller the cost difference, the greater the probability of change. If changed, that cost becomes the new current cost. While making the above changes, gradually lower the temperature. If the calculation assignment is not changed several times in a row, that calculation assignment is taken as the final result.

Problems to be Solved by the Invention However, in the above method, as the number of operations to be allocated increases, the number of changes must also increase, and the time required to calculate the cost also increases. The problem was that it was rapidly increasing.

In view of the above problems, it is an object of the present invention to perform calculation assignments in a short time by processing the calculation assignments in parallel.

Means for Solving the Problems To achieve this object, the present invention provides a source interpreter that interprets sentences of a given source program and develops it into intermediate code, and a source interpreter that interprets the sentences of a given source program and develops it into intermediate code. It consists of a block dividing unit that divides the blocks into blocks, a scheduling unit that uses multiple processors to allocate calculations to each block in parallel, and a block integration unit that combines the blocks to which calculations have been allocated. The intermediate code is divided so that it can be processed in parallel.

Effect of the present invention With the above configuration, the intermediate code is divided into blocks with as little interaction as possible, and a plurality of processors are used in parallel to execute calculation assignments for each block, and each block to which the calculation assignment has been performed. By combining these into one, calculation assignments can be made in a short time.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the logical synthesis operation allocation method according to the present invention. In FIG. 1, 1 is a source interpreter that develops a source program into intermediate code, 2 is a block division unit that divides the intermediate code into blocks, 3 is a scheduling unit that assigns operations to each divided block, and 4 is a block integration unit that combines blocks into one.

The operation of the configuration shown in FIG. 1 as described above will be explained below with reference to the flowchart shown in FIG. 2.

First, the source interpreter 1 interprets the sentences of the source program and develops it into intermediate code.

Next, the block dividing unit 2 divides the intermediate code into blocks that have little interaction with each other. Blocks that have little interaction with each other are blocks that have a small number of operations that can be executed by another block due to dependencies in intermediate code.

FIG. 2 is an example of a flow chart in the block dividing section 2 for dividing into such blocks.

Creation 21 of the data flow graph is performed by the source interpretation unit 1.
From the intermediate code as shown in Fig. 3 converted by
Create the data flow graph shown in the diagram. That is, a clause indicating a load corresponding to the intermediate code ri=to'' and a clause indicating addition corresponding to the intermediate code ra=i+tl are prepared. Then, from the data dependencies, the intermediate code ra=
Since the addition corresponding to "i+t1" must be executed after the load corresponding to the intermediate code ri=toJ, this is indicated by an arrow. In the same manner, the data flow graph shown in FIG. 4 is created.

Step range determination 22 determines the step range that can be assigned to each operation based on the data flow graph. That is, by assigning the intermediate code to the step as early as possible in order from the top, as shown in FIG. 5(A).
Step assignment as shown in Figure 5 (b) is performed by assigning the intermediate code from the bottom to the next possible step. Then, in Figure 5 (^) The calculation step range is from the assigned step to the assigned step in FIG. 5(B). FIG. 6 is the step range obtained from the step assignment shown in FIG.

Step range distribution graph creation 23 creates a step range distribution graph in which the number of step ranges that intersect between each step is calculated. For example, the step range distribution graph shown in FIG. 7 is created from the step range shown in FIG.

The division between steps 24 is performed by repeatedly dividing the block into two based on the step range distribution graph created in step range distribution graph creation 23.
Split into multiple blocks that have little interaction with each other. First, the step range distribution graph is divided between the smallest steps. However, if there are multiple steps where the distribution graph is the minimum, the block is divided at the point where the difference in the number of intermediate coats between the two blocks when divided is the minimum. Similarly, the two divided blocks are divided between the steps that have the minimum steps within the block. This process is repeated until the number of intermediate codes included in the block becomes sufficiently small.

When the intermediate code is divided into blocks in this way,
The scheduling unit 3 performs calculation assignment for each block independently using simulated rad annealing. Needless to say, the calculation assignment for each block is executed in parallel using a plurality of processors.

Finally, the block integration unit 4 integrates the blocks to which calculations have been assigned.

As described above, according to the present embodiment, by providing the block division section 2 and the block integration section 4 and executing the calculation assignment in parallel, the calculation assignment can be performed in a short time. In this embodiment, the scheduling unit 3 performs calculation reduction using simulated rad annealing, but any calculation allocation method in which the execution time of calculation allocation increases as the number of allocated calculations increases, can be similarly applied. effect can be obtained.

Effects of the Invention As described above, the present invention includes a source interpretation unit that interprets sentences of a given source program and develops it into intermediate code, and a block division unit that divides the intermediate code into blocks that have little interaction with each other. , using multiple processors,
It consists of a scheduling section that assigns operations to each block in parallel, and a block integration section that combines the blocks to which operations have been assigned, and is configured to divide the intermediate code so that operation assignments can be processed in parallel. By dividing the intermediate court into blocks and executing the calculation assignments for each pro and ivy in parallel, the calculation assignments can be made in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the logic synthesis operation assignment method according to the present invention, and FIG. 2 is a block diagram showing a main part of an embodiment of the logic synthesis operation assignment method according to the present invention. FIG. 3 is a flowchart showing the operation of the dividing section, FIG. 3 is an intermediate code illustrating the operation of the operation assignment method for logic synthesis according to the present invention, and FIG. 4 is a flowchart showing the operation of the operation assignment method for logic synthesis according to the present invention. The conceptual diagram of the data flow graph, Figures 5 (A) and (11), explain
5(A) is a conceptual diagram of step assignment, FIG. 5(+1) is a conceptual diagram showing assigned steps,
FIG. 6 is a conceptual diagram of a step range explaining the operation of the operation assignment method for logic synthesis according to the present invention, and FIG. 7 is a step range distribution graph illustrating the operation of the operation assignment method for logic synthesis according to the present invention. It is the intention. 1... Source interpretation section, 2... Block division section, 3... Scheduling section, 4...
...Block integration department. Patent applicant: Director of the Agency of Industrial Science and Technology Ken Sugiyu

Claims (1)

[Claims] A source interpreter interprets the sentences of a given source program and develops it into intermediate code, and a block divider divides the intermediate code into blocks that have little interaction with each other, using multiple processors in parallel. Logic comprising a scheduling unit that assigns operations to each block, and a block integration unit that combines the blocks to which operations have been assigned, and divides the intermediate code so that the assignments of operations can be processed in parallel. Composite operation assignment method.