JPH0469773A - Logical composite system - Google Patents

Abstract

PURPOSE:To shorten the processing time by executing technical mapping by utilizing a function kind table for the technical mapping generated automatically, and a mapping rule of every function kind. CONSTITUTION:The system is constituted of a logical description input part 1 for inputting a logical description of a logical composite object circuit, a library input part 2 for inputting a library of target technology, a library storage part 3 for holding the library, a rule generating part 4 for generating a technology mapping rule from the library, a rule base part 5 in which a logical composite rule is stored, a synthesizing part 6 for executing logical synthesis, a temporary storage part 7 for holding the midst of synthesis and a final result, and an output part 8 for outputting a circuit description. In such a state, a logical composite rule having a function kind table classified into every fundamental element of the library of an applied technique and a technical mapping rule corresponding to every function kind is generated, and by this logical composite rule, a partial circuit of a logical composite object circuit and the fundamental element are compared and the partial circuit subjected to matching to the maximum is determined. In such a way, the processing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic synthesis system, and particularly to a synthesis system used for designing digital logic circuits using CAD.

[Conventional technology]

Conventionally, this type of logic synthesis system has been comprised of a technology-independent optimization processing section, a technology mapping processing section, and a technology-dependent optimization processing section.

In the technology mapping processing section, A in the circuit to be synthesized is
For partial circuits such as ND and OR, mapping is performed by sequentially searching for library basic elements to be matched and selecting the most suitable one among the matched basic elements.

In this case, for a composite game consisting of multiple gates), one game I among the gates constituting the composite gate is
・Matching was performed, and each of the peripheral circuits of the matched gates was matched.Finally, the most suitable basic element of the matched library was selected and mapped.

[Problem to be solved by the invention]

In the conventional logic synthesis system described above, after performing technology-independent optimization processing, during technology mapping, the subcircuits of the circuit to be synthesized are matched with basic elements in all libraries, or After narrowing down the functions of the basic life elements, matching is performed, which has the disadvantage of increasing the number of matching operations and lengthening the processing time.

Also, when matching with composite case 1~, a certain case 1
After matching .

[Failure to solve the problem]

The logic synthesis system of the present invention includes a logic synthesis rule creation unit that includes means for creating a logic synthesis rule having a function type table classified by basic element of a library of applied technologies and a technology pine pink rule corresponding to each function type. and means for comparing a partial circuit of a logic synthesis target circuit with the basic element and determining the partial circuit that provides the maximum matching based on the logic synthesis rule.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention.

Referring to FIG. 1, the logic synthesis system of the present invention includes a logic description input unit 1 that inputs a logic description of a circuit to be synthesized.
, a library input unit 2 that inputs the Targetera I Technology library, a library storage unit 3 that holds the input library, a rule creation unit 4 that creates technology mapping rules from the input library, and rules that store logic synthesis rules. A base unit 5, a synthesis unit 6 that performs logic synthesis, a temporary storage unit 7 that holds intermediate and final results of synthesis, and an output unit 8 to 414 that outputs a circuit description of the synthesis result.
will be accomplished.

Next, the operation of the present invention will be explained with reference to the drawings.

A library that describes the functions, input/output terminals, etc. of each basic element of Turkella 1 to Dekurotsuji when logic 6 is implemented is input from the library input section 2, converted into an internal data structure, and stored in the library storage section 3.

Details of the rule creation section 4 are shown in FIG.

The rule creation unit 4 first searches input port 1 to configuration for each basic element with a similar function using the functional unit table creation means 41 shown in FIG. 2 for each basic element stored in the library storage unit 3. Create a table that is differentiated by the difference between the two.

- As an example, FIG.
An example of a functional type table of an OR circuit is shown.

\/ Input signal pattern 1-1 is 2-manpower 0R13-22 is 3-manpower NOR, fan-in source is 3-manpower A, N Dl,
Composite game 1 where two people A, N D are connected
~． 2-1. -1 represents a composite game 1~ in which one (2-person ANI) is connected to the fan-in source of the 3-person NOR.

Next, if the classification end determination means 42 determines that there are basic elements in the library that have not been classified by function type, the process returns to the function type table creation means 41. When all the basic elements in the library have been classified and each functional type is completed, the technology pin rule creation means 43
A technology mapping rule is created for each functional type, and the created technology mapping rule is registered in the rule base unit 5 by the rule registration means 44.

Next, the specification description of the circuit to be synthesized is inputted from the logic description input section 1, converted into an internal data structure, and then converted into a temporary storage section 7.
Store in.

Details of the synthesizing section 6 are shown in FIG.

First, the technology-independent optimization means 6 performs technology-independent logic optimization on the logic synthesis target circuit description stored in the -time storage section.

The configuration of the technology mapping means 62 is shown in FIG.

The technology mapping means 62 uses the mapping rule selection means 621 to select the technology mapping rule stored in the rule base unit 5 for the circuit that has undergone technology-independent optimization, and the partial circuit matching means 622 selects the technology mapping rule stored in the rule base section 5. , performs matching of partial circuits of the circuit to be synthesized.

The function type determination means 623 refers to the function type table and determines whether there is a basic element of the library that can be matched at maximum with the matched partial circuit and the partial circuit including its peripheral circuits.

If there is no basic element to be matched at maximum on the function type table, the circuit division means 624 first divides the matching sawtooth partial circuit l~, and the matsupin rule selection means 621
Return to

If there is a basic element that can be matched to the maximum on the function type table, the matched partial circuit is mapped to the basic element in the library by the mapping means 625.

For example, when applying the matching rule with a NOR circuit, there are 3 human ORs in the circuit to be synthesized, and the 3
Three people each under one fan-in A, N D
1, 2 manual AND 2, there is a description of the corresponding input button: 3-2-2 in the OR circuit table in Figure 5, which shows that there are basic elements that can configure this circuit in the library. , this rule succeeds and the corresponding primitive is pine pink.

Next, if the matching completion determination means 626 determines that mapping processing for all of the synthesis target circuits remains, the process returns to the partial circuit mapping processing 622.

If there is no pine pink processing remaining (if there is a technology mapping rule that has not been applied), the rule application completion determination means 627 returns to the rule selection means 621; if not, the technology mapping processing is terminated.

The synthesis target circuit for which the technology pin pink has been completed is subjected to technology-dependent optimization such as deletion of redundant circuits by the technology-dependent optimization means 63 of the synthesis unit 6. When the logic synthesis of all the circuits to be synthesized is completed, the circuit description stored in the -time storage section 7 is outputted from the output section 8.

〔Effect of the invention〕

As explained above, the present invention utilizes automatically created functional type rules for technology mapping and technology mapping using the Matsupin rules for functional types, so the library of the target circuit for synthesis and the target technology is mapped. This has the significant effect that the number of pattern matchings with each basic element can be reduced and the processing time can be shortened.

42... Classification end determination means, 43... Functional type technology mapping rule creation means, rule registration means.

Claims (1)

[Claims] A logic synthesis rule creation unit including means for creating a logic synthesis rule having a function type table separated for each basic element of a library of applied technologies and a technology mapping rule corresponding to each function type, and the logic synthesis rule,
A logic synthesis system comprising means for comparing a subcircuit of a logic synthesis target circuit with the basic element and determining the subcircuit with maximum matching.