JPH0469422B2 - - Google Patents

Info

Publication number
JPH0469422B2
JPH0469422B2 JP58176781A JP17678183A JPH0469422B2 JP H0469422 B2 JPH0469422 B2 JP H0469422B2 JP 58176781 A JP58176781 A JP 58176781A JP 17678183 A JP17678183 A JP 17678183A JP H0469422 B2 JPH0469422 B2 JP H0469422B2
Authority
JP
Japan
Prior art keywords
heat treatment
defect
wafer
density
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58176781A
Other languages
Japanese (ja)
Other versions
JPS6066827A (en
Inventor
Yasushi Shimanuki
Hisaaki Suga
Mitsuhiro Kainuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP17678183A priority Critical patent/JPS6066827A/en
Publication of JPS6066827A publication Critical patent/JPS6066827A/en
Publication of JPH0469422B2 publication Critical patent/JPH0469422B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Description

【発明の詳細な説明】 本発明は、半導体素子製造工程におけるシリコ
ン単結晶ウエハー中の結晶欠陥導入の際、所望の
欠陥密度を得るための熱処理条件を的確に予測す
る方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for accurately predicting heat treatment conditions for obtaining a desired defect density when introducing crystal defects into a silicon single crystal wafer in a semiconductor device manufacturing process.

現在IC、LSI等の半導体素子製造工程において
は、工程中に必然的に生ずる汚染物を凝集させる
活性点として積層欠陥や転位などの結晶欠陥をウ
エハー内部に発生させ、ウエハー表面近傍の電気
的活性層の電気的特性の向上を計るために、予め
所定密度の結晶欠陥をウエハー内部に導入するよ
うにしている。そして、この結晶欠陥の導入は熱
処理によつて行われている。
Currently, in the manufacturing process of semiconductor devices such as ICs and LSIs, crystal defects such as stacking faults and dislocations are generated inside the wafer as active sites that agglomerate contaminants that are inevitably generated during the process. In order to improve the electrical properties of the layer, crystal defects at a predetermined density are introduced into the wafer in advance. The introduction of crystal defects is performed by heat treatment.

この熱処理は、基本的には600〜1050℃の温度
範囲において特定温度および特定時間で熱処理す
るか、あるいは上記温度範囲にて、低温から特定
の昇温速度で昇温させて熱処理して、ウエハー内
に所望密度の欠陥核を導入したうえ、さらに1000
〜1200℃の温度範囲で特定時間熱処理し、上記欠
陥核から欠陥を発生させることによつて行われる
のが一般的である。
This heat treatment is basically performed at a specific temperature and for a specific time in the temperature range of 600 to 1050 degrees Celsius, or by heating the wafer in the above temperature range by increasing the temperature from a low temperature at a specific temperature increase rate. In addition to introducing the desired density of defect nuclei within the
This is generally carried out by heat treatment at a temperature range of ~1200°C for a specific period of time to generate defects from the defect nuclei.

しかしながら、このような熱処理によつて生成
する結晶欠陥は、上記熱処理条件は勿論の事、ウ
エハーがこれまで受けてきた熱履歴、初期固溶酸
素濃度、炭素濃度などによつても種々に影響を受
けるため、所定の欠陥密度を得るための熱処理条
件の設定が困難であり、再現性が乏しくまた、対
象とするウエハーにとつて効率的な熱処理条件を
選択していないという欠点があつた。
However, crystal defects generated by such heat treatment are variously affected by not only the above heat treatment conditions but also the thermal history that the wafer has undergone, initial solid solution oxygen concentration, carbon concentration, etc. Therefore, it is difficult to set heat treatment conditions to obtain a predetermined defect density, resulting in poor reproducibility and disadvantages in that efficient heat treatment conditions are not selected for the target wafer.

本発明は上記事情に鑑みてなされたもので、対
象ウエハーに所望の欠陥密度を確実に発生させる
ことのできる熱処理条件を的確に予測することの
できるシリコンウエハー中への結晶欠陥導入制御
法を提供することを目的とするものである。
The present invention has been made in view of the above circumstances, and provides a method for controlling the introduction of crystal defects into silicon wafers that can accurately predict heat treatment conditions that can reliably generate a desired defect density in the target wafer. The purpose is to

以下、本発明を詳細に説明する。 The present invention will be explained in detail below.

本発明の結晶欠陥導入制御法は予め、熱履歴、
初期固溶酸素濃度等などの履歴が明確なシリコン
単結晶ウエハーに種々の温度、時間の熱処理条件
で第1段の熱処理を施して、欠陥核を導入したう
え、これをさらに第2段の熱処理して、先の欠陥
核を計測可能なまで成長せしめたのちこれを計測
して上記第1段の熱処理によつて導入された欠陥
核密度を求め、これを各履歴毎に第1段の熱処理
時の温度−時間グラフ上に等密度曲線として描い
て標準グラフを作成しておき、この標準グラフを
用いて、新しく欠陥を導入すべきウエハーについ
て所望の欠陥密度を生成せしめる必要な熱処理時
間、温度(熱処理条件)を予測するものである。
The crystal defect introduction control method of the present invention is based on thermal history,
A first stage heat treatment is performed on a silicon single crystal wafer with a clear history such as initial solid solution oxygen concentration, etc. under heat treatment conditions of various temperatures and times to introduce defect nuclei, which is then further subjected to a second stage heat treatment. After growing the defective nuclei until they can be measured, the density of defective nuclei introduced by the first-stage heat treatment is determined, and this is determined for each history by the first-stage heat treatment. A standard graph is created by drawing it as an isopycnic curve on the temperature-time graph of (heat treatment conditions).

まず、履歴の明確なシリコン単結晶ウエハーを
用意することになるが、通常は欠陥生成に極めて
大きな影響を与える初期固溶酸素濃度(以下、
O2濃度と略称する。)がわかつているものを数種
選べばよい。このウエハーを適当なサイズの試片
に裁断し、この試片に第1段の熱処理を施す。こ
の時の温度は650〜1050℃の範囲とされ、650℃未
満および1050℃を越えると欠陥核導入に長時間を
要するかもしくは欠陥核が発生しない不都合があ
る。また、時間は2分〜300時間とされ、2分未
満ではウエハー熱処理の制御が難しく、また300
時間を越えると長時間となり、実際的でなくな
る。そして、この温度、時間条件範囲内で、でき
るだけ多くの異つた条件で、できるだけ多くのウ
エハーを熱処理することにより、得られる標準グ
ラフの精度が高くなり、好ましい。
First, a silicon single crystal wafer with a clear history is prepared, but normally the initial solid solution oxygen concentration (hereinafter referred to as
It is abbreviated as O 2 concentration. ) can be selected from several items for which the following information is known. This wafer is cut into test pieces of an appropriate size, and the test pieces are subjected to a first heat treatment. The temperature at this time is in the range of 650 to 1050°C, and if it is less than 650°C or exceeds 1050°C, it will take a long time to introduce defect nuclei or there will be a disadvantage that defect nuclei will not be generated. In addition, the time is 2 minutes to 300 hours, and if it is less than 2 minutes, it is difficult to control the wafer heat treatment;
If the time is exceeded, it becomes too long and becomes impractical. It is preferable to heat treat as many wafers as possible under as many different conditions as possible within this range of temperature and time conditions, as this will increase the accuracy of the standard graph obtained.

つぎに、このようにしてウエハー試片に導入さ
れた欠陥核を、欠陥核が実際できるまで成長させ
るための第2段目の熱処理が行われる。この熱処
理条件は1000〜1200℃で10分〜10時間とされる。
1000℃未満では欠陥核から欠陥が発生するのに長
時間を要し、1200℃を越えると欠陥核の再固溶、
発生した欠陥の消滅が起る。また、10分未満では
欠陥の検出、計測が容易でなく、10時間を越える
と発生した欠陥の数の飽和もしくは減少が生じて
不都合となる。
Next, a second stage heat treatment is performed to grow the defective nuclei thus introduced into the wafer specimen until the defective nuclei are actually formed. The heat treatment conditions are 1000 to 1200°C for 10 minutes to 10 hours.
At temperatures below 1000°C, it takes a long time for defects to form from defective nuclei, and at temperatures above 1200°C, defective nuclei re-dissolve into solid solution.
Disappearance of the generated defect occurs. Further, if the time is less than 10 minutes, it is not easy to detect or measure defects, and if the time exceeds 10 hours, the number of defects generated will become saturated or decrease, which is disadvantageous.

かくして生成されたウエハー中の欠陥は、選択
エツチングによるエツチヒング像からの欠陥の計
数、透過電子顕微鏡による透過明視野像と暗視野
像からの欠陥の計数等の測定法によつて、その密
度が求められる。なお、選択エツチング法により
表面に現われた像の形状から欠陥の種類(積層欠
陥、転位、析出物)の判別も可能である。
The density of the defects in the wafer thus generated can be determined by measurement methods such as counting defects from etching images obtained by selective etching, and counting defects from transmitted bright-field and dark-field images using a transmission electron microscope. It will be done. Note that it is also possible to determine the type of defect (stacking fault, dislocation, precipitate) from the shape of the image that appears on the surface using the selective etching method.

このようにして求められた個々のウエハー試片
についての欠陥密度は、第1段目の熱処理の温度
−時間グラフ上に等密度曲線として描かれ、個々
のO2濃度に対応した標準グラフが得られる。
The defect density for each wafer specimen determined in this way is drawn as an isopycnic curve on the temperature-time graph of the first stage heat treatment, and a standard graph corresponding to each O 2 concentration is obtained. It will be done.

この標準グラフを得るためには、上述のよう
に、広い温度範囲と広い時間範囲にわたつて数多
くのウエハー試片を用いて異なる条件で熱処理を
行わないと欠陥発生の状況を知ることができな
い。すなわち、O2濃度が欠陥発生に支配的な役
割を果すが、なおそれ以外の結晶引上条件や炭素
濃度によつても影響を受けていると考えられる部
分も多く、O2濃度からだけでは正確な欠陥発生
を予測することは難しいためである。
In order to obtain this standard graph, as mentioned above, it is not possible to know the state of defect occurrence unless heat treatment is performed using a large number of wafer specimens under different conditions over a wide temperature range and a wide time range. In other words, although O 2 concentration plays a dominant role in defect generation, there are many other factors that are thought to be influenced by other crystal pulling conditions and carbon concentration, and it is not possible to determine whether O 2 concentration alone This is because it is difficult to accurately predict the occurrence of defects.

つぎに、このようにして得られた標準グラフを
用いて、処理対象とするウエハーに所望の欠陥密
度を形成せしめるための熱処理条件を予測する一
般的手順について説明する。
Next, a general procedure for predicting heat treatment conditions for forming a desired defect density in a wafer to be processed will be described using the standard graph obtained in this manner.

(イ) まず、処理対象ウエハーのO2濃度に対応す
るグラフを選択する。定性的にはO2濃度が高
ければあるいは処理温度が高ければ欠陥の発生
する時間が短くなる。あらゆる処理対象のウエ
ハーの欠陥発生を定量的に予測することは難し
いが、近年の結晶育成技術の向上により欠陥の
発生状況は安定化の方向に向いつつある。した
がつて、特定の育成条件で引上げられたシリコ
ン単結晶の欠陥発生条件を把握しておけば、そ
れに近い条件範囲で引上げられた単結晶につい
ての欠陥発生は外挿により精度よく推定でき、
簡単な確認熱処理を行うだけで、処理対象ウエ
ハーの欠陥発生を正確かつ効率的に実現でき
る。
(b) First, select the graph corresponding to the O 2 concentration of the wafer to be processed. Qualitatively, the higher the O 2 concentration or the higher the processing temperature, the shorter the time for defects to occur. Although it is difficult to quantitatively predict the occurrence of defects in any wafer to be processed, recent improvements in crystal growth technology have led to stabilization of the defect occurrence situation. Therefore, if we know the defect occurrence conditions for silicon single crystals pulled under specific growth conditions, we can accurately estimate the defect occurrence for single crystals pulled under similar conditions by extrapolation.
By simply performing a simple confirmation heat treatment, it is possible to accurately and efficiently detect defects in the wafer being processed.

(ロ) 次に、選択された標準グラフに示された密度
の欠陥が実際に発生するかどうかを確認するた
めに処理対象ウエハーの1枚を熱処理する。こ
の時の熱処理条件は標準グラフを見て適当に選
択すればよい。
(b) Next, one of the wafers to be processed is heat-treated to check whether defects having the density shown in the selected standard graph actually occur. The heat treatment conditions at this time can be appropriately selected by looking at the standard graph.

(ハ) 上記確認熱処理したウエハーの欠陥発生密度
と選択した標準グラフから予想した欠陥密度と
の差異を調べる。この差が小さければ選択した
標準グラフ中の欠陥の等密度曲線を確認熱処理
で得られた値に一致するように長時間側もしく
は短時間側にずらして補正すればよい。また、
この差が大きくこのような補正が行えないよう
な場合は、予め用意しておいた他の標準グラフ
のいずれに近いか判断がつくだけの確認熱処理
を行い、処理対象ウエハーの欠陥の発生に対応
する標準グラフを選ぶ。
(c) Examine the difference between the defect occurrence density of the wafer subjected to the above confirmation heat treatment and the defect density predicted from the selected standard graph. If this difference is small, the isodensity curve of defects in the selected standard graph may be corrected by shifting it to the longer time side or the shorter time side so that it matches the value obtained in the confirmation heat treatment. Also,
If this difference is large enough that such correction cannot be performed, perform heat treatment to determine whether the wafer is close to other standard graphs prepared in advance, and take measures to prevent defects in the wafer being processed. Select the standard graph to use.

(ニ) 処理対象ウエハーの欠陥発生の熱処理条件に
よる変化の状況と上記標準グラフの等密度曲線
とを比較対象して、所望の欠陥種と欠陥密度が
得られるための最も効率的で確実な熱処理条件
を予測、設定する。処理対象ウエハーの実際の
処理は定温熱処理を行つて急冷してもよく、ま
た高温から冷却条件を調整することによつて行
つてもよい。
(d) Compare the changes in the occurrence of defects in the wafer to be processed due to heat treatment conditions with the isodensity curve of the standard graph above to determine the most efficient and reliable heat treatment to obtain the desired defect types and defect density. Predict and set conditions. The actual processing of the wafer to be processed may be carried out by performing constant temperature heat treatment to rapidly cool it, or may be carried out by adjusting the cooling conditions from a high temperature.

かくして得られた(予測した)熱処理条件によ
つて、処理対象ウエハーを熱処理した場合、所望
の欠陥密度を高い精度で導入することができ、生
成欠陥密度のバラツキを従来法に比べて著しく小
さくできる。また、所望の欠陥密度を得るために
効率的な(短時間)処理条件を知ることができ、
コスト低減も可能となる。
When the wafer to be processed is heat treated using the heat treatment conditions obtained (predicted) in this way, the desired defect density can be introduced with high precision, and the variation in the generated defect density can be significantly reduced compared to conventional methods. . In addition, it is possible to know efficient (short-time) processing conditions to obtain the desired defect density.
Cost reduction is also possible.

以下、実施例を示して具体的に説明する。 Hereinafter, a specific explanation will be given by showing examples.

実施例 1 標準グラフを作製するため、CZ法で引き上げ
られたO2濃度が○イ1.95×1018原子/cm3、○ロ1.29×
1010原子/cm3、○ハ1.65×1018原子/cm3の3種のシ
リコン単結晶ウエハー(直径104cm、厚み500μ
m)各15枚から1枚を8枚分割して計120枚の同
一O2濃度の試料片を作製した。全試料片数は360
枚となる。これらの試料片を拡散用熱処理炉中、
窒素雰囲気下650〜1050℃の範囲の種々の温度で、
熱処理時間を変えて処理することにより欠陥核を
導入した。(第1段の熱処理) この欠陥核密度測定のために、3種の熱処理試
料を拡散用熱処理炉中に入れ水蒸気雰囲気下、
1100℃で1時間熱処理したのち、急冷し、(第2
段の熱処理)エツチング法、透過電子顕微鏡法に
よつて欠陥密度を実測した。なお、○イ、○ロの試料
については積層欠陥のみならず、転位、析出物に
ついてもその密度を測定した。得られた欠陥密度
の値を先の熱処理における温度−時間グラフ上に
プロツトし、等密度点を結んで等密度曲線を描
き、第1図ないし第5図を得た。第1図および第
2図はいずれもO2濃度が1.95×1018原子/cm3のウ
エハーについての標準グラフで、第1図は積層欠
陥密度の、第2図は転位および析出物密度の等密
度曲線を示す。また、第1図中の白丸印は実施し
た熱処理条件を示し、破線で示したカーブは飽和
密度に達する時間を示す。第3図および第4図
は、いずれもO2濃度が1.29×1018原子/cm3のウエ
ハーの標準グラフで、第3図は積層欠陥密度の、
第4図は転位および析出物密度の等密度曲線を示
す。また、第3図中の白丸印は実施した熱処理条
件を示し、破線で示したカーブは飽和密度に達す
る時間を示す。第5図はO2濃度が1.65×1018
子/cm3のウエハーについての積層欠陥密度の等密
度曲線を示し、白丸印は実施した熱処理条件を示
し、破線で表したカーブは飽和密度に達する時間
を示す。また、第5図には熱処理として高温から
冷却条件を調整して行つた場合についての冷却曲
線A、B、Cが併せて記入してあり、A、Bにあ
つては1100℃からの冷却曲線、Cにあつては1280
℃からの冷却曲線である。
Example 1 To create a standard graph, the O 2 concentration raised by the CZ method was 1.95×10 18 atoms/cm 3 and 1.29×
Three types of silicon single crystal wafers (diameter 104cm , thickness 500μ
m) A total of 120 sample pieces with the same O 2 concentration were prepared by dividing each of the 15 pieces into 8 pieces. Total number of specimen pieces is 360
It becomes one piece. These sample pieces were placed in a diffusion heat treatment furnace.
At various temperatures ranging from 650 to 1050℃ under nitrogen atmosphere,
Defect nuclei were introduced by changing the heat treatment time. (First stage heat treatment) In order to measure the density of defect nuclei, three types of heat treated samples were placed in a diffusion heat treatment furnace and heated under a steam atmosphere.
After heat treatment at 1100℃ for 1 hour, quenching
Defect density was actually measured by etching (step heat treatment) and transmission electron microscopy. Note that for the samples ○A and ○B, the density of not only stacking faults but also dislocations and precipitates was measured. The obtained defect density values were plotted on the temperature-time graph for the previous heat treatment, and the isopycnal points were connected to draw isopycnal curves to obtain FIGS. 1 to 5. Figures 1 and 2 are standard graphs for a wafer with an O 2 concentration of 1.95 x 10 18 atoms/cm 3 , where Figure 1 shows the stacking fault density and Figure 2 shows the dislocation and precipitate densities. The density curve is shown. Moreover, the white circles in FIG. 1 indicate the heat treatment conditions, and the broken line curve indicates the time required to reach the saturated density. Figures 3 and 4 are standard graphs for a wafer with an O 2 concentration of 1.29 x 10 18 atoms/cm 3 , and Figure 3 shows the stacking fault density.
FIG. 4 shows isopycnal curves of dislocation and precipitate densities. Moreover, the white circles in FIG. 3 indicate the heat treatment conditions, and the broken line curve indicates the time required to reach the saturation density. Figure 5 shows isopycnal curves of stacking fault density for a wafer with an O 2 concentration of 1.65 x 10 18 atoms/cm 3 , white circles indicate the heat treatment conditions performed, and the curve represented by a broken line reaches the saturation density. Show time. Figure 5 also shows cooling curves A, B, and C when heat treatment is performed by adjusting the cooling conditions from high temperature. , 1280 for C
This is a cooling curve from ℃.

次に、第1図ないし第5図の標準グラフを用い
て処理対象ウエハーに所望の欠陥密度を導入する
方法を説明する。
Next, a method for introducing a desired defect density into a wafer to be processed will be explained using the standard graphs shown in FIGS. 1 to 5.

O2濃度が1.75×1018原子/cm3のウエハーにでき
るだけ短時間で109個/cm3の積層欠陥を導入する
ケースを考える。初めに熱処理温度を決定するた
めの標準グラフの選定を行つた。処理対象ウエハ
ーは結晶引上時の熱履歴がよく制御されており、
炭素濃度も赤外分光器での検出感度(約1.0×
1016原子/cm3)以下であれば、上記ウエハーの積
層欠陥の発生状況は、第1図および第3図のグラ
フから、内挿法によつてその傾向がおおよそ推定
される。具体的には、例えば1.95×1018原子/cm3
のO2濃度のグラフから等密度曲線の位置を時間
軸に平行に移動して推定する。そして、この推定
が正しいかどうか確認するために確認熱処理を行
う。第6図は、この確認熱処理で求められた処理
対象ウエハーの等密度曲線である。第6図の標準
グラフは10枚の試料によつて得られたものである
が、4枚程度に減らすことも可能である。これは
上記のように等密度曲線の傾向が予測されている
からである。第1図ないし第4図の標準グラフを
作成するには試料数が60枚程度必要であつたこと
に比べて、格段に少量の試料数で確実な予測が可
能となる。第6図のグラフから処理対象ウエハー
に、109個/cm3の積層欠陥をできるだけ短時間に
導入するには800℃、9時間の熱処理条件が予測
された。処理対象ウエハー1000枚に上記条件で熱
処理を行つたところ、0.5×109個/cm3〜5×109
個/cm3の積層欠陥が発生し、同一種ウエハー間で
それらの欠陥密度は正規分布で分布していた。
Consider a case where stacking faults of 10 9 atoms/cm 3 are introduced into a wafer with an O 2 concentration of 1.75×10 18 atoms/cm 3 in the shortest possible time. First, a standard graph for determining the heat treatment temperature was selected. The thermal history of the wafer to be processed during crystal pulling is well controlled.
The detection sensitivity of the infrared spectrometer for carbon concentration (approximately 1.0×
10 16 atoms/cm 3 ) or less, the tendency of stacking fault occurrence in the wafer can be roughly estimated by interpolation from the graphs in FIGS. 1 and 3. Specifically, for example, 1.95×10 18 atoms/cm 3
Estimate the position of the isopycnic curve from the O 2 concentration graph by moving parallel to the time axis. Then, a confirmatory heat treatment is performed to confirm whether this estimation is correct. FIG. 6 shows isodensity curves of the wafer to be processed obtained through this confirmation heat treatment. The standard graph in Figure 6 was obtained using 10 samples, but it is possible to reduce the number to about 4 samples. This is because the tendency of the isopycnic curve is predicted as described above. Compared to the approximately 60 samples needed to create the standard graphs shown in Figures 1 to 4, reliable predictions can be made with a much smaller number of samples. From the graph in FIG. 6, heat treatment conditions of 800° C. and 9 hours were predicted to introduce 10 9 stacking faults/cm 3 into the wafer to be processed in the shortest possible time. When 1000 wafers were heat-treated under the above conditions, the results were 0.5×10 9 wafers/cm 3 to 5×10 9
Stacking faults/cm 3 occurred, and the defect density was normally distributed among wafers of the same type.

実施例 2 つぎに、欠陥を導入するのに高温からの冷却過
程が利用できる場合の実施例を示す。O2濃度が
わかつていても、結晶引上時の熱履歴が明確でな
いもの、あるいは炭素濃度が前述の1×1016
子/cm2より高いものについては、欠陥の発生が速
く、定量的に予想しにくいので、650〜1050℃の
広い範囲にわたつて欠陥の発生挙動を調べる必要
がある。
Example 2 Next, an example will be shown in which a cooling process from a high temperature can be used to introduce defects. Even if the O 2 concentration is known, if the thermal history during crystal pulling is unclear or if the carbon concentration is higher than the aforementioned 1×10 16 atoms/cm 2 , defects will occur quickly and cannot be quantitatively determined. Since it is difficult to predict, it is necessary to investigate the defect generation behavior over a wide range of temperatures from 650 to 1050°C.

第5図は、このような欠陥の発生が速いウエハ
ーについて得られた等密度曲線で、実施例1の○ハ
のO2濃度が1.65×1018原子/cm3のウエハーについ
てのものである。このような欠陥の発生の速いウ
エハーにあつては、この等密度曲線から予測した
熱処理条件による熱処理をわざわざ行わなくて
も、加熱後の冷却速度を制御してその冷却曲線を
等密度曲線と接するか交差するように冷却してや
れば、その交差した等密度曲線から予想される欠
陥密度を導入することができる。(標準グラフの
別の応用例とも言える。) そして、冷却曲線A、B、Cはウエハーをそれ
ぞれ1100℃の炉中に5分間、15分間および1280℃
の炉中に15分間入れておいてから炉外に取り出し
たときの冷却速度を示すものである。冷却曲線A
に沿つて冷却されたウエハーは、その冷却曲線A
が107の等密度曲線と接しているので、1×107
個/cm2の積層欠陥が生成することが予測される。
同様に、冷却曲線Bに沿つて冷却されたウエハー
は、その冷却曲線Bが1017と108の等密度曲線の
中間付近を通過しているので5×107個/cm3の積
層欠陥が、また冷却曲線Cに沿つて冷却されたウ
エハーは、108の等密度曲線寄りを通過している
ので7〜8×107個/cm3の積層欠陥がそれぞれ生
成することが予測される。実際の欠陥密度の平均
値はAでは1.5×106個/cm3、Bでは9.4×106個/
cm3、Cでは8.5×107個/cm3となり、A、Bでは予
測値の1/6程度となつた。しかしながら、恒温熱
処理法により生成する欠陥密度から作製された標
準グラフ(第5図)が連続冷却により発生する欠
陥密度をも精度よく予測できることにもなり、標
準グラフの有用性がより一層高められる。
FIG. 5 is an isopycnal curve obtained for a wafer in which such defects occur quickly, and is for a wafer of Example 1 in which the O 2 concentration of O 2 is 1.65×10 18 atoms/cm 3 . For wafers where such defects occur quickly, it is possible to control the cooling rate after heating and make the cooling curve contact the isopycnal curve, without having to go to the trouble of performing heat treatment under the heat treatment conditions predicted from the isopycnal curve. If it is cooled so that the curves intersect, it is possible to introduce the defect density expected from the isopycnal curves that intersect. (This can also be said to be another application example of the standard graph.) The cooling curves A, B, and C show the wafers placed in a furnace at 1100°C for 5 minutes, 15 minutes, and 1280°C, respectively.
This shows the cooling rate when the product is taken out of the furnace after being placed in the furnace for 15 minutes. Cooling curve A
A wafer cooled along its cooling curve A
is in contact with the 10 7 isopycnal curve, so 1×10 7
It is predicted that stacking faults/cm 2 will be generated.
Similarly, a wafer cooled along cooling curve B has stacking faults of 5×10 7 /cm 3 because cooling curve B passes near the middle of the 10 17 and 10 8 isopycnic curves. Also, since the wafer cooled along the cooling curve C passes near the 10 8 isopycnal curve, it is predicted that 7 to 8×10 7 stacking faults/cm 3 will be generated. The average value of actual defect density is 1.5×10 6 defects/cm 3 for A and 9.4×10 6 defects/cm 3 for B.
For cm 3 and C, it was 8.5×10 7 pieces/cm 3 , and for A and B, it was about 1/6 of the predicted value. However, the standard graph (Figure 5) created from the defect density generated by constant temperature heat treatment can also accurately predict the defect density generated by continuous cooling, which further increases the usefulness of the standard graph.

以上説明したように、この発明のシリコンウエ
ハー中への結晶欠陥導入制御法は、熱履歴、O2
濃度等の履歴が明確なシリコン単結晶ウエハーに
種々の温度、時間の熱処理条件で第1段の熱処理
を施して欠陥核を導入したうえ、これをさらに第
2段の熱処理を行い先の欠陥核を計測可能なまで
成長せしめたのち、これを計測して上記第1段の
熱処理によつて導入された欠陥核密度を求め、こ
れを各履歴毎に第1段の熱処理時の温度−時間グ
ラフ上に等密度曲線として描いて標準グラフを作
成しておき、この標準グラフを用いて、新しく欠
陥を導入すべきウエハーについて所望の欠陥密度
を生成せしめるに必要な熱処理条件を予測するこ
とを特徴とするものである。
As explained above, the method of controlling the introduction of crystal defects into silicon wafers according to the present invention is based on thermal history, O 2
A silicon single crystal wafer with a clear history of concentration, etc. is subjected to a first heat treatment under heat treatment conditions of various temperatures and times to introduce defect nuclei, and then a second heat treatment is performed to introduce defect nuclei. After growing to a point where it can be measured, this is measured to determine the density of defect nuclei introduced by the first heat treatment, and this is plotted as a temperature-time graph during the first heat treatment for each history. A standard graph is created by drawing an isopycnic curve on the top of the wafer, and this standard graph is used to predict the heat treatment conditions necessary to generate a desired defect density for a wafer into which new defects are to be introduced. It is something to do.

よつて、本法によれば処理対象ウエハーに所望
の欠陥密度を効率よく、かつ確実に発生せしめう
る熱処理条件を容易かつ正確に予測することがで
き、ひいてはウエハーに所望の欠陥密度を短時間
に正確に生成せしめることができる。したがつ
て、従来法に比べて安価に欠陥を導入することが
でき、また欠陥密度のバラツキの少ないウエハー
を製造できる。
Therefore, according to this method, it is possible to easily and accurately predict the heat treatment conditions that can efficiently and reliably generate the desired defect density on the wafer to be processed, and in turn, the desired defect density can be generated on the wafer in a short time. It can be generated accurately. Therefore, defects can be introduced at a lower cost than in conventional methods, and wafers with less variation in defect density can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第6図はいずれもこの発明の方法
の標準グラフである。
1 through 6 are standard graphs of the method of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 熱履歴、初期固溶酸素濃度などの履歴が明確
なシリコン単結晶ウエハーに、不活性ガス雰囲気
中650〜1050℃の温度範囲で2分〜300時間の温度
範囲で第1段の熱処理を施して、欠陥核を導入
し、ついで1000〜1200℃の温度で10分〜10時間の
第2段の熱処理を施して前記欠陥核を観測可能な
程度にまで成長させて欠陥核の密度を計測し、前
記第1段の熱処理における温度対時間曲線を履歴
毎に欠陥核密度の等密度曲線として図示し、かく
して得られた等密度曲線を標準グラフとして用い
て、シリコン単結晶ウエハーに所望の欠陥密度を
成長せしめうる熱処理条件を予測することを特徴
とするシリコンウエハー中への結晶欠陥導入制御
法。
1. A silicon single crystal wafer with a clear history of thermal history, initial solid solution oxygen concentration, etc. is subjected to the first heat treatment in an inert gas atmosphere in a temperature range of 650 to 1050°C for 2 minutes to 300 hours. Then, defect nuclei were introduced, and then a second stage heat treatment was performed at a temperature of 1000 to 1200°C for 10 minutes to 10 hours to grow the defect nuclei to an observable level, and the density of the defect nuclei was measured. , the temperature vs. time curves in the first stage heat treatment are illustrated as isopycnal curves of defect nucleus density for each history, and the isopycnal curves obtained in this way are used as standard graphs to determine the desired defect density in the silicon single crystal wafer. A method for controlling the introduction of crystal defects into silicon wafers, which is characterized by predicting heat treatment conditions that will allow the growth of crystal defects.
JP17678183A 1983-09-24 1983-09-24 Controlling method of introducing crystal defect into silicon wafer Granted JPS6066827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17678183A JPS6066827A (en) 1983-09-24 1983-09-24 Controlling method of introducing crystal defect into silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17678183A JPS6066827A (en) 1983-09-24 1983-09-24 Controlling method of introducing crystal defect into silicon wafer

Publications (2)

Publication Number Publication Date
JPS6066827A JPS6066827A (en) 1985-04-17
JPH0469422B2 true JPH0469422B2 (en) 1992-11-06

Family

ID=16019724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17678183A Granted JPS6066827A (en) 1983-09-24 1983-09-24 Controlling method of introducing crystal defect into silicon wafer

Country Status (1)

Country Link
JP (1) JPS6066827A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293621A (en) * 1986-06-12 1987-12-21 Nec Corp Semiconductor integrated circuit element
JPH0750713B2 (en) * 1990-09-21 1995-05-31 コマツ電子金属株式会社 Heat treatment method for semiconductor wafers
JP2006032799A (en) * 2004-07-20 2006-02-02 Shin Etsu Handotai Co Ltd Silicon epitaxial wafer and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538098A (en) * 1978-09-08 1980-03-17 Ibm Method of increasing gettering effect existing in semiconductor substrate bulk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538098A (en) * 1978-09-08 1980-03-17 Ibm Method of increasing gettering effect existing in semiconductor substrate bulk

Also Published As

Publication number Publication date
JPS6066827A (en) 1985-04-17

Similar Documents

Publication Publication Date Title
JP5228031B2 (en) Silicon wafer manufacturing method
US5505157A (en) Low hydrogen-content silicon crystal with few micro-defects caused from annealing, and its manufacturing methods
US20080176415A1 (en) Wafer support pin for preventing slip dislocation during annealing of water and wafer annealing method using the same
US9995693B2 (en) Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method
Kissinger et al. A Method for Studying the Grown‐In Defect Density Spectra in Czochralski Silicon Wafers
EP0550750B1 (en) Semiconductor wafer heat treatment method
KR101895817B1 (en) Silicon wafer and method for manufacturing same
TWI631242B (en) Methods to evaluate and fabricate silicon wafer
JP2001081000A (en) Method of evaluating crystal defect in silicon single crystal
US9748112B2 (en) Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method
JP2936916B2 (en) Quality evaluation method of silicon single crystal
JPH0469422B2 (en)
JPH1012689A (en) Method for inspecting semiconductor substrate and semiconductor substrate for monitoring used therefor
JP2000269288A (en) Crystal defect detecting method for silicon wafer, crystal defect evaluating method, and oxide film breakdown voltage characteristics evaluating method
JP2903520B2 (en) Evaluation method of silicon single crystal
JP2002334886A (en) Method for evaluating oxygen deposit density in silicon wafer, and the silicon wafer manufactured based on the evaluation method
JP6711320B2 (en) Silicon wafer
KR0127999B1 (en) Semiconductor device having substrate made from silicone crystal and its manufacturing method
JPH0666695A (en) Preparation of sample
KR20050059910A (en) Method of detecting defects in the silicon wafer
TW202417696A (en) Method for forming substrate
JP2023169790A (en) Silicon wafer heat treatment method
JPH0527974B2 (en)
JP2021098623A (en) Method for evaluating oxide film voltage resistance of single crystal silicon wafer
JPH0463839B2 (en)