JPH0468646A - Address conversion method - Google Patents

Abstract

PURPOSE:To eliminate the need for replacement even when a converted address is changed and to attain address conversion with high reliability as a ROM or the like by employing a DPRAM. CONSTITUTION:An address to be converted is written in a DPRAM 2 in the initial state and the sum of written addresses is stored in a memory 4. A sequential address is inputted to the DPRAM 2 at a prescribed period from a sequential address output section 1 in the steady-state and the converted address is read from the DPRAM 2 and outputted. On the other hand, a sequential address is inputted from a counter 14 to other address terminal and the sum of addresses outputted from the other data terminal for one period is obtained by an adder 5. Then the sum is compared with the sum stored in the memory 4 previously. When they are coincident, the steady-state mode is continued, and when dissident, the write mode is selected similarly in the initial state, a processor 3 sends an address sequentially to the address terminal of the DPRAM 2 and a prescribed address corresponding to each of the sequential address is entered to the data terminal to rewrite the DPRAM.

Description

[Detailed Description of the Invention] [Summary] Regarding an address conversion method, the present invention aims to provide an address conversion method that does not require replacement even if the address to be converted changes and has high reliability similar to that of a ROM, and uses a sequential address output unit. , when converting each sequential address that is repeatedly output at a fixed period into a predetermined address, a dual port RAM (hereinafter referred to as DPRAM) is used, and in the initial state, it is in the write state, and the processor inputs the address terminal of the DPRAM. The addresses in the above order are sent, and the predetermined address values are input into the data terminals in correspondence with each of the addresses in the order and written to the iDPRAM, and the total value of the input address values is stored in the memory. In the steady state, the read state is set, and the DPR
The sequential address output to the address terminal of the AM is switched from the processor to the sequential address output section, sequentially inputting the sequential addresses at a fixed period, giving the predetermined address value to be read to the target section, and inputting the sequential address to the counter. sends the address in the above order from the other address terminal, inputs the predetermined address value outputted from the other data terminal to the adder to add the value for one cycle, and sends the addition result to the processor. , and the total address value stored in the memory. If they match, the steady state continues; if they do not match,
As in the initial state, the write state is set, and the processor sends sequential addresses to the address terminals of the D P RAM, and the above-mentioned predetermined address values corresponding to each of the sequential addresses are input to the data terminals. Configure to write.

[Industrial Application Field] The present invention relates to an improvement in an address conversion method used in a lamp lighting device that lights a lamp in a lamp lighting section using a signal from an exchange.

[Conventional technology]

FIG. 3 is a block diagram of a conventional lamp lighting device.

In the lamp lighting section 8 of FIG. 3, seven lamp rows of lamps 1-1 to 1-7 are installed at the address 4000.
Set the 7 lamp rows of lamps 2-1 to 2-7 to address 50.
Attach to position 00, 7 lamps 3-1 to 3-7 Q
A lamp row is installed at address 7000,
Since the mounting position changes depending on various circumstances, the address value indicating the mounting position changes.

The exchange cyclically sends a lighting signal to light each lamp of the lamp lighting section 8, as shown in FIG. 3(A), in order to display the received telephone number, etc.
Turn it on.

At this time, the DMA (direct memory access) transfer unit 1 is used to input the address value of the lamp array to the lamp lighting unit 8.
However, since the addresses output from the DMA transfer unit 1a are in the order, for example, 60006001.6002, this address is converted to 4000.5000.70 of the address of the lamp array by the address conversion means.
Must be converted to 00.

To perform this conversion, ROM10 is used in FIG.
The address value 4000.50007000 is written in the addresses 6000, 6001, 6002 of OMl0, and when the address 60006001.6002 is input, 4000.5000.7000 is output from the output and given to the lamp lighting section 8. There is.

The lighting signal sent from the exchange shown in FIG. 3(A) corresponds to each of the seven lamps after the control bit, and has, for example, 7 focus signals such as lighting at 1 and clearing at 0, and 1. Since the control focus at the beginning of a cycle indicates the beginning of one cycle, O2 and others are set to I.

The lighting signal from the exchange is a series lighting signal that flashes 7 lamps at address 400000, then 7 lamps at address 5000, and then 7 lamps at address 7000. .

This serial signal is input to the control bin) 0 detection unit 7, and the beginning of one cycle is found, and when it is found, DMAIIJal1
Start part 1a and enter address 6000.6001.60
02 is outputted and inputted to the S/P converter 6 to become an 8-bit parallel signal, which is sent to the lamp lighting section 8.

Then, in the lamp lighting section 8, the address 4000.50
00.7000 lamps 1-1 to 1-72-1 to 2-7
．． 3-1 to 3-7 are lit according to the contents of the lighting signal.

[Problem to be solved by the invention]

However, in the address translation method using ROM,
If the address for attaching the lamp row changes, ROM10 must be recreated, which is time-consuming and the R used until now.
There is a problem in that OM10 becomes unusable, which increases costs.

The present invention aims to provide an address translation method that does not require replacement even if the address to be translated changes and is as reliable as a ROM.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, when converting each sequential address that is repeatedly output from the sequential address output unit 1 into a predetermined address, a DPRAM 2 is used. The DPR
Send the addresses in the above order to the address terminal of AM2, input the above predetermined address values corresponding to each of the addresses in the order to the data terminal, write them into the DPRAM2, and write the total of the input address values. The value is stored in the memory 4, and in a steady state, it is in a read state, and the sequential address output to the address terminal of the DPRAM 2 is sent to the processor 3.
Switches to the sequential address output section 1, inputs sequential addresses at a fixed period, gives the predetermined address value to be read out to the target section, and inputs the above sequential address to the other address terminal from the counter 14. Then, the predetermined address value outputted from the other data terminal is inputted to the adder 5 to add the value for one cycle, and the addition result is sent to the processor 3, and the address stored in the memory 4 is added. Compare with the sum of values.

If the comparison results match, the steady state continues, and if they do not match, the writing state is set as in the initial state, and the processor 3 sends sequential addresses to the address terminals of the DPRAM 2, and the data terminals receive the corresponding addresses. The predetermined address values corresponding to each of the sequential addresses are input and written.

[Function] According to the present invention, in the initial state, the address value to be converted is written in the DPRAM 2, and the total value of the written address values is stored in the memory 4, and in the steady state, the address value is output from the sequential address output unit 1. Addresses in sequence are repeatedly input to the DPRAM 2 at a constant cycle, and the address value to be converted is read out from the DPRAM 2 and output.

On the other hand, the addresses in the above order are input from the counter 14 to the other address terminal, and the adder 5 calculates the total value for one cycle of the address values output from the other data terminal, and first stores it in the memory 4. If they match, the steady state continues; if they do not match, the program enters the write state as in the initial state, and the processor 3 sends a sequential order to the address terminals of the dual port RAM 2. The address is sent, and the predetermined address value corresponding to each address in the order is input to the data terminal and rewritten.

In this way, if the DPRAM2 is used for address conversion, if the address value to be converted changes, the processor 3
Since the address value can be rewritten even if the address value to be converted changes, there is no need to replace it, and the other address terminal and data terminal can be used to check whether the total of the converted address values matches the original total value. Reliability is RO because I check it and rewrite it if it doesn't match.
High as M.

Of course, when the converted address changes, there is a normal RAM that can be rewritten to a new address by the processor without replacing it, but normal RAM does not have the other address terminal and data terminal and cannot be checked when in use. Since there is no memory, it is less reliable than ROM.

〔Example〕

FIG. 2 is a block diagram of a lamp lighting device according to an embodiment of the present invention.

The difference in FIG. 2 from the conventional example shown in FIG. 3 is the use of the DPRAM 2 for address translation, so the explanation will focus on this difference.

In the initial state, the switch SW is controlled by the processor 3.
is set to the dotted line side and in the write state, and a signal indicating the write state is input to the decoder 11, and the 3-state buffer 1
2 through, 3 state buffer 13 open,
The 3-state buffer 15 is prohibited from outputting, and the processor 3
For example, as shown in Figure 2 (B), the address is 6.
000゜6001.6002 is sent to the address terminal of DPRAM2, and the corresponding address value 4 is converted.
000.5000.7-000 3-state Banhua 1
2 to the data terminal and stored, and the total of the address values written at this time is stored in the memory 4.

In the steady state, the processor 3 is in a read state, the 3-state buffer 12 is opened via the decoder 11, the 3-state buffers 13 and 15 are through, and the switch SW is switched to the solid line side.

Then, in synchronization with the lighting signal input shown in FIG. 2(A), as in the case of FIG.
Address 6000.6001.60 to address terminal 2
Enter 02. Then 4000.50 from the data terminal
00.7000 is read out, passes through the 3-state buffer 13, and is input to the lamp lighting section 8 as an address.

On the other hand, at approximately the same speed as the DMA transfer unit 1a, the counter 14
6000.6001.600 to the other address terminal.
2 is input and 400 is read from the other data terminal.
The adder 5 adds up the address values of 0.5000.7000 and sends the total value to the processor 3 through the 3-state buffer 15.

In the processor 3, the value is compared with the value stored in the memory 4, and if they match, the stationary steady state is continued, and if they do not match, the switch SW is set to the dotted line side and the write state is entered.
The 3-state buffer 12 is passed through the decoder 1, the 3-state buffer 13 is prohibited from outputting, and the 3-state buffer 15 is open, and as in the initial state, the DPRA
6000.6001.6002 is sent to the address terminal of M2, and 4000.5000.7000 is sent to the data terminal to write the data and establish a steady state.

If the DPRAM 2 is used to convert the address in this way, even if the address to be converted changes, it can be rewritten from the processor 3 without replacing it, which saves time and money.

Furthermore, even if there is an abnormality in DPRAM 2 during use, it is discovered and rewritten immediately, which increases reliability.

〔Effect of the invention〕

As explained in detail above, according to the present invention, by using DPRAM, even if the address to be converted changes, it can be rewritten without replacing it, and even if an abnormality occurs during use, it is discovered and rewritten immediately. Therefore, it is possible to obtain an address translation method that requires less time and effort for address translation, costs less, and has high reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a lamp lighting device according to an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional lamp lighting device. In the figure, l is a sequential address output section, 1-1 to 1-7.2-1 to 2-7.3-1 to 3-7 are lamps, la is a DMA transfer section, 2 is a dual baud) RAM, 3 is a processor, 4 is a memory, 5 is an adder, 6 is an S/P conversion unit, 7 is a control bit 0 detection unit, 8 is a lamp lighting unit, 10 is a ROM, 11 is a decoder, 12.1.3.15 is a 3-state buffer, 14 indicates a counter.

Claims (1)

[Claims] When converting each sequential address that is repeatedly output at a fixed period from the sequential address output unit (1) into a predetermined address, a dual port RAM (2) is used, and in the initial state, a write state, the processor (3) sends the addresses in the above order to the address terminals of the dual port RAM (2), and inputs the predetermined address values corresponding to each of the addresses in the order to the data terminals. The dual port R
At the same time as writing to AM (2), the total value of the input address values is stored in the memory (4), and in the steady state, it is in the read state and the dual port R
The sequential address output to the address terminal of AM (2) is
Switching from the processor (3) to the sequential address output unit (1) and sequentially inputting sequential addresses at a constant cycle;
The predetermined address value to be read is given to the target section, and the counter (14) sends the address in the above order from the other address terminal, and the predetermined address value output from the other data terminal is sent to the adder (14). 5) to add the values for one cycle, and the addition result is sent to the processor (3).
and compares it with the total value of the address values stored in the memory (4). If they match, the steady state continues; if they do not match,
As in the initial state, the write state is set and the processor (3
) to the address terminals of the dual port RAM (2), and inputting and writing the above-mentioned predetermined address values corresponding to each of the addresses in the order into the data terminals. .