JPH0468559A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0468559A JPH0468559A JP18203290A JP18203290A JPH0468559A JP H0468559 A JPH0468559 A JP H0468559A JP 18203290 A JP18203290 A JP 18203290A JP 18203290 A JP18203290 A JP 18203290A JP H0468559 A JPH0468559 A JP H0468559A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- sealing resin
- mount
- lead
- plating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000011347 resin Substances 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 238000007789 sealing Methods 0.000 claims abstract description 23
- 238000007747 plating Methods 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 7
- 239000007769 metal material Substances 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 230000035939 shock Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に樹脂封止型の半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device.
従来のこの種の半導体装置には、ＤＩＰ、ＺＩＰ、ＳＯ
Ｊ、ＰＬＣＣ等のパッケージが適用され、表面実装対応
としてはＳＯＪか主流となっており、表面実装の場合、
リフロー半田付けにより実装される。（日経マイクロデ
バイス１９８８年５月号３６頁「大詰めを迎える４ＭＤ
ＲＡＭパッケージの開発ｊ参照）
これら半導体装置のリードフレームは、加工性の良さ等
のためその材料は銅を用いる場合が多く、半導体チップ
は年々大型化の方向にある。Conventional semiconductor devices of this type include DIP, ZIP, and SO.
Packages such as J, PLCC, etc. are applied, and SOJ is the mainstream for surface mounting.
Mounted by reflow soldering. (Nikkei Microdevice May 1988 issue, p. 36 “4MD reaching its final stage”
(Refer to RAM Package Development J) The lead frames of these semiconductor devices are often made of copper because of its good workability, and semiconductor chips are becoming larger year by year.
上述した従来の半導体装置は、リードフレームの材料と
しては銅が用いられ、半導体チップも年々大型化してい
るので、表面実装の際等の熱的衝撃、温度変化により、
リードフレームと封止樹脂部、半導体チップとの熱膨張
係数の違いのために、封止樹脂部の端部のリードフレー
ム付近に弓張り応力が集中してクラックが発生するとい
う欠点がある。In the conventional semiconductor devices mentioned above, copper is used as the lead frame material, and semiconductor chips are becoming larger year by year, so thermal shock and temperature changes during surface mounting, etc.
Due to the difference in thermal expansion coefficient between the lead frame, the sealing resin part, and the semiconductor chip, there is a drawback that bowing stress is concentrated near the lead frame at the end of the sealing resin part, causing cracks.
本発明の目的は、熱的衝撃や温度変化に対してもクラッ
クの発生を防止することができる半導体装置を提供する
ことにある。An object of the present invention is to provide a semiconductor device that can prevent cracks from occurring even when subjected to thermal shock or temperature changes.
本発明の半導体装置は、リード部及びマウント部を備え
たリードフレームと、このリードフレームのマウント部
にマウント材により固着搭載された半導体チップと、こ
の半導体チップ、並びに前記リードフレームのリード部
の所定の部分及びマウント部を封入する封止樹脂部とを
有する半導体装置において、前記リードフレームの表面
の所定の部分に、引張り降伏点が前記封止樹脂部より小
さい金属材料で形成されためっき層を設けて構成される
。A semiconductor device of the present invention includes a lead frame including a lead portion and a mount portion, a semiconductor chip fixedly mounted on the mount portion of the lead frame with a mount material, the semiconductor chip, and a predetermined portion of the lead portion of the lead frame. In the semiconductor device, a plating layer formed of a metal material having a tensile yield point smaller than that of the sealing resin portion is provided on a predetermined portion of the surface of the lead frame. provided and configured.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.
この実施例は、リード部１１及びマウント部１２を備え
、銅で形成されたリードフレーム１と、このリードフレ
ーム１の上表面全体に、引張り降伏点が封止樹脂部５よ
り小さい金属材料の金をめっきして形成されためつき層
２と、リードフレーム１のマウント部１２上にめっき層
２を介して銀ペースト等のマウント材３により固着搭載
された半導体チップ４と、この半導体チップ４、並びに
リードフレーム１のリード部１１の所定の部分及びマウ
ント部１２を内部に封入するプラスチック等の封止樹脂
部５とを有する構成となっている。This embodiment includes a lead frame 1 that includes a lead part 11 and a mount part 12 and is made of copper. a plating layer 2 formed by plating, a semiconductor chip 4 fixedly mounted on the mount portion 12 of the lead frame 1 via the plating layer 2 with a mount material 3 such as silver paste, and the semiconductor chip 4; The structure includes a predetermined portion of the lead portion 11 of the lead frame 1 and a sealing resin portion 5 made of plastic or the like that encapsulates the mount portion 12 therein.
この実施例のめっき層２には金が使用され、その引張り
降伏点は約” 、”ｋ ｇ／ｍｍ２であり、これに対し
封止樹脂部５の引張り降伏点は約８．０ｋｇ／ｍｍ２と
なっている。Gold is used for the plating layer 2 in this embodiment, and its tensile yield point is approximately 1,000 kg/mm2, whereas the tensile yield point of the sealing resin portion 5 is approximately 8.0 kg/mm2. It has become.
熱的衝撃や温度変化による引張り応力は、主にリードフ
レーム１と封止樹脂部５との熱膨張係数の違いにより発
生する。Tensile stress due to thermal shock or temperature change is mainly caused by the difference in thermal expansion coefficient between the lead frame 1 and the sealing resin portion 5.
従って引張り応力が発生するリードフレーム１と封止樹
脂部５との間に、塑性材料の金によるめっき層２を設け
ることにより、上記のようにめっき層２の引張り降伏点
が封止樹脂部５より小さいので、めっき層２に塑性変形
が起こり引張り応力が低減し、封止樹脂部５のクラック
の発生を防止することができる。Therefore, by providing the plating layer 2 made of gold, which is a plastic material, between the lead frame 1 and the sealing resin part 5 where tensile stress is generated, the tensile yield point of the plating layer 2 can be lowered to the sealing resin part 5 as described above. Since it is smaller, plastic deformation occurs in the plating layer 2 and the tensile stress is reduced, making it possible to prevent the occurrence of cracks in the sealing resin portion 5.
従来の半導体装置のリードフレームは銅で形成され、こ
の実施例のようにめっき層２がなく、かつ銅の引張り降
伏点は３５ｋｇ／ｍｍ２と高いので、封止樹脂部にクラ
ックが発生していた。The lead frame of a conventional semiconductor device is made of copper, and there is no plating layer 2 as in this example, and the tensile yield point of copper is as high as 35 kg/mm2, so cracks have occurred in the sealing resin part. .
実際に従来例と本発明との応力解析を行った数値例を第
１表に示す。この第１表より、加わる最大応力値は、従
来例より本発明の方が大幅に低減しており、本発明では
封止樹脂部５の引張り降伏点以下となっているのに対し
、従来例ではそれ以上となっていることが分かる。Table 1 shows numerical examples in which stress analysis was actually performed for the conventional example and the present invention. From Table 1, the maximum applied stress value is significantly lower in the present invention than in the conventional example, and in the present invention it is below the tensile yield point of the sealing resin part 5, whereas in the conventional example It turns out that it is more than that.
第１表 第２図は本発明の第２の実施例を示す断面図である。Table 1 FIG. 2 is a sectional view showing a second embodiment of the invention.
この実施例は、引張り応力が第２図の（Ａ）部に示され
た封止樹脂部５の端部（封止樹脂部５の内側と外表面と
の境界）とリードフレーム１．めっき層２Ａとの接合部
に集中するので、この部分にめっき層２Ａを設けたもの
で、めっき層２Ａを形成する金の量を削減しコストを低
減することができる利点がある。In this embodiment, the tensile stress is applied to the end portion of the sealing resin portion 5 (the boundary between the inside and outer surface of the sealing resin portion 5) shown in part (A) of FIG. Since the gold is concentrated at the joint with the plating layer 2A, providing the plating layer 2A in this portion has the advantage that the amount of gold forming the plating layer 2A can be reduced and the cost can be reduced.
以上説明したように本発明は、リードフレームの表面、
特に引張り応力が集中する部分を主体に、引張り降伏点
が封止樹脂部より小さい塑性金属材料のめっき層を設け
た構成とすることにより、熱的衝撃や温度変化によりこ
のめっき層に塑性変形が起り引張り応力が低下するので
、封止樹脂部等のクラックの発生を防止することができ
る効果がある。As explained above, the present invention provides the surface of the lead frame,
In particular, by providing a plating layer of a plastic metal material whose tensile yield point is smaller than that of the sealing resin part mainly in areas where tensile stress is concentrated, this plating layer will not undergo plastic deformation due to thermal shock or temperature changes. Since the resulting tensile stress is reduced, it is possible to prevent the occurrence of cracks in the sealing resin portion, etc.
【図面の簡単な説明】
第１図及び第２図はそれぞれ本発明の第１及び第２の実
施例を示す断面図である。
１・・・リードフレーム、２，２Ａ・・・めっき層、３
・・・マウント材、４・・・半導体チップ、５・・・封
止樹脂部、１１・・・リード部、１２・・・マウント部
。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are sectional views showing first and second embodiments of the present invention, respectively. 1... Lead frame, 2, 2A... Plating layer, 3
... Mount material, 4... Semiconductor chip, 5... Sealing resin part, 11... Lead part, 12... Mount part.
Claims (1)
、このリードフレームのマウント部にマウント材により
固着搭載された半導体チップと、この半導体チップ、並
びに前記リードフレームのリード部の所定の部分及びマ
ウント部を封入する封止樹脂部とを有する半導体装置に
おいて、前記リードフレームの表面の所定の部分に、引
張り降伏点が前記封止樹脂部より小さい金属材料で形成
されためっき層を設けたことを特徴とする半導体装置。 ２、封止樹脂部の内部と外表面との境界線部分と接合す
るリードフレームの表面の所定の範囲にめっき層を設け
た請求項１記載の半導体装置。[Claims] 1. A lead frame including a lead part and a mount part, a semiconductor chip fixedly mounted on the mount part of the lead frame with a mount material, the semiconductor chip, and the lead part of the lead frame. In a semiconductor device having a predetermined portion and a sealing resin portion that encapsulates a mount portion, a plating layer formed of a metal material having a tensile yield point smaller than that of the sealing resin portion is formed on a predetermined portion of the surface of the lead frame. A semiconductor device characterized by being provided with. 2. The semiconductor device according to claim 1, wherein a plating layer is provided in a predetermined range of the surface of the lead frame that is bonded to the boundary line between the inside and the outer surface of the sealing resin part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18203290A JPH0468559A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18203290A JPH0468559A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0468559A true JPH0468559A (en) | 1992-03-04 |
Family
ID=16111145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18203290A Pending JPH0468559A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0468559A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5463248A (en) * | 1993-05-18 | 1995-10-31 | Kabushiki Kaisha Toshiba | Semiconductor package using an aluminum nitride substrate |
-
1990
- 1990-07-10 JP JP18203290A patent/JPH0468559A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5463248A (en) * | 1993-05-18 | 1995-10-31 | Kabushiki Kaisha Toshiba | Semiconductor package using an aluminum nitride substrate |
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