JPH0467772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a reduction projection alignment method and apparatus for aligning circuit patterns when they are exposed onto a wafer through a reduction projection lens.

[Background of the invention]

As the miniaturization of semiconductor integrated circuits progresses, higher and higher alignment precision is required between a reticle and a wafer during exposure using a reduction projection exposure apparatus. For this reason, TTL technology is developed using a reduction projection lens that allows alignment for each chip and accommodates chip alignment errors within the wafer.
Alignment methods are becoming mainstream in the manufacturing of highly integrated circuits in the future.

FIG. 13 shows an example of the TTL alignment method. The circuit pattern on the reticle 1 is exposed onto the wafer 3 one to several chips at a time through a reduction projection lens 2. 4 is the wafer stage,
16 is a chip. Here, first, the positions of the reticle initial setting patterns 15, 15' are detected by the reticle alignment optical systems 5, 5', and the reticle 1 is set at the initial position. Next, the alignment patterns 14 and 14' on the wafer are imaged onto the alignment patterns 13 and 13' on the reticle 1 through the reduction projection lens 2, and both patterns are detected by the wafer alignment detection optical system. The system includes mirrors 6, 6', relay lenses 7, 7', magnifying lenses 8, 8', movable slits 9, 9', photomultiplier tubes 10, 10', and alignment illumination light having the same wavelength as the exposure light. It consists of emitting optical fibers 11, 11'. If the detected wafer alignment patterns 14, 14' do not match the positions of the reticle alignment patterns 13, 13', move the wafer stage 4 on which the wafer 3 is mounted in the , 14', 13, and 13' are aligned. When the alignment is completed in this way, the exposure system 12 illuminates with exposure light.
A related alignment method of this type is JP-A-55-41739.

In this TTL alignment method, a problem that has been pointed out in the past but still remains unsolved is a decrease in alignment accuracy due to uneven coating of photoresist on the wafer. This problem has become extremely serious in recent years as semiconductor circuits become more highly integrated.

As shown in FIG. 14, the photoresist is coated on the entire surface of the wafer by rotating the wafer 3 at high speed (in the R direction) using a spin coater (rotary coating machine), and applying the centrifugal force to the photoresist.
Applied to a thickness of ~2 μm (for single layer resist). Therefore, the direction in which the photoresist flows is the direction in which it spreads radially from the center of the wafer, as shown by arrows A, B, C, and D. FIG. 15 is an enlarged view of the x-direction alignment pattern 19 of the chip 17. As shown in FIG. 15, the alignment pattern usually consists of a concave or convex step pattern, and the thickness of the photoresist 23 applied thereon draws a gentle curve depending on the shape of the step.
Note that here, 21 is a Si substrate, and 22 is a SiO ₂ layer.
Now, as shown in FIG. 14, the x-direction alignment pattern 19 of the chip 17 is parallel to the resist flow direction B, but the x-direction alignment pattern 20 of the chip 18 is perpendicular to the resist flow direction C. . As a result, as shown in FIG. 15a, the photoresist film thickness distribution in the pattern position detection direction near the alignment pattern 19 becomes symmetrical, but on the other hand, as shown in FIG. , the flow of photoresist is disturbed at the step part of the pattern, resulting in left-right asymmetry. In addition, in figures a and b, B and C indicate the direction in which the resist flows. Alignment patterns 19 and 20 are pattern illumination light 2
4a and 25a, the reflected light from the pattern is approximately equal to the reflected light 24b, 25b from the photoresist surface and the Si substrate 21 or
It is obtained as interference light with the reflected lights 24c and 25c from the surface of the SiO ₂ layer 22. Therefore, as shown in FIG. 17, the intensity of the interference light changes periodically depending on the thickness of the photoresist 23. As a result, the reflected light intensity distribution from the alignment pattern 19 is
As shown in Figure 6a, it is symmetrical, but the intensity distribution of the reflected light from the alignment pattern 20 is as shown in Figure 6b.
As shown in the figure, the left and right sides are asymmetrical. Therefore, in the conventional alignment method that utilizes the symmetry of the detection signal waveform and sets the center of symmetry of the waveform as the center position of the alignment pattern, as shown in Figure b, xd is This was regarded as the pattern center position, resulting in an error and a decrease in alignment accuracy. FIG. 18 shows the magnitude and direction of alignment error in each chip on the wafer 30 with arrows. For example, the alignment error 32 in the chip 31 is
As shown in Figure 19, 32
The x and y directions are represented by 32y arrows.

[Purpose of the invention]

In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a reduction projection alignment method that eliminates the deterioration in alignment accuracy caused by uneven resist coating and enables stable and highly accurate alignment between a reticle and a wafer. The goal is to provide equipment.

[Summary of the invention]

That is, in order to achieve the above object, the present invention has the following objectives: Under monochromatic illumination, multiple interference occurs within the resist, while under white illumination, multiple interference within the photoresist is small, and as a result, the detection signal caused by uneven coating of the photoresist is reduced. Focusing on the fact that an alignment pattern detection signal with no asymmetry, always high contrast, and good waveform symmetry is obtained, and the position detection accuracy is extremely high, we The alignment pattern on the wafer is illuminated with white illumination light and monochromatic illumination light of the same wavelength as the alignment illumination light, without going through a reduction projection lens, and in a separate optical system different from the alignment optical system. The position of the alignment pattern is detected under light and the difference between the two position detection signals is determined. Based on the pattern position detection error data, the alignment amount during alignment is corrected to correct alignment caused by uneven resist coating. This method is characterized by eliminating deterioration in accuracy.

Furthermore, in the alignment method according to the present invention, pattern position detection error data is first calculated for alignment patterns in the vicinity of at least five chips, including the central chip on the wafer.
For other chips, the relationship between the position coordinates of the alignment pattern and the amount of position detection error that occurs is calculated from the position detection error data and the position coordinates of the corresponding alignment pattern. A relationship is derived, and an alignment pattern position detection error amount at an arbitrary position is determined based on the relationship.

Further, in the present invention, it is assumed that the white illumination light exhibits a flat spectral distribution that does not include a bright line spectrum.

[Embodiments of the invention]

Embodiments of the present invention and its principles will be described below with reference to FIGS. 1 to 12.

In the present invention, before alignment of the reticle and the wafer, detection signals with extremely high contrast can be obtained for all or several chips on the wafer using white illumination light with high position detection accuracy and having the same wavelength as the alignment illumination light. A major feature is that the alignment pattern position is detected using monochromatic illumination light, and the alignment amount is corrected based on the difference between the two position detection data.

FIG. 1 is a diagram showing a first embodiment of the present invention, in which a pattern detection optical system 51 (hereinafter referred to as This is a view from above of an aligner having a stage 40 and a TTL alignment/exposure stage 41 which are equipped with a sub-pattern detection system (referred to as a sub-pattern detection system). The wafer supplied from the supply side track 42 first determines its approximate orientation on the pre-alignment stage 43. The pre-aligned wafer is handled by a suction or mechanical handling mechanism 4.
4, it is set on the sub-pattern detection stage 40 as shown in 45. 49 is chip 5
0 and 50' are x- and y-direction position detection alignment patterns, and 52 is a detection field of view of the sub-pattern detection system 51.

Hereinafter, this sub-pattern detection system 51 will be explained in detail based on FIG. This detection system is
It consists of an XY stage 40, a white light/monochromatic light alignment illumination system, and an x/y direction alignment pattern detection optical system. First, white light from an ultra-high pressure mercury lamp is illuminated by the white light illumination fiber 70a through the shutter 71a. At this time, the shutter 71b is closed and the illuminated white light is transmitted through the half mirror 72, the condensing lens 73, and the half mirror 6.
3. Illuminate the x-direction alignment pattern 50 on the wafer 45 through the relay lens 62, mirror 61, and magnifying lens 60. It is now assumed that uneven coating of the photoresist has occurred in the vicinity of the pattern 50. The reflected light from the pattern passes through the magnifying lens 60, mirror 61, relay lens 62,
After passing through the half mirror 63, the image is optically compressed by a magnifying lens 64 and a cylindrical lens 67 in a direction (y direction) orthogonal to the pattern position detection direction, and expanded onto a one-dimensional solid-state image sensor 68 for position detection in the x direction. imaged. In addition, at this time, the reflected light from the pattern passes through the half mirror 65 to y
An image is also formed on the one-dimensional solid-state image sensor 68' for detecting the directional position, but this does not pose any particular problem if only the x-direction pattern detection signal is stored in a memory (not shown).
Further, as the magnifying lenses 60 and 64, three-color corrected microscope objective lenses are used. Next, shutter 71
a and open the shutter 71b. Monochromatic light (g-line; in this embodiment, the g-line of an ultra-high pressure mercury lamp is used for alignment illumination) is illuminated by the monochromatic illumination fiber 70b. The illuminated monochromatic light passes through an optical system with white light,
The x-direction alignment pattern 50 is illuminated. The reflected light from the pattern is enlarged and imaged onto the one-dimensional solid-state sensor 68 through a similar optical system.
Note that the same applies to the detection of the y-direction alignment pattern. Figure 3a shows x in white illumination.
This is a detected image 75 of the direction alignment pattern 50. FIG. 5B shows a detection signal waveform of the one-dimensional solid-state image sensor 68 for detecting the position in the x direction at that time. From both figures, in the case of white illumination, there is almost no multiple interference of light within the photoresist, and therefore there is no effect of uneven coating, and a signal with extremely high contrast and good waveform symmetry can be obtained. I understand.
Therefore, when using a pattern position detection method that utilizes the symmetry of the signal waveform and sets the center of symmetry of the waveform as the center position of the alignment pattern, the pattern center position xa can be detected with very high accuracy. On the other hand, c in the figure is a detected image 77 of the x-direction alignment pattern 50 under monochromatic (g-line) illumination. Further, d in the same figure shows the detection signal waveform of the one-dimensional solid-state image sensor 68 at that time. From both figures, in the case of monochromatic lighting,
It can be seen that if multiple interference of light occurs within the resist and there is uneven coating of the photoresist near the alignment pattern, the detection signal becomes asymmetric. Then, the detected pattern center position becomes xb, and an error ex occurs with respect to the almost ideal center position xa under white illumination.

Therefore, before alignment, the pattern position detection error ex between both illuminations is detected in advance for all chips using this sub-pattern detection system, and alignment accuracy can be improved by making corrections based on this value during alignment. Improvements can be made. However, in consideration of throughput, it is preferable to estimate the detection error of all chips on a wafer by analogy from measurements of several chips. Therefore, in this embodiment, the latter method was adopted. This will be explained in detail below.
Generally, the effect of uneven coating of photoresist is most noticeable on chips 100 to 10 that cross the center of the wafer in the x and y directions, as shown in FIG.
It is 8. First, this sub-pattern detection system detects the x and y direction patterns 100x and 100y of the chip 100 using white monochromatic illumination. The detected center positions are respectively (xaO, yaO) (white illumination) and (xbO, ybO) (monochromatic illumination), and the pattern position detection errors e _xp and e _yp between both illuminations are (1 ) and (2)
Calculated using the formula.

e _xo = x _ao -x _bo (1) e _yo = x _ao -x _bo (2) where n = 0 to 8 Next, for chips 101 to 104, the x direction pattern, for chips 105 to 108,
The directional pattern is similarly detected using white/monochromatic illumination. The detected center positions are respectively x _a1 ~ _{x a4}
(white illumination), x _b1 to x _b4 (monochromatic illumination), y _a5 to y _a8 (white illumination), and y _b5 to _{y b8} (monochromatic illumination). Similarly, pattern position detection error e _xo , e _yo (n=1~
8) is calculated using equations (1) and (2). Figure 5 shows
The design coordinates of the x-direction patterns 100x to 104x are (x ₀ , y _x ) to (x ₄ , y _x ), respectively, and the y-direction patterns 100y, 105y to 105y to 108y
The design coordinates of (x _y , y ₀ ), (x _y , y ₅ ) ~
Position detection error of each pattern when (x _y , y ₈ )
It shows e _x0 to e _x8 , e _y0 , e _y5 to e _y8 . The size of the arrow indicates the magnitude of the error, and the direction of the arrow indicates the direction of the error.

Next, from these position detection error data, a virtual origin (x _s , y _s ) with the minimum error is determined. Figures 6a and 6b are plots of pattern position detection errors e _xo and e _yo between both illuminations in the x and y directions. From both figures, each error curve 7
9 and 80 can be quadratic approximated by equations (3) and (4).

e _x (x)=a _x x ² +b _x x+c _x (3) e _y (y)=a _y y ² +b _y y+c _y (4) Therefore, first, each coordinate of the pattern and the detected error are expressed in the above equation. Substitute and use the least squares method to obtain a _x , b _x ,
Find c _x , a _y , b _y , c _y . Then, by finding the x and y coordinates such that e _xo (x) = 0 and e _yo (y), the virtual origin (x _s , y _s ) is obtained.

Next, the pattern position detection error e _x , e _y between white and monochromatic illumination in the alignment pattern at any position
A general formula for analogy will be explained based on FIG.
_In the figure, the detection errors of the x- and y-direction alignment patterns near _the chip 82 are functions f _e (m _x ) and f _e
It is given as a mapping of the error amount expressed as (m _y ) in the x and y directions. Therefore, the general formulas are (5) and (6)
Expressed by the formula.

e _x ^* (x, y)=f _e (m _x )・cosθ _x (5) e _x ^* (x, y)=f _e (m _y )・sinθ _y (6) However, f _e (m _x ) = a _n m _x ² + b _n m _x + c _n f _e (m _y ) = a _n m _y ² + b _n m _y + c _n m _x =√( _x − _s ) ² + ( _x − _s ) ² m _y =√( _y − _s ) ² +( _y − _s ) ² θ _x =tan ^-1 (y _x −y _s )/(x _x −x _s ) θ _y = tan ^-1 (y _y −y _s )/ (x _y − x _s ) Here, f _e (m _x ) and f _e (m _y ) are expressed as the coordinates of each pattern and the detected pattern in equations (5) and (6), as shown in Figure 8. Substitute the error and calculate using the least squares method.

As described above, first, the sub-pattern detection system detects alignment pattern detection errors between white and monochromatic illumination for several chips on the wafer. Next, based on the error data, find the virtual origin (x _s , y _s ) where the error is minimum. Then, using equations (5) and (6), alignment pattern detection error e _x ^* (x, y) e _y ^* (x,
y) and store the data in memory (not shown)
to be memorized.

Now, after the alignment pattern detection errors of all chips are stored in memory, the wafer 45 is transferred by the arm 48 to the TTL alignment/exposure stage 41 and set as 46 in FIG. Here, after the θ rotation amount of the wafer is corrected, TTL alignment is performed for each chip. The TTL alignment optical system is the 13th
It is exactly the same as shown in the figure. Figure 9 shows the output signal from the photomul 10, with large signal changes at both ends indicating the edges of the reticle alignment pattern (window pattern), and the center of both edges.
x _r is the center position of the reticle alignment pattern. When a conventional pattern position detection method in which the center of symmetry of the waveform is set as the center position of the pattern is applied to the detection signal of the asymmetric wafer alignment pattern as shown in the figure, the detection center position becomes x _b .
However, the white color that I had found and memorized in advance
Using the detection error amount e _x ^* (x, y) between monochromatic illumination,
By adding correction as shown in equation (7),
Ideally, the center position x _a of the wafer alignment pattern can be determined with extremely high accuracy under white illumination.

x _a = x _b + e _x ^* (x, y) (7) Calculate the alignment amount △ from the corrected center position x _a of the wafer alignment pattern and center position x _r of the reticle alignment pattern, and move the stage 41
Move slightly in the x direction. The situation is exactly the same for alignment in the y direction. When the alignment is completed, exposure light is emitted from the exposure system 12,
The circuit pattern of reticle 1 is printed onto a chip on a wafer. The above operation is repeated for each chip, and when all the chips have been exposed, the wafer is discharged by the discharge side track 47. As described above, alignment can be performed by correcting detection errors caused by uneven photoresist coating caused by multiple interference within the photoresist unique to monochromatic illumination, which has been a problem in the past, for each chip, thereby improving alignment accuracy. In addition, in this example, a method was used in which the amount of detection error for several chips on a wafer was measured and the amount of detection error for all chips was estimated from that data. Measure the amount of detection error in advance,
It is also possible to store the data in memory. In that case, it is not necessary to use equations (1) to (6).

Next, the second embodiment of the present invention is shown in FIGS. 10 and 1.
This will be explained using Figure 1. FIG. 10 shows a stage that further improves the configuration of the aligner shown in FIG. 11 and is equipped with a sub-pattern detection system 51 for the purpose of measuring alignment pattern detection errors of all chips.
This figure shows an aligner that combines a TTL alignment and exposure stage. 87 is
A coarse movement stage 88 moves in the XY directions, 88 is for pattern detection error measurement, and 89 is an XYθ fine movement stage for TTL alignment and exposure. After pre-alignment (not shown), the wafer on which the pattern detection error amount between white and monochromatic illumination is to be measured is placed on stage 88 at 9
It is set as 3. At this time, the wafer awaiting exposure, whose pattern detection error amount has already been measured and whose data has been stored in a memory (not shown), is set on the stage 89 as shown at 90, and the θ rotation has been corrected. Next, while these two wafers are moved step-and-repeat by a coarse movement stage 87, one detects the alignment pattern of each chip in both x and y directions by a sub-pattern detection system 51 under white monochromatic illumination. Both detected position data are stored in a temporary memory (not shown). On the other hand, through the reduction projection lens 2, alignment is performed for each chip while correction is applied based on the amount of detection error between the two illuminations stored in the memory in advance, and then the chip is exposed. In order to shorten the operation time of both stages, the detection error amount is calculated from the previously stored pattern detection position data under both illuminations when the wafer 93 is transferred from the stage 88 to the stage 89. be exposed. FIG. 11 shows the aligner of FIG. 10 viewed from above, and alignment pattern detection, TTL alignment, and exposure are always performed on corresponding chips of two wafers using white monochromatic illumination.
According to this embodiment, highly accurate alignment is possible with a throughput comparable to that of the conventional method, without requiring time for pattern detection using white/monochromatic illumination. Furthermore, if the sub-pattern detection system 51 is improved (not shown) so that both x and y alignment patterns can be detected simultaneously, the stage 88
The operating time can be further reduced.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 12 shows a sub-pattern detection system 51 in which the configuration of the aligner shown in FIG. 10 is further improved.
This figure shows an aligner with a single stage attached to a TTL alignment/exposure stage. 96 is white/monochrome illumination pattern detection and
This is an XYθ precision stage for TTL alignment and exposure. After pre-alignment is completed (not shown)
For the wafer set as 97, pattern position detection error data is measured by the sub-pattern detection system 51 and stored in the memory in the same manner as in the first embodiment. Next, alignment is performed for each chip while making corrections based on the stored error data, and then exposure is performed. In this embodiment, if pre-alignment is also performed by the sub-pattern detection system 51, which also serves as white/monochrome illumination pattern detection, there is almost no reduction in throughput and the device configuration is extremely simple.

〔Effect of the invention〕

As explained above, according to the alignment method of the present invention, uneven coating of photoresist, which has been pointed out in the past but still remains unsolved, is becoming a serious problem as semiconductor circuits become highly integrated. The reduction in alignment accuracy caused by this can be eliminated, alignment with stable and high accuracy is possible, and high productivity and reliability can be achieved. In addition, the time required for pattern detection under white/monochromatic illumination can be ignored, resulting in a throughput comparable to conventional chip alignment.Compared to conventional methods, this method has the effect of improving accuracy and providing high overall performance. play.

[Brief explanation of drawings]

Figure 1 is a top view of the two-stage aligner;
The figure is a perspective view of the sub-pattern detection system in Figure 1, Figures 3 a to d are diagrams showing differences in alignment pattern detection images and detection signals in white illumination and monochromatic illumination, and Figure 4 is detection by the sub-pattern detection system. A plan view showing the alignment pattern to be
Figure 5 is a diagram showing the detection error of alignment patterns detected with white and monochromatic illumination between both illuminations,
Figures 6a and b are diagrams showing the error curves of the alignment pattern in the x and y directions, Figure 7 is a diagram showing the method for deriving the position detection error of the alignment pattern at an arbitrary position, and Figure 8 is the diagram showing the distance from the virtual origin. FIG. 9 is a diagram showing the relationship between the position detection error of the alignment pattern, and FIG. 9 is a diagram showing the output signal from the photomultiplier.
The figure is a perspective view of a 1-stage, 2-wafer type aligner, Figure 11 is a top view of the aligner shown in Figure 10, Figure 12 is a perspective view of a 1-stage, 1-wafer type aligner, and Figure 13 is a conventional TTL alignment method. FIG. 14 is a perspective view showing the flow direction of the photoresist spin-coated onto the wafer and an enlarged wafer alignment pattern, and FIGS. 15a and b show the photoresist film thickness distribution according to the direction of the alignment pattern. Figure 16a, which shows the difference between
Similarly, Fig. 17 shows the relationship between the photoresist film thickness and the interference intensity, and Fig. 18 shows the magnitude of the alignment error in each chip on the wafer. FIG. 19, a plan view showing the directions, is a diagram showing the x and y direction components of the alignment error. Explanation of symbols, 1... Reticle, 2... Reduction projection lens, 3... Wafer, 14, 14', 19, 2
0,50,50',100x~108x,100
y~108y, 83, 83', 99, 99'...Wafer alignment pattern, 51...Sub pattern detection system, 87...Coarse movement stage, 88, 89,
96...Seido stage.

Claims (1)

[Scope of Claims] 1. In a method of aligning a reticle circuit pattern when exposing a reticle circuit pattern onto a wafer through a reduction projection lens, the first enlargement lens and the first A pattern detection optical system equipped with an imaging device illuminates the alignment pattern on the wafer with white illumination light and monochromatic illumination light with the same wavelength as the alignment illumination light, and detects the alignment pattern on the wafer under each illumination light. Position detection is performed to determine the position detection error amount from the difference between both position detection signals, and the alignment pattern on the reticle illuminated by the alignment illumination light and the alignment pattern on the wafer are transferred to the second image through the reduction projection lens. magnifying lens and second
A reduction projection type alignment method characterized in that the reticle and the wafer are relatively aligned by detecting the alignment using an alignment optical system equipped with an imaging device, and correcting the detected alignment amount using the position detection error amount. . 2 The position detection error amount is obtained by detecting the position of the alignment pattern for the center and peripheral parts of the wafer, and for other arbitrary positions, the position detection error amount is determined from the relationship between the determined position detection error amount and its position coordinates. 2. The reduction projection type alignment method according to claim 1, characterized in that the amount of detection error is calculated and determined. 3. The reduction projection alignment method according to claim 1, wherein the white illumination light exhibits a flat spectral distribution that does not include a bright line spectrum. 4. When exposing a reticle circuit pattern onto a wafer through a reduction projection lens, the alignment pattern on the wafer is illuminated with white illumination light and monochromatic illumination light having the same wavelength as the alignment illumination light in a device that aligns both. A first illumination means, and a first magnifying lens magnifies an image of the alignment pattern on the wafer under each illumination light illuminated by the first illumination means, and the image is captured by a first imaging device. a pattern detection means for converting and detecting a video signal indicating the positions of both alignment patterns; and a position detection error amount calculation for calculating a position detection error amount from the difference between both position detection signals detected by the pattern detection means. a second illumination means for illuminating the alignment pattern on the reticle and the alignment pattern on the wafer, and an image of both the alignment patterns illuminated by the second illumination means is transmitted through the reduction projection lens. obtained, magnify it with a second magnifying lens, image it with a second imaging device,
an alignment detection means for detecting the alignment amount by converting it into a video signal, and correcting the alignment amount detected by the alignment detection means with the position detection error amount calculated by the position detection error amount calculation means, and a reticle. 1. A reduction projection type alignment apparatus, characterized in that it is equipped with alignment correction means for relatively aligning a wafer. 5. The position detection error calculation means further calculates, for any position on the wafer, the difference between the position signals detected by the pattern detection means for the center and peripheral parts of the wafer, and the position coordinates thereof. 5. The reduction projection type alignment apparatus according to claim 4, characterized in that the position detection error amount is calculated from the relationship. 6 The white illumination light in the first illumination means is:
5. The reduction projection type alignment apparatus according to claim 4, characterized in that the spectral distribution is configured to exhibit a flat spectral distribution that does not include a bright line spectrum.