JPH0467655B2 - - Google Patents

Info

Publication number
JPH0467655B2
JPH0467655B2 JP60163222A JP16322285A JPH0467655B2 JP H0467655 B2 JPH0467655 B2 JP H0467655B2 JP 60163222 A JP60163222 A JP 60163222A JP 16322285 A JP16322285 A JP 16322285A JP H0467655 B2 JPH0467655 B2 JP H0467655B2
Authority
JP
Japan
Prior art keywords
interrupt
processing
signal
microprocessor
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60163222A
Other languages
Japanese (ja)
Other versions
JPS6222128A (en
Inventor
Hiroshi Maeda
Tomikatsu Shiraishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60163222A priority Critical patent/JPS6222128A/en
Priority to EP86110006A priority patent/EP0215236B1/en
Priority to DE8686110006T priority patent/DE3674307D1/en
Publication of JPS6222128A publication Critical patent/JPS6222128A/en
Priority to US07/244,569 priority patent/US4981296A/en
Publication of JPH0467655B2 publication Critical patent/JPH0467655B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Control By Computers (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)

Description

【発明の詳細な説明】 〈技術分野〉 本発明はクロツク発振器の発振信号に応答して
動作するマイクロプロセツサを備え、当該マイク
ロプロセツサの処理速度を切換え可能にしたデー
タ処理装置に関するものである。[Detailed Description of the Invention] <Technical Field> The present invention relates to a data processing device that is equipped with a microprocessor that operates in response to an oscillation signal from a clock oscillator, and that is capable of switching the processing speed of the microprocessor. .

〈従来技術〉 マイクロコンピユータ等にあつて、低処理速度
機向けに開発されたゲームソフト等のプログラム
を、高処理速度機で実行すると、ゲーム操作キー
等のキー操作が追征できなくなる。即ち、キー入
力待ち時間が短くなつて、キー入力ができなくな
る。<Prior Art> When a program such as game software developed for a low processing speed machine is executed on a high processing speed machine in a microcomputer or the like, key operations such as game operation keys cannot be performed. That is, the waiting time for key input becomes shorter and key input becomes impossible.

そのため、従来は、マイクロプロセツサのクロ
ツク周波数を切替える方法が用いられていたが、
それではハード的に高価となつてしまう。 For this reason, the conventional method used was to switch the clock frequency of the microprocessor.
That would make the hardware expensive.

〈発明の目的〉 本発明は上述した事項に鑑み、マイクロプロセ
ツサの動作周波数は一定に保つたまま、処理速度
が変更可能としたデータ処理装置を提供すること
を目的とする。<Object of the Invention> In view of the above-mentioned matters, an object of the present invention is to provide a data processing device in which the processing speed can be changed while the operating frequency of the microprocessor is kept constant.

〈実施例〉 以下、本発明の構成を説明する。<Example> The configuration of the present invention will be explained below.

本発明の実施例に係るデータ処理装置は、発振
器の出力を分周することにより、一定周期で割込
み信号を発生させ、当該割込み信号２回につき１
回の割合で時間待ちループを実行し、それによつ
てマイクロプロセツサのみかけの処理速度を下げ
る構成とした。 The data processing device according to the embodiment of the present invention generates an interrupt signal at a constant period by frequency-dividing the output of the oscillator, and generates one interrupt signal for every two interrupt signals.
The configuration is such that a time waiting loop is executed at a certain rate, thereby reducing the apparent processing speed of the microprocessor.

第１図に本実施例のデータ処理装置の概略ブロ
ツクを示す。 FIG. 1 shows a schematic block diagram of the data processing apparatus of this embodiment.

図中、１は主制御ユニツトCPU（マイクロプロ
セツサ）であり、図示しないROM（リード・オ
ンリ・メモリ）に記憶するシーケンスプログラム
によつて制御動作を行う。該シーケンスプログラ
ムの一部を第２図及び第３図に示す。 In the figure, 1 is a main control unit CPU (microprocessor), which performs control operations based on a sequence program stored in a ROM (read-only memory) not shown. A part of the sequence program is shown in FIGS. 2 and 3.

前記CPU１は発振器２からクロツク信号Clock
を受けて動作する。又、該CPU１は前記クロツ
ク信号を所定数分周する分周回路３からのインタ
ーラプト信号によつて割込み処理へ移行する。こ
の分周回路３の出力は、有め決められた所定時間
間隔でラツチ回路４に供給される。その後、該ラ
ツチ回路４は、インターラプト（割込み）信号
INTRを出力し、該インターラプト信号をCPU
１に供給する。 The CPU 1 receives the clock signal Clock from the oscillator 2.
It operates according to the following. Further, the CPU 1 shifts to interrupt processing in response to an interrupt signal from a frequency dividing circuit 3 which divides the frequency of the clock signal by a predetermined number. The output of this frequency divider circuit 3 is supplied to a latch circuit 4 at predetermined time intervals. After that, the latch circuit 4 outputs an interrupt signal.
Outputs INTR and sends the interrupt signal to the CPU
Supply to 1.

CPU１は、前記インターラプト信号によつて
割込み処理可能時、インターラツプアクノリツジ
（割込認識）信号INTAを出力して、前記ラツチ
回路４をリセツトし、割込み処理へ移行したこと
を判定する。 When the interrupt processing is enabled by the interrupt signal, the CPU 1 outputs an interrupt acknowledge signal INTA, resets the latch circuit 4, and determines that the interrupt processing has started. .

又、このラツチ回路４は他のデバイスにも利用
され、CPU１への割込み処理を起動させる。 This latch circuit 4 is also used by other devices to start interrupt processing to the CPU 1.

５はキーボード装置であり、各種データ入力キ
ー、フアンクシヨンキーが設けられる。本実施例
に関しては、カーソルキー５ａ、Set upキー５
ｂ並びにスペースキー５ｃである。 5 is a keyboard device provided with various data input keys and function keys. In this embodiment, the cursor key 5a, the Set up key 5
b and space key 5c.

６は、LCD（液晶）デイスプレイの表示データ
を記憶するビデオメモリである。 6 is a video memory that stores display data of an LCD (liquid crystal) display.

第２図について説明を行う。 An explanation will be given regarding FIG. 2.

データ処理装置に電源投入（Power on）が行
なわれるが、又は、Set upキー５ｂが操作され
ると（S0ステツプ）、シーケンスプログラムによ
つて予め定められたSet upメニユーデータがビ
デオメモリ６に記憶され、LCDデイスプレイ７
に第４図のように表示が成される（S1ステツプ）。 When the data processing device is powered on or the Set up key 5b is operated ( S0 step), the Set up menu data predetermined by the sequence program is stored in the video memory 6. Memorized and LCD display 7
A display as shown in Fig. 4 is created (S 1 step).

操作者はカーソルキー５ａを操作して、表示上
のプロセツサスピード変更指示欄５１にカーソル
マーク５０を移動させる（S2ステツプ）。すると、
図示しないカーソルカウンタがカーソル位置に応
じた値にカウントを更新する（S3ステツプ）。 The operator operates the cursor key 5a to move the cursor mark 50 to the processor speed change instruction column 51 on the display (step S2 ). Then,
A cursor counter (not shown) updates the count to a value according to the cursor position (step S3 ).

続いてスペースキー５ｃを操作すると（S4ステ
ツプ）、上記プロセツサスピード変更指示欄５１
であるか判定して（S6ステツプ）、slowフラツグ
がONであれば該slowフラツグをOFFにし（S6→
S7ステツプ）、それとは反対にslowフラツグが
OFFであれば該slowフラツグをONにする（S6→
S8ステツプ）。 Next, when you operate the space key 5c (step S 4 ), the processor speed change instruction field 51 is displayed.
(S 6 step), and if the slow flag is ON, turn the slow flag OFF (S 6 →
S 7 steps), on the other hand, the slow flag
If it is OFF, turn on the slow flag (S 6 →
S 8 steps).

その後、“solw”のメツセージデータ、若しく
は“standard”のメツセージデータをビデオメ
モリ６に書き込み（S9及びS10ステツプ）、当該メ
ツセージデータのいずれかをプロセツサスピード
欄５２に表示する。 Thereafter, either the "solw" message data or the "standard" message data is written into the video memory 6 (steps S9 and S10 ), and either of the message data is displayed in the processor speed column 52.

所定のモード設定が完了すると、Set upキー
５ｂを操作して、モード設定に応じた処理へと移
行する。 When the predetermined mode setting is completed, the user operates the Set up key 5b to proceed to processing according to the mode setting.

インターラプトの割込み信号により、第３図の
処理が実行される。 The processing shown in FIG. 3 is executed by the interrupt signal.

割込み処理において、今まで処理して途中で紙
えた各種データを、ランダム・アクセス・メモリ
RAM（図示せず）へ特定エリアに記憶して、退
避する（N1ステツプ）。 During interrupt processing, various data that has been processed and generated during the process is stored in random access memory.
Store it in a specific area in RAM (not shown) and save it ( N1 step).

次いで、割込み回数をカウントするカウンタが
奇数であるか否か判定する（N2ステツプ）。 Next, it is determined whether the counter that counts the number of interrupts is an odd number ( N2 steps).

上記N2ステツプにおいて、判定した結果、カ
ウントが奇数であれば設定されたslowフラツグ
がONであるか否か判定される（N3ステツプ）。
もし、solwフラツグがONであると、N4ステツ
プのWHIT処理（時間待ちループ）へと移行す
る。 In the N2 step, if the count is an odd number, it is determined whether the set slow flag is ON ( N3 step).
If the solw flag is ON, the process moves to N4 step WHIT processing (time waiting loop).

WAIT処理は、予め決められた時間のウエイ
ト処理を行うために、プログラム処理によつて、
例えば所定ステツプのNOP（No Operation）命
令を動作させることにより、WAIT時間を作動
させる（N4ステツプ）。 WAIT processing is performed by program processing in order to perform wait processing for a predetermined time.
For example, by operating a NOP (No Operation) command at a predetermined step, the WAIT time is activated ( N4 step).

上記N2ステツプにおける判定の結果、カウン
トが偶数回であれば、通常の割込み処理又は直ち
に割込み処理を完了する（N5ステツプ）。 As a result of the determination in the above N2 step, if the count is an even number, the normal interrupt processing or the interrupt processing is immediately completed ( N5 step).

上述の処理後、回数を１カウントアツプして
（N6ステツプ）、上記退避したRAMのレジスタを
再び処理するための復帰動作を行い、割込み動作
が完了する（N7ステツプ）。 After the above processing, the number of times is incremented by 1 ( N6 steps), and a return operation is performed to process the saved RAM register again, and the interrupt operation is completed ( N7 steps).

なお、上記実施例では、マイクロプロセツサ
CPUの見かけの処理速度を基本と低速の２段階
で切換可能としたが、低速の方を２段階以上にし
処理速度の選択の幅を広げることも考えられる。 Note that in the above embodiment, the microprocessor
Although the apparent processing speed of the CPU can be switched between two levels, basic and low speed, it is also possible to increase the range of processing speed selection by setting the lower speed to two or more levels.

例えば、割込み信号２回につき１回の割合で時
間待ち処理を行う場合と、割込み信号10回につき
１回の割合で時間待ち処理を行う場合とを選択可
能とすることが想到される。 For example, it is conceivable to be able to select between performing time waiting processing once for every two interrupt signals and performing time waiting processing once for every 10 interrupt signals.

〈効果〉 以上のように本発明のデータ処理装置によれ
ば、特にハードウエアを追加しなくても、簡単な
制御プログラムを付加するだけで、使用するプロ
グラム内容に応じた処理速度を使用者が選択する
ことが出来る。<Effects> As described above, according to the data processing device of the present invention, the user can adjust the processing speed according to the content of the program to be used by simply adding a simple control program without adding any particular hardware. You can choose.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例に係るデータ処理装置
のブロツク構成図、第２図及び第３図は前記デー
タ処理装置の処理を示すフローチヤート、第４図
は前記データ処理装置の表示内容を示す図であ
る。 １…CPU、２…発振器、３…分周回路、４…
ラツチ回路、５…キーボード装置、６…ビデオメ
モリ、７…LCDデイスプレイ。 FIG. 1 is a block configuration diagram of a data processing device according to an embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing the processing of the data processing device, and FIG. 4 shows the display contents of the data processing device. FIG. 1... CPU, 2... Oscillator, 3... Frequency divider circuit, 4...
latch circuit, 5...keyboard device, 6...video memory, 7...LCD display.

Claims (1)

【特許請求の範囲】 １ クロツク発振器の発振信号に基づき動作する
マイクロプロセツサを備えるデータ処理装置にお
いて、 前記クロツク発振器のクロツク信号に基づいて
所定時間毎に出力する割込み要求信号に応じてマ
イクロプロセツサに割込み信号を発生する発生手
段と、前記データ処理装置の選択可能な処理速度
を選択設定するための処理速度入力手段と、前記
入力手段により設定された処理速度モードを記憶
保持するモード保持手段と、前記モード保持手段
の出力に基づき少なくとも前記割込み信号の所定
数毎に時間待ち処理を介在させるか否かを制御す
る制御手段と を具備するデータ処理装置。[Scope of Claims] 1. In a data processing device including a microprocessor that operates based on an oscillation signal of a clock oscillator, the microprocessor operates in response to an interrupt request signal output at predetermined intervals based on the clock signal of the clock oscillator. generating means for generating an interrupt signal, processing speed input means for selecting and setting selectable processing speeds of the data processing device, and mode holding means for storing and holding the processing speed mode set by the input means. and control means for controlling whether or not to intervene in a time waiting process at least every predetermined number of interrupt signals based on the output of the mode holding means.
JP60163222A 1985-07-22 1985-07-22 Data processor Granted JPS6222128A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60163222A JPS6222128A (en) 1985-07-22 1985-07-22 Data processor
EP86110006A EP0215236B1 (en) 1985-07-22 1986-07-21 Data processing machine
DE8686110006T DE3674307D1 (en) 1985-07-22 1986-07-21 DATA PROCESSING SYSTEM.
US07/244,569 US4981296A (en) 1985-07-22 1988-09-12 Data processing machine with interrupt control for varying processing speed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60163222A JPS6222128A (en) 1985-07-22 1985-07-22 Data processor

Publications (2)

Publication Number Publication Date
JPS6222128A JPS6222128A (en) 1987-01-30
JPH0467655B2 true JPH0467655B2 (en) 1992-10-29

Family

ID=15769634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60163222A Granted JPS6222128A (en) 1985-07-22 1985-07-22 Data processor

Country Status (4)

Country Link
US (1) US4981296A (en)
EP (1) EP0215236B1 (en)
JP (1) JPS6222128A (en)
DE (1) DE3674307D1 (en)

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Also Published As

Publication number Publication date
EP0215236B1 (en) 1990-09-19
EP0215236A1 (en) 1987-03-25
JPS6222128A (en) 1987-01-30
US4981296A (en) 1991-01-01
DE3674307D1 (en) 1990-10-25

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