JPH0467653B2 - - Google Patents

Description

Detailed Description of the Invention [Summary] The random number generation circuit of the present invention is an addition type random number generation circuit having a feedback loop, so-called a Fibonacci type random number generation circuit, in which an adder has a pipeline structure and the addition By making the device also function as a shift register, it is possible to generate high-quality, long-period, uniformly condensed random numbers at high speed.

[Industrial Field of Application] The present invention relates to a random number generation circuit, and particularly to a random number generation circuit that rapidly generates random numbers used in simulations, etc., in, for example, a data processing device.

[Conventional technology]

Conventionally, pseudorandom numbers used in data processing devices have generally been generated by software, but consideration has been given to generating them quickly and easily using hardware circuits.

As conventional random number generation methods, for example, the linear congruence method and the M-sequence method are known. In the linear congruence method, random numbers x _o are sequentially generated by performing the calculation x _o =a·x _o-1 +c mod2 ^m . Since this method involves multiplication, it is usually uneconomical to use dedicated hardware, and the period of the random numbers is limited by the word length m, and the random numbers exhibit high-dimensional regularity.

In addition, in the M-sequence method, each bit of a random number (integer) is independently expressed as: b _o = a ₁・b _o-1 a ₂・b _o-2 ……a _N・b _oN (・ is a logical product, indicates an exclusive OR operation) Random numbers x _o are sequentially generated by performing the logical operation. This method has the advantages of being able to set the random number cycle to be long independently of the word length, being relatively easy to implement in hardware, generating random numbers at high speed, and not exhibiting high-dimensional regularity. . However, it has also been pointed out that the local statistical properties of random numbers obtained by the M-sequence method are not necessarily satisfactory. In addition, in the M-sequence method, based on the theory of ternary primitive polynomials, a specific
Only a _p and a _N were made non-zero.

The form b _o = b _op b _oN is adopted for the purpose of hardware simplification.

A random number generation method using a higher-order congruence method, which is a more general version of the above two methods, is also known. FIG. 3 shows a conceptual diagram of a general Fibonacci random number generation circuit to which the present invention relates.

In this method, random numbers are generated by performing the calculation x _o = x _op + x _oN mod2 ^m . In Figure 3,
The shift register 20 has a bit width of m bits.
It is a stage shift register. Adder 21 performs addition of m-bit integers.

The initial value to the shift register 20 is first supplied via the multiplexer 22, and thereafter the output of the adder 21 is fed back to the shift register 20.

[Problem that the invention seeks to solve]

The random number generation method using the high-order congruential method shown in Figure 3 has a long random number generation period (<2 ^m+N ), and by appropriately selecting p and N, it is possible to generate statistically high-quality random numbers. Since it is possible to do this, it is thought that there are great advantages to implementing it in hardware. but,
Although the theory of this method is already known, there are few examples of its actual use in software, and there are almost no examples of its implementation in hardware. This is because the m-bit addition operation by the adder 21 takes longer than the M-sequence method, which slows down the speed of random number generation.

An object of the present invention is to solve the above-mentioned problems and provide a high-speed random number generation circuit using a high-order congruential method consisting only of addition.

[Means for solving problems]

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, 10 is an N-p stage first shift register, 11 is a pipeline type m-bit integer adder, 12 is a feedback forming unit that feeds back the output of the adder 11 to the first shift register 10, and 13 is a a second shift register of p-k stages;
Reference numeral 14 represents a multiplexer used to set an initial value for the first shift register 10, and reference numeral 15 represents a clock circuit that supplies clock signals to the first shift register 10, the adder 11, the feedback forming section 12, and the like.

In the present invention, in order to realize a random number generation circuit of the form x _o = x _op + x _oN mod2 ^m , the adder 11 has a k-stage pipeline structure as shown in FIG. The roles of shift registers for k stages are shared. Although the random number is taken out from the output part of the adder 11, it is of course possible to take out the random number from any arbitrary place in the first shift register 10, second shift register 13, etc.

The operation is as follows. First, an initial value is selected as an input to the multiplexer 14 using a control signal based on the decoding result of an instruction, and the N initial values are sequentially taken in by N clock pulses.
As a result, the first shift register 10, the adder 1
1 pipeline, data is set in the second shift register 13. Therefore, multiplexer 14
When switched to the feedback side, the random value is sequentially updated for each clock pulse.

The total number of stages N and the parameter p may be selected as appropriate mathematically, but especially for the adder 1.
If the number of pipeline stages k in 1 is the same as the parameter p, the second shift register 13 is
It can be practically omitted.

[Effect]

According to the present invention, since the adder 11 has a pipeline structure and also functions as a shift register, the clock circuit 1
The period of the clock pulse provided by 5 can be shortened to the processing time of each pipeline stage, rather than from the start to the end of the addition. Also, for the number of pipeline stages k,
Since the number of stages of the shift register can be shortened, the amount of hardware can be reduced.

〔Example〕

FIG. 2 is an example of an adder used in the present invention, and shows a 24-bit adder with a five-stage pipeline.

The hardware configuration of the pipeline pole adder is
Various methods are possible depending on the parameter p, word length m, clock frequency, etc. For example, what is shown in Figure 2 can be realized with a five-stage pipeline by using an 8-bit carry look-ahead circuit (carry look ahead circuit) CL when p = 5 and m = 24. It is something that In the random number generation circuit using this adder, random numbers x _o are sequentially generated based on the following equation: x _o =X _o-5 +X _o-17 mod2 ²⁴ .

In this example, since p=k=5, the first shift register 10 shown in FIG. 1 has "12 stages",
The second shift register 13 becomes unnecessary. Adder 1
The inputs A ₀ , A ₁ , and A ₂ to the first shift register 10 each have 8-bit data to be input to the first shift register 10 , and the other inputs B ₀ , B ₁ , and B ₂ have data input from the first shift register 10 . This is the output of each 8 bits.

In stage ST1, P ₀ , P ₁ , P ₂ are each
The exclusive OR of the corresponding bits in A ₀ , A ₁ , A ₂ and B ₀ , B ₁ , B ₂ is set, and G ₀ , G ₁ , G ₂
is set to the logical AND of the corresponding bits.
In stage ST2, the 8-bit carry reel pick circuit CL carries out the carry of the least significant byte.
C ₂ is required. In stage ST3, P ₂ and
The exclusive OR of _C2 is calculated by the circuit SUM, and the 8-bit carrier reel head circuit
Carry C ₁ in the second byte is determined by CL. This kind of processing is stage ST5
repeated every clock until A ₀ , A ₁ , A ₂
and the 24-bit addition result of B ₀ , B ₁ , B ₂ S ₀ , S ₁ ,
_S2 is output after stage ST5.

〔Effect of the invention〕

As explained above, according to the present invention, long-period, high-quality random numbers can be generated at high speed.
In addition, it is possible to partially reduce the amount of shift register hardware.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of the present invention, Figure 2 is an example of a 24-bit adder with a 5-stage pipeline used as an embodiment of the present invention, and Figure 3 is a general Fibonacci type high random number generation speed. A conceptual diagram of the circuit is shown. In the figure, 10 is a first shift register, 11 is a pipeline pole m-bit integer adder, 12 is a feedback forming section, 13 is a second shift register, and 14
1 represents a multiplexer, and 15 represents a clock circuit.

Claims (1)

[Scope of Claims] 1. In an additive random number generation circuit having a feedback loop, a multi-stage shift register holding a plurality of pieces of data, the plurality of pieces of data being held are shifted at every predetermined clock. shift register 1
0, and an adder 11 which has a pipeline structure and processes an addition operation on two pieces of data input and output from the shift register 10 at a predetermined interval at each stage of the pipeline every predetermined clock. , the output of the adder 11 is transferred to the shift register 10
Circuit 1 to form a feedback loop
2. A random number generation circuit comprising: