JPH0465736A - Address lock system - Google Patents

Abstract

PURPOSE:To reduce the capacity of hardwares and to simplify control by comparing an address obtained by adding address width corresponding to the sort of an access to a start address and the start address respectively with a lock address. CONSTITUTION:At the time of receiving an unlocked access, an adding means 20 adds a previously determined access address width selected by a selecting means 22 in accordance with the sort of the access to an access start address. A lock address register means 18 stores a valid bit to be turned on by a locked access and a lock start address. Only when an address coincidence comparing output is obtained from any one of comparing means 24-1 to 26-2 for respectively comparing the start address and the added address with the lock start address, an access to a locked memory area is decided and the memory access is inhibited. Consequently, the comparison of the lock address with the access address can be simply and easily decided, the capacity of hardwares can be reduced and the control of the system can be simplified.

Description

[Detailed Description of the Invention] [Summary] When data is transferred between a plurality of processing units and a shared memory via a shared memory control unit by packet transfer using a start address, data length, address interval, and access type as access information. Regarding the address lock method, the purpose of this method is to make the comparison between the lock address and the access address simple and easy, and the start address is used to perform the comparison between the lock address and the access address at the beginning of packet transfer. In comparing and determining the start address, the start address and the addition address, which is the start address plus the address width determined by the type of access, are each compared with the lock start address, and bit comparisons that are less than the address width determined by the type of access are not necessary. Configure it as follows.

[Industrial Application Field] The present invention relates to an address locking method when data is transferred between a plurality of processing units and a shared memory via a shared memory control unit by packet transfer.

When data is transferred between multiple processing units and shared memory using packet transfer via the shared memory control unit, when a locked access is received from a specific processing unit, subsequent access from other processing units is blocked. , performs a comparative judgment between the lock address and the access address,
If the address is included in the lock address, address lock control is performed to make access wait until the lock is released.

However, in conventional address lock control, address comparison is performed for all bits, and a comparison with the lock address register must be performed for each element of hacket transfer, which increases the amount of hardware required for control. becomes complicated, and it is desired to realize simpler address comparison.

I try to do that.

[Prior Art] Conventionally, in an information processing system including a shared memory control unit and a shared memory unit for multiple processing units such as a cluster,
It has the start address, data length, address interval, and access type as access information for the shared memory section, and read or write data between the cluster and the shared memory section under the control of the shared memory control section by packet transfer. Transfer is in progress.

In such a memory access method that performs packet transfer, when a cluster receives a lock access and then receives a normal access from another cluster, the memory area targeted for the lock access is If it is determined that the access is to a locked memory area, the access is prohibited until the lock is released; on the other hand, if it is determined that the access is not to a locked memory area, the access is [Problem to be Solved by the Invention] However, in such a conventional address lock method, the lock access comparison circuit must compare all bits, for example, 32 bits, and the packet Comparison with the lock address register must be performed for each transfer element, which increases the amount of hardware, and the control becomes complicated as the hardware and control timing increase.

The present invention has been made in view of these conventional problems, and provides an address that makes it simple and easy to compare and judge a lock address and an access address, thereby reducing the amount of hardware and simplifying control. The purpose is to provide a locking method.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention provides a plurality of processing units 10-1 and 10-2.
, a memory control unit 12, and a shared memory unit 14, and has a start address, data length, address interval, and access type as access information for the shared memory unit 14K, and also has a start address, a data length, an address interval, and an access type, and the shared memory control unit 12 by packet transfer.
The object is a device that transfers data between the processing unit 10-1, 10-2 and the shared memory section 14 under the control of the processor.

In the address lock method of the present invention for such a device, the lock access control means 16 provided in the shared memory control unit 12 uses a valid bit and a lock start address that are turned on by lock access from a specific processing unit. When a non-locked access is received from another processing unit, the access start address is set to a predetermined access address width (selected by the selection means 22 according to the type of access). (W1, W2); first comparison means 24-1, 24-2 that extracts a comparison target bit portion according to the type of access from the lock address register means 18 and compares it with the lock start address; Second comparison means 26-1.26- which extracts a comparison target bit portion according to the type of access from the lock address register means 18 and compares it with the addition address of the addition means 20.
2 and ; are provided, and the valid bit of the lock address register means 18 is on and the first and second comparing means 24-1 to 26
-2, only when a comparison output indicating address coincidence is obtained, it is determined that the access is to a locked memory area, and the memory access is prohibited.

Here, there are at least two types of access: continuous access that accesses a continuous memory area determined by the data length from the start address, and distance access that sequentially accesses distributed memory areas determined by the address interval and data length from the start address. Contains seeds.

Also, lock address register means 18, addition means 20,
The selection means 22, the first comparison means 24-1, 24-2, and the second comparison means 26-1, 26-2 select data widths greater than or equal to the data width (W1, W1) according to the type of access in the start address. It is characterized by handling the bit part as address data.

Specifically, the data width (W1) of consecutive addresses is 4K bytes, and the data width (W1) of distance access is 1M.
When used as a byte, 1 from the most significant bit during continuous access
The bits up to the 9th bit are handled as address data, and during distance access, the bits from the most significant bit to the 11th bit are handled as address data.

Furthermore, the shared memory control section 12 has a priority circuit section 3.
4, and the priority circuit section 34 is configured to provide a predetermined priority level when accesses are received from a plurality of processing units at the same time when the valid bit of the lock address register means 18 is off, and when both are accesses with a lock. Prioritizing the locked access of a higher unit, the valid bit of the lock access register means 18 is turned on and the lock start address is set, and when only one unit is accessing with lock, the locked access is performed regardless of the priority Prioritize access by turning on the valid bit and setting the lock start address, while
When an access is received while the valid bit of the lock address register means 18 is already on, the access is made to wait until the valid bit turns off.

[Operation] According to the address lock method of the present invention having such a configuration, the lock start address and the access start address are set at the beginning of the packet transfer without making a comparison judgment with the lock address register for each element of packet transfer. Furthermore, the address comparison does not use the entire address, but instead processes the bit part that is larger than the address width determined by the type of access as address data, which greatly reduces the amount of hardware configuration, and the control timing is packet-based. Since it is only the beginning of the transfer, it can be easily controlled as a result.

[Embodiment] FIG. 2 is an overall configuration diagram of an information processing device to which the address lock method of the present invention is applied. In Figure 2, 10-
1.10-2 is a cluster as a processing unit,
In this embodiment, the case where two units are provided is taken as an example. The clusters 10-1 and 10-2 may consist of one or more CPUs, a main storage device, and the like. 12 is a shared memory control unit, and 14 is a shared memory unit. The shared memory unit 14 can be commonly accessed by both clusters 10-1 and 10-2 under the control of the shared memory control unit 12, and the shared memory unit 14 and clusters 10-1, 10-2 Data transfer between the two uses a packet transfer method in which one piece of access data is collected into a packet. Further, the access information performed from the cluster 10-1 and 10-2 to the shared memory unit 14K includes a start address, data length, address interval, and type of access, and further includes access with lock that specifies whether or not the memory area is locked. Or normal access without lock.

Here, there are two types of locked access: locked access and unlocked access. That is, the cluster uses lock access to set an address in the lock register and turns on the VR bit, and upon receiving an access completion notification from the shared memory control unit 12, the same cluster makes unlock access and turns off the VR bit. This lock access and unlock access are always used in pairs from the same cluster.

In addition, as a type of access information,
In this embodiment, either continuous access or distance access is specified. Continuous access means, for example, as shown in the memory map of FIG. 6, a predetermined data length (address width W1), for example 4
Continuously read or write a KB memory area. On the other hand, distance access sequentially reads or writes separated memory areas determined by the data length and address interval starting from the start address, and the size of the maximum memory area that can be accessed from a distance (address width W2) is: For example, it is predetermined as 1 Mbyte.

FIG. 3 shows a block diagram of an embodiment of the shared memory control unit 12 shown in FIG.

In FIG. 3, first, on the input side from the cluster 10-1, there are provided a data buffer 30-1, a mover 32-1 serving as a reception control unit, and a transfer register 36-1 serving as an interface to the shared memory unit 14K. Similarly, on the input side from the cluster 10-2, a data buffer 30-
2. A mover 32-2 and a transfer register 36-2 are provided.

Access information from movers 32-1 and 32-2 is input to the priority circuit section 34K, and when accesses are received from two clusters 10-1 and 10-2 at the same time, the access information is determined according to predetermined priorities. I'm wearing it. A lock register circuit 16 as lock access control means is provided for the priority circuit section 34K. Details of this lock register circuit 16 are shown in the configuration diagram of an embodiment in FIG. The lock register circuit 16 determines whether or not a locked memory area of the shared memory unit 14 is being accessed by comparing the access start address at the start of packet transfer with the lock start address of the lock address register at that time. If a locked memory area is accessed, access will be allowed until the lock is unlocked, and if it is not a locked area, access will be allowed.

Access information from the mover 32-1 or 32-2 is transferred to the shared memory unit 14 via the transfer interface 36-1.
K is given.

At the same time, the access information from the movers 32-1 and 32-2 is transferred to the access pipeline 3 via the transfer interface 36-2 under the control of the priority circuit section 34K.
8 and shared memory section 1 by pipeline control.
4 is read or written, transfer control of the read data from the shared memory unit 14 to the transfer register 40 is performed, and finally, the read data is stored in the read buffer 42. Transfer interfaces 44-1 and 44-2 are provided following the read buffer 42, and the transfer interface 4
The read data is transferred from the transfer interface 44-1 to the cluster 10-1, and the read data is transferred from the transfer interface 44-2 to the cluster 10-1.
Read data is transferred to 0-2.

FIG. 4 is a block diagram of an embodiment of the lock register circuit 16 shown in FIG. 3.

In FIG. 4, reference numeral 18 is a lock address register, which includes a valid bit VR indicating the presence or absence of a lock, and a shared memory section 1.
The start address of the memory area that is locked in 4K, that is, the lock start address is stored. Here, if the valid bit VR is on due to a lock access, indicating that the shared memory unit 14 is locked, and if the valid bit VR is off due to an unlock access from the cluster that has performed the lock access, the shared memory unit 14 is locked. Indicates that there is no In addition, the lock start address has a bit width that can store the bit portion from the most significant bit 0 to the 20th bit, bit 19, based on the address width W1 during continuous access, which will be explained later.
The bit length is only 20 bits, which is ⅔ of the total number of address bits of 32.

For lock address register 18, selector 46
The lock start address obtained from the access information from the cluster 10-1 or 10-2 is stored. The selector 46 is selectively controlled by the priority circuit section 34.

The selection control by the priority circuit section 34K is as follows.

[Mode 1] When the valid bit vR of the lock address register 18 is off and lock accesses are received from clusters 10-1 and 10-2 at the same time, cluster 102 is given priority and cluster 10-1 is made to wait. Therefore, in this case, selector 4
6 selects the start address from cluster 10-2, turns on the valid bit VR of the lock address register 18, and stores bits 0 to 19 of the start address.

[Mode 2] After the valid bit VR of the lock address register 18 is off and accesses are received from clusters 10-1 and 10-2 at the same time, if the access from cluster 10-2 is not a lock access, then cluster 10 -1 is given priority.

That is, in this case, the selector 46 selects the upper part (0 to 19 bits) of the start address from the cluster 10-1 that has made the lock access and stores it in the lock address register 18, and at the same time the priority circuit unit 34 Turn on the valid bit VR. Conversely, if the cluster 10-1 side does not have lock access, priority is given to the cluster 10-2 side that has performed lock access, and similarly the lock start address is stored in the lock address register 18 and the valid bit VR is turned on. .

[Mode 3] If cluster 10-1 performs a lock access while the valid bit VR of the lock address register 18 is already on, cluster 10-1 accesses the lock from cluster 10-2. The user is forced to wait until the valid bit VR turns off during unlock access. Conversely, if cluster 10-2 performs a lock access while the valid bit VR is already on in the lock access from cluster 10-1, similarly, the valid bit VR is set to the valid bit VR by unlock access from cluster 10-1. Cluster 1 until turned off
Make 0-2 wait.

[Mode 4] Regardless of whether the valid bit VR is on or off, when a normal access is made from cluster 10-1 or cluster 10-2, lock start is performed by the lock register circuit section 16 shown in FIG. It is determined whether or not to permit access by comparing the address and the access start address.

In order to determine whether or not access is possible by comparison with the lock start address during normal access, in the embodiment of FIG. 4, the first comparator 24-1 is
1.24-12 and second comparator 26-11.26-1
2 are provided. First comparator 24-11.24-12
directly compares the start address of the lock address register 18 and the access start address transferred from the cluster 10-1.

On the other hand, second comparators 26-11 and 26-12 compare the start address of lock register 18 and the addition address from adder 20-1.

Adder 20-1 selector 22-1 at the start address
Outputs the value added with the address width according to the access type selected in . Selector 22-1 is set with data in which only 19 bits are turned on, corresponding to address width W1 during continuous access, and data in which only 11 bits are turned on, corresponding to address width W2 during distance access, is set. The control signal from the priority circuit IE34 selects 19-bit ON setting data during continuous access, and selects 19-bit ON setting data during distance access.
Data with 1 bit on is selected, added to the respective start addresses, and output to the first comparators 26-11 and 26-12.

Here, the bit data of the memory address in FIG. 4 will be explained with reference to FIG. 5.

In FIG. 5, the address data of the present invention has a 32-bit configuration when the most significant address bit is 0 and the least significant address bit is 31, and the weight of each bit is 1 byte for the least significant bit and 31 for the least significant bit. The upper bits are 2 GB.

On the other hand, regarding continuous access, the address width W1 is 4K bytes as shown in FIG. 6, and can be expressed by address data in which only the 20th address bit 19 from the most significant one in FIG. 5 is set as bit 1.

Therefore, in the case of continuous access, it is sufficient to compare address bits 19 and above. On the other hand, during distance access, the address width w2 is 1M byte as shown in Figure 6, and from Figure 5, IM is address bit 11, so in the case of distance access, address bits 11 and above need only be compared. .

However, in the present invention, a carry may occur because the start address at the start of packet transfer is compared. Therefore, 4K bytes or 1
The result of adding M bytes also needs to be compared as a lock address.

Here, address data with address bit 19 turned on corresponding to 4K bytes during continuous access is added to the access start address, and address data with address bit 11 turned on corresponding to 1M byte during distance access is added, and this addition is performed. The reason why the address is also compared with the lock address data will be explained.

Note that the address data is shown in FIG. 5 in hexadecimal notation, divided into 4-bit units and showing one digit.

The lock start address is now r3 in full bit representation.
Suppose that it is F F F F OOOJ.

On the other hand, the access start address for continuous access of 4K bytes is r3FFFFOOo in full bit representation.
Assume that it is in the range of ~3FFFFFFFFJ. In the present invention, since address bits 19 and above are used for comparison, the lock start address for comparison is r3 F F F
FJ, and the access start address for comparison is also r3 FF F FJ. When the lock start address and the access start address match, it is determined that the access is to the lock address, and the access can be made to wait.

However, when the access start address is in the range of r3FFFEOO1 to 3FFFFFFJ, which is 4K bytes earlier in full bit representation, the access end address is r3FFFFOOO to 3FFFFF because the access width is 4K bytes.
FFJ, and the access falls within the lock address range.

However, in this case, the access end address for comparison of bits 19 and above is r3FFFEJ, and the lock start address to be compared is r3 F F F F
J does not match, and it cannot be determined that this is a lock address access.

Therefore, the access start address r3 F F FE
” and roooolJ with only bit 19 turned on to obtain the addition address r3 FF F F FJ, and then add the start address r3 FF F F EJ and the addition address r3
Set the two F F FJ to the lock start address "3".
By comparing with F F FJ, it is possible to reliably determine whether or not the access will enter the lock address.゛In the embodiment of the present invention, address data with only address bits 19 or 11 turned on is added to the access start address and compared with the lock start address, but the access start address is left as is and the lock start address is It is exactly the same even if the subtracted address obtained by subtracting address data with only address bit 19 or 11 turned on from the lock start address is compared with the lock start address.

For the above reasons, in the embodiment of FIG. 4, the adder 20
-1, the value obtained by adding the address widths W1 and W2 according to the type of access to the start address is added to the second comparator 26-11.
．． It is compared with the lock start address of the lock address register 18 at 26-12.

Also, in the comparison circuit section, comparators 24-11 and 26-11
is valid during distance access, and comparator 2
4-12.26-12 is valid during continuous access.

The outputs of the comparators 24-11 to 26-12 are sent to the OR gate 48.
-1 and is applied to terminal 50-2.

On the other hand, corresponding to the cluster 10-2, similarly to the cluster 10-1 side, the first comparator 24-21, 24-22, the second comparator 26-21, 26-22, the adder 26-2, the selector 22 -2 and an OR gate 48-2 are provided to similarly perform a comparison operation between the lock start address and the access start address depending on the type of access.

As is clear from FIG. 4, the terminal 50 is connected to the lock register circuit 16 for the priority circuit section 34K of FIG.
On/off signal of valid bit VR from -1, OR age
Comparison outputs from terminals 50-2 and 50-3, which are the outputs from 48-1, are provided.

When the valid bit is on and a comparison result of address matching is obtained from either terminal 50-2 or 50-3, the priority circuit 34 determines that the access is to a locked memory area and performs the access at that time. The system waits until the valid bit VR is turned off by unlock access. On the other hand, if the valid bit VR is off, the terminal 50-2.
Regardless of the presence or absence of the comparison output from 50-3, it is determined that the access is not to a locked memory area and the access is permitted.

Specifically, by calculating the logical sum of terminals 50-2 and 50-3 and the logical product of terminal 50-1 in FIG. 4, it is possible to determine whether or not access is permitted.

Note that in the above embodiment, the address width during continuous access is 4K.
Although the address width at the time of byte and distance access is set to 1 Mbyte, this maximum access value is arbitrarily determined by the operation code of the instruction, and an appropriate maximum access value can be determined as necessary.

Further, although the above embodiment has been exemplified by the case where two clusters are connected as processing units, the same applies to the case where two or more appropriate processing units are connected.

Furthermore, in the embodiment shown in FIG. 4, hardware is provided for comparing and determining lock addresses for each cluster.
By selectively inputting the start addresses from the clusters 10-1 and 10-2 to the adder 20-1 via a selector, it is possible to form one circuit section.

[Effects of the Invention] As described above, according to the present invention, lock address control is performed by comparing a lock address and an access address using a start address at the start of packet transfer, and the address is set according to the type of access. By comparing the address obtained by adding the width to the start address with the lock address together with the start address, comparison processing of all bits is not necessary, and it is possible to reduce the amount of hardware and simplify control.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is an overall configuration diagram of the present invention; Fig. 3 is a configuration diagram of the shared memory control section of the invention; FIG. 5 is an explanatory diagram of 32-bit address data of the present invention; FIG. 6 is an explanatory diagram of a lock address of the present invention. In the figure, 10-1.10-2: Processing unit (cluster) 12:
Shared memory control section 14: Shared memory section 16 Lock access control means (lock register circuit) 18: Lock address register means 20: Addition means 20-1.20-2: Adder 22: Selection means 22-1.22- 2: Selector 24-1.26-1: First comparison means 24-2.26-2: Second comparison means 24-11 to 26-22: Comparator 30-1.30-2: Data buffer 32-1 .32-2: Mover 34 Ni priority circuit section 36-1.36-2.4044-1.44-2: Transfer interface 38: Pipeline 42: Read buffer 48-1.48-2: OR gate 50- 1 to 50-3: Terminal

Claims (5)

[Claims] (1) A plurality of processing units (10-1, 10-2), a shared memory control unit (12), and a shared memory unit (14) are provided, and access information for the shared memory unit (14) includes a start address and data. The processing unit (10-1, 10-1) and the shared memory unit (14) have a length, an address interval, and a type of access, and are controlled by the shared memory control unit (12) by packet transfer.
), the lock access control means (16) provided in the shared memory control unit (12) includes a valid bit and a lock that are turned on by access with a lock from a specific processing unit. A lock address register means (18) storing a start address; When a non-locked access is received from another processing unit, a lock address register means (18) storing a start address; Adding means (20) for generating an addition address by adding a predetermined access address width (W1, W2); extracting a comparison target bit portion according to the type of access from the lock address register means (18) and starting the access; A first comparison means ((24-1, 24-2) for comparing with the address; extracts a comparison target bit part according to the type of access from the lock address register means (18) and adds it to the addition means (20). A second comparison means ((26-1, 26-2) and ~26-2) Only when a comparison output of address matching is obtained from either of
An address locking method that prohibits memory access by determining that the access is to a locked memory area. (2) The types of access mentioned above are continuous access, which accesses continuous memory areas determined by the data length from the start address, and distance access, which sequentially accesses distributed memory areas determined by the address interval and data length from the start address. 2. The address lock system according to claim 1, further comprising: an address lock system. (3) The lock address register means (18), the addition means (20), the selection means (22), the first comparison means (24)
-1, 24-2) and second comparison means (26-1, 26-
2) The lock address method according to claim 1, wherein a bit portion of the start address having a data width (W1, W2) or more corresponding to the type of access is handled as address data. (4) When the data width (W1) of the continuous address is 4K bytes and the data width (W2) of distance access is 1M byte, 19 bits from the most significant bit during continuous access.
4. The address lock system according to claim 3, wherein up to the bits are handled as address data, and during distance access, the most significant bit to 11 bits are handled as address data. (5) The permissible memory control section (12) includes a priority circuit section (34);
), when the valid bit of the lock register means (18) is off and accesses are received from multiple processing units at the same time, if both are accesses with locks, the unit with a predetermined high priority is accessed with locks. Prioritize access by turning on the valid bit of the lock address register means (18) and setting the lock start address, and if only one unit is accessing with lock, the access with lock is performed regardless of the priority. At the same time, the lock start address is set with priority given to the valid bit of the lock address register means (18).On the other hand, when an access is received while the valid bit of the lock address register means (18) is already on, the valid bit is turned off. 2. The address locking method according to claim 1, wherein the access is made to wait until the address is accessed.