JPH0465406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an information processing apparatus in which the structure of hardware or firmware is changed by control instructions added at the beginning or middle of a program.

Prior Art and Problems Conventionally, computers have been designed according to a predetermined hardware configuration or logic, apart from functional expansion. Therefore, when various programs are run, the performance of the computer changes greatly depending on the content of the programs. For example, there is a difference in performance between an office processing program that frequently accesses external memory and a science and technology program that uses many internal registers, depending on the structure of the computer used, such as whether more data registers or instruction registers are reserved. appears large.

For this reason, even if you try to design any program to improve its performance on a general-purpose computer, it is extremely difficult for the reasons mentioned above.
Conventionally, countermeasures have been considered, such as (1) system settings using configuration control, and (2) changing the internal logic of the hardware using OPSR (Operation Status Register), but the former is determined at the time of system installation. In the latter case, the operator mainly changes the OPSR, which places a heavy burden on the operator.
Also, when the program changes for both (TSS etc.)
There is no flexibility at all.

Purpose of the Invention In order to solve the above-mentioned problems, the present invention automatically changes the structure (configuration or logic) of hardware or formware so that the computer itself is suitable for software, that is, a collection of various instructions. It allows you to change it.

Structure of the Invention The present invention provides a memory including a plurality of access pipes, a memory including a plurality of banks, a memory including a plurality of banks in which a plurality of access timings are determined for each of the plurality of access pipes, and A mode in which each of the plurality of access pipes accesses the plurality of banks according to the timing so as not to overlap, and one access pipe among the plurality of access pipes accesses all or any of the timing points of the plurality of access timings. The present invention is characterized in that it has a change function for switching between modes for accessing all of the plurality of banks at the timing of , and the change function is activated by a control command, as shown in the drawings below. This will be explained in detail with reference to.

Embodiments of the Invention In a computer that aims to increase speed, such as a vector processor, multiple instructions and multiple external data processed by the instructions are buffered, and subsequent instructions in the program are changed depending on the state of the computer, etc. It may be executed before the preceding instruction (instruction overtaking). To this end, a plurality of commands and external data are loaded into an instruction holding unit (iR) and a data holding unit (DR), respectively, and the order and timing of issuing the commands is controlled.

As an example of this, a conventional vector instruction control device (Vlu) is shown in FIG. It is assumed that this command control device consists of a command fetching circuit 1 and a command issuing circuit 2, and two pieces of data (first and second) are input for one command. 3 sends instructions and data to external devices such as external memory and auxiliary processors. A buffer 4 in the instruction fetching circuit 1 buffers instructions and data from the external device 3. A flag control circuit 5 manages data. iR _0~3 are instruction registers
_AR0-3 are data address registers, _DRF is a first data register, _DRS is a second data register, and CL is a clock. Further, SEL is a selector circuit, 101 is a bus line that transmits instructions and data, 110 is an address line that indicates data to be processed by the iR ₀ instruction, 111 is a read (READ) address line for data register DR, and 112 is a command that is sent. This is an address line that indicates the storage location of data to be processed.

Information is sent from the external device 3 in the order of command, first data, and second data (repetition of this), and is held in the buffer 4. Information is taken out from buffer 4 in the same order, and clocks CL ₀ ,
When CL _DF and CL _DS are turned on in sequence, the instruction is set to the instruction register iR ₀ and the two data are set to the data registers _DRF and _DRS, respectively. Furthermore, when the clock CL ₀ is turned on, the flag control circuit 5 sends a signal to one of the addresses (0 to 3 in the illustrated example) of the data register DR whose flag (described later) is turned off. Set address register _AR0 through line 110. The contents of the address register AR ₀ then become the write (WRiTE) addresses of the data registers DRF _{and DRS} , respectively, when the clocks CL _DF and DL _DS are turned on (signal line 113). Command transmission circuit 2
Now, instruction registers iR1 to iR3
When one of the clocks becomes free, one of the clocks CL ₁ to CL ₃ turns on, and the corresponding instruction register and address register are respectively set.
Import the contents of iR ₀ and AR ₀ . Further, the arithmetic unit (described later) determines the command to be issued based on the context of the instructions, selects one of the registers iR ₁ to iR ₃ in response to the set signal sel, and transmits the command to the arithmetic unit. Simultaneously corresponding address register
One of AR ₁ to _{AR 3} is sent to the flag control circuit 5 through the signal line 112. The flag control circuit 5 transmits the sent address to the data register DR through the signal line 111, and sends two pieces of data 1st and 2nd to the arithmetic unit. The arithmetic unit receives the transmitted command and two pieces of data and processes them.

FIG. 2 is a detailed diagram of the flag control circuit 5.
212 corresponds to the signal lines 110/112 in FIG. 230 to 233 are the data registers in Figure 1.
This flag indicates whether the data at each address 0 to 3 of the DR is valid or invalid, and uses a set (S)/reset (R) type latch. SET FLAG is a signal that turns on at the same time as clock _CL0 in FIG. 1 turns on, and determines the timing at which flags 230 to 233 are set. START
iNSTRUCTioN is a signal sent from the command transmitting circuit 2 in FIG.
233 reset timing is determined. 222
A decoder decodes the address on the signal line 212 to indicate which address the flag belongs to, a select circuit 221 indicates a vacant address depending on the state of the flag, and an encoder 220 encodes the selected address. Note that the output ALL BUSY from the select circuit 221 is a signal indicating that data at all addresses are valid and no more data can be taken in. Also, RAR is signal line 2
This register latches the signal on signal line 211 (112 in FIG. 1) and sends it to the data register DR in FIG. 1.

Explain the operation. The select circuit 221 selects the address (the flag is in the reset state) of invalid data (data that has already been sent to the arithmetic unit) (giving priority to the smaller value), encodes it with the encoder 220, and then sends it to the signal line 210 ( It is transmitted to the address register _AR0 in FIG. 1 as a signal 110) in FIG. Each address of the data register DR and the flag 230 corresponding to each address
~233 is four in this example, so it is represented by two binary values, 230 is 00, 231 is 01, 23
2 is assigned 10, and 233 is assigned 11. The reset of these flags and the designation of a free address in the data register DR by these flags are also performed using these two binary values and two bits. For example flag 23
When only 0 is reset, the signal line 210 becomes 00, and the signal line 212 becomes 00, and the flag 230 is reset. Signal line 2
When the signal No. 10 is set in the register AR ₀ by turning on the clock CL ₀ , the corresponding address flag (any one of 230 to 233) is set at the same time.
Furthermore, when a command is transmitted by the command transmitting circuit 2,
The address on signal line 212 is sent along with START iNSTRuCTioN, and the corresponding flag is reset. The address is also latched in register RAR,
It is sent to the data register DR in FIG. 1 as a read address on the signal line 211, and the data to be processed by the issued command is read out and sent to the arithmetic unit. In addition to the above, when all flags 230 to 233 are set, ALL
BUSY signal turns on. This signal is sent to the control unit that controls the entire instruction fetching circuit 1, and prevents any further instructions from being loaded into the register _iR0 .

In conventional computers, register iR is fixed for instructions and register DR is fixed for data.
There is no mutual accommodation. However, scientific computers require a large number of data registers,
Office computers require a large number of instruction registers, and a design suitable for one will be inadequate for the other. Therefore, the present invention changes the hardware using control instructions.

Figure 3 shows an example of a partial configuration of an information processing device with a structure change function, as described above, in which the balance of the capacities of the information storage units such as the instruction register iR and the data register DR can be changed. Show what is possible. 1st
In the example shown, instruction registers iR ₀ to _{iR 3}
Both the number of data registers _DRF or _DRS are four (fixed), but many actual instructions do not use external data (for example, instructions that use only internal registers as operands), so The usage rate of data register DR differs depending on the software. Therefore, in this example, an auxiliary information holding unit SR is provided,
This can be used as both iR and DR. As is the case throughout all the figures, the same parts in FIG.
1 to 113. Data register _DRF ,
Both _DRSs have one stage reduced to three stages, and the output 32 is obtained by decoding the signal line 313 with the decoder 324.
7 (specifying addresses 0 to 2 of DR) selects the data register DR that sets the input data on the bus line 301. 300 is a structure change signal, and registers _SRF and _SRS are used as instruction and address registers _iR0 ' and _AR0 ', respectively (Fig. 4), or the fourth stage data register is used.
Select whether to use it as DR _F3 or DR _S3 (Figure 5).
That is, when the signal 300 is 1, the configuration is as shown in FIG. This is automatically achieved by switching selectors 320-323 with signal 300 in FIG. On the other hand, signal 300
When is 0, the configuration is as shown in FIG. This is realized by reversing the states of selectors 320-323 from those shown in FIG. 328 is the output of the decoder 324, and is a signal indicating that data register 3 3, ie, _DRF3 and _DRS3, is selected.
Note that 331 and 332 are clocks CL ₀ , CL _DF , CL _DS
This is a switching gate.

In the above example, for the registers iR ₀ and AR ₀ of _the instruction capture circuit 1 shown in FIG.
Although AR ₀ ' is added, the registers in the instruction issuing circuit 2 may be configured in four stages such as iR ₀ to iR ₄ and AR ₁ to _{AR 4} . In either case, the registers _SRF and _SRS that can be used for data are used, so that a portion of the address register AR is unused, as shown by diagonal lines in FIG.

When adopting the configuration shown in FIG. 4, the flag control circuit 5 shown in FIG. 2 must also be changed (because the number of data registers DR is reduced to three). FIG. 6 shows the modified functional part for this purpose. In the same figure, 62
1 and 633 correspond to 221 and 233 in FIG. 2, respectively. 640 is an additional OR gate. 600 is the same structure change signal as 300 in FIG. 3; when this is 1, the output of the OR gate 640 is always 1, and the flags 230 to
233 are all set, which is equivalent to a state where all three data registers DR are filled with data, and the +ALL BUSY signal becomes 1.

Although the above embodiment has shown an example in which the register configuration of the hardware is automatically changed (depending on the nature of the software will be described later), the hardware to be changed is not limited to this. 7th
The following figure is an example of application to control change of a vector access control device.

In a computer that processes multiple data (vector data) at high speed, it is desirable to use only internal registers (VR) to execute arithmetic instructions, etc., without using the main memory (MEM) as much as possible. This internal register VR, also called a vector register, consists of one or more elements, and each element holds one piece of data. Generally, elements are processed in order starting from element 0, and the results are written to other VRs.
For this purpose, the more VRs the better. Multiple VR
The set of is called a vector register group (VRG), but due to limitations in the capacity of the VRG or the nature of the software, data must be transferred at a certain frequency between the MEM and the VRG.
The memory access control device (VSu) is configured to include, for example, a plurality of access control units (hereinafter referred to as access pipes or simply pipes) to efficiently control the above data transfer.

Figure 7 is a block diagram of the entire information processing device equipped with the function of processing vector data at high speed, where 11 is the main memory (MEM), 12 is the memory control unit (MCu), and 13 is a system that processes scalar data with one element. 14 is a channel device (CHP), and 15 is an external input/output device (I/O). Inside the broken line frame 16 is a vector data processing unit (Vu: vector unit), which includes a vector register group (VRG) 17, a memory access control unit (VSU) 18, and an instruction control unit (VIu) 19 shown in the previous example. and a computing device (VEu) 20. The VRG 17 is composed of a plurality of vector registers VR as described above, and the arithmetic unit 20 executes various arithmetic instructions using VR as an operand. This arithmetic device 20 includes an ADD adder 20A for addition, a MuLTi arithmetic machine 20B for multiplication, and a DiViDE arithmetic machine 20C for division. The aforementioned command control device 9 controls the transmission of commands to the memory access control device 18 and the arithmetic unit 20. In the diagram, IT is command transmission, D is data, and I
indicates the flow of instructions.

FIG. 8 shows an example of the configuration of the VRG 17. This VRG
17 uses, for example, a RAM with an access time of 1τ (Vu clock cycle) or less, and has an interleaved configuration. The same numbered elements of each register VR ₀ to VR ₂₅₅ that make up the fast VRG are grouped together as a bank, and this bank consists of 8 elements.
One VRG is configured, and the access timings from the plurality of access control units in the VSu are made different (shifted) for each bank. With this interleaved configuration, multiple pipes (access control units) can simultaneously access the same VRG.
can be accessed without having to interact with the
FIG. 9 is an explanatory diagram of this (described later).

Although the number of elements in each vector register VR ₀ , VR _{1 .} . . may be variable, it is basically set to 8 for simplicity. The number of actually valid elements is given by the vector length VL. The number of VRs that make up one VRG is 256, and is specified by an 8-bit address. Regarding element allocation, when there is one VRG, element n is made to correspond to bank n. In FIG. 8, E is an element, and the numbers therein are element numbers.

The instruction control device 19 in FIG. 7 includes a vector length register VLR, in which the value of VL is set by a control instruction. This VL indicates the number of valid elements. The memory access control unit (VSu) 18 stores the number of data indicated by VL.
Transfer between MEM11 and VRG17. Further, the arithmetic unit 20 processes the number of data indicated by VL using the same instruction.

Figure 9 is a time chart of the bank timing that defines the timing for accessing the first element (element number 0) of the vector register VR for each access source (pipe, arithmetic unit).
Eight timings of K, E ₁ , E ₂ , E ₃ , L, F ₁ , F ₂ , and F ₃ are cyclically repeated. Of these, K and L are for pipes, E ₁ to F ₁ , E ₂ to F ₂ ,
E ₃ to F ₃ are for the arithmetic unit, and each corresponds to the instruction word R.
Access the VR specified by the 1, R2, and R3 parts. One instruction word consists of a 1-byte (8-bit) operation code section (OP) followed by three vector operation sections R1, R2, and R3 (1 byte each), generally denoted by R2 and R3.
The operation indicated by OP is executed for each element of the same number on the vector data of VR, and the result is written to the element of the same number of VR indicated by R1.

FIG. 10 shows, as another example of a partial configuration of an information processing device having a structure change function, a control change function when one VRG is handled by a two-pipe memory access control device. In the same figure, 1000A and 1000B (hereinafter A and B are omitted) are framed by broken lines.
are two pipes (access control units), and when a control circuit and the like are added to these, the memory access control unit (VSu) 8 shown in FIG. 7 is obtained. 1010 (subscripts A and B are omitted as appropriate for simplicity, the same applies to other items)
is a bidirectional bus, which transfers bidirectional data input/output to the memory control unit (MCU) 12 by switching gates. 1001 is a fetch data register (FDR) that holds fetch data from MCU 12; 1002 is a store data register (SDR) that holds store data to MCU 2;
003 is an align circuit (ALiGN) for rearranging data strings, 1004 is an align register stack (ARS), and 1020 is a vector register group.

The configuration up to this point is similar to the previously proposed configuration.
First, to explain its operation, (1) In the case of a data fetch instruction, the command is sent via the bidirectional bus 1010.
Data for each four elements sent from the MCU 12 enters the register 1001, and the align circuit 10
After being rearranged in the correct order of elements through 03, they are held in a stack 1004. stack 1
The data held in 004 is retrieved in a FiFo (first-in, first-out) manner, and when bank time is obtained, VRG1 is stored for each element.
It is written to the corresponding VR of 020. (2) In the case of a data store instruction, data is read out from the VR element by element when bank time is available and held in the stack 1004. Then, the data held in the stack 1004 is taken out in the FiFo style and passed through the alignment circuit 1003 to the memory 1004.
1 (FIG. 7), enters register 1002, and is sent to MCU 12 via bidirectional bus 1010.

In this example, gate logic (GL) 1005A, 1005B is added to each pipe 1000A, 1000B, and this is controlled by a structure change signal 1030. Gate logic 1005 consists of a group of gates that control whether or not input data is transmitted to the output side.
When the structure change signal 1030 is 0, the gate is closed, and when it is 1, the gate is open. Below, the signal 1
When 030 is 0, it is called 1-pipe mode, and when it is 1, it is called 2-pipe mode, and the operation of each mode will be explained.

1 pipe mode: At this time, gate logic 1
005A and 1005B are closed, stack 1004A (ARS A) is connected only to banks 0 to 3 of VRG 1020, and stack 1004A (ARS A) is connected only to banks 0 to 3 of VRG 1020.
B (ARS B) is connected only to banks 4 to 7 of VRG 1020. In this case pipe 1000
A and 1000B can execute the same instruction simultaneously.
In other words, in FIG. 9, pipes 1000A, 10
Both 00B are either K or L (one is a solid line,
The other one starts accessing VR at the same time as the dashed line). Since there are two access timings, the time required to wait for instruction timing is considerably shorter than in the two-pipe mode. The pipe 1000A handles elements 0 to 3, and the pipe 1000B handles elements 4 to 7, and writes or reads data there. The start of VR access indicates the start of access from the first bank, so there is a risk of conflict if these are the same, but VR
If divided into two groups of 7, the access start bank is 0.
and 4, and from now on one is 1, 2, 3, 0, 1,
..., the other goes 5, 6, 7, 4, 5, etc., so they never collide.

2 pipe mode: At this time, gate logic 1
Since 005A and 1005B open, stacker 10
04A and 1004B are both connected to banks 0 to 7 of VRG 1020. In this case, as shown by the solid line in FIG.
Set the bank times to be different for B (one is K and the other is L) to prevent pipes 1000A and 1000B from accessing (colliding) the same bank of VRG 1020 at the same time, and then operate both pipes independently. Execute two instructions at the same time if possible.

The advantages and disadvantages of each mode described above are as follows. In 1-pipe mode, only one instruction can be executed, but it only takes 4τ to access VR from elements 0 to 7. On the other hand, in 2-pipe mode, two instructions can be executed at the same time, but it takes 8τ to access VR from elements 0 to 7. Therefore, if the frequency of memory access instructions is high, the 2-pipe mode is more effective because it allows two instructions to be executed at the same time, and if the frequency of memory access instructions is low, the 1-pipe mode doubles the amount of data transferred. So it will be advantageous.

Two examples of changing the structure of hardware using a structure change signal have been described above.Next, a control command execution section that generates this structure change signal in response to a special control command will be described. FIG. 11 is an example. The control instruction execution section of this example is formed as an addition to the instruction control device shown in FIG. In other words, 1100 and 1101 in FIG. 11 correspond to the instruction fetching circuit 1 and the instruction issuing circuit 2 in FIG. 1, respectively, and these constitute an instruction control device. In the conventional instruction control device, the normal instruction selected by the instruction issuing circuit 1101 and the data output from the data register DR are sent to the arithmetic unit in the same way as in FIG.
In this example, special control commands (described later) are sent to the control command execution unit.

In other words, 1110 is the instruction capture circuit 1100
A circuit for decoding that the instruction sent through the signal line 1102 at the timing when the instruction from the buffer is set in the register _iR0 is a control instruction for structure change according to the present invention;
120 is a signal line 11 from the command transmission circuit 1101
A register ( _iRE ) 1130 is a decoder that decodes the instructions set in the register _iRE and outputs a signal corresponding to each instruction. 1181-11
8n is a latch in which a value determined by a control command for structure change according to the present invention is set, and its outputs (structure change signals) 1191 to 119 are structure change signal lines of a determined structure change function, respectively; For example, it is connected to 300 in FIG. 3, 600 in FIG. 6, 1030 in FIG. 10, etc.

Next, the operations of various control commands will be explained using examples. FIG. 12 shows examples of command words of three types of control commands according to the present invention. The CD instruction (Change Di
-rect instruction) is an 8-bit instruction code OP (Opera
The CR instruction (Change by Register instruction) in b has an additional 8-bit register specification section (R section), and the CB instruction (Change by Bit instruction) in c has a multi-bit register specification section. (for example
A bit pattern section (section B) of 24 bits) is added to each bit pattern section (section B).

The CD command in a is given in the form of CDONX or CDOFX, and the former turns function X on (ON).
The latter also specifies that function X is turned off (OF). Then, if the function
double CDONA, CDOFA, CDONB, CDOFB,…
will be prepared. In other words, this CD instruction, as its name suggests, directly specifies the function to be changed.

On the other hand, the CR instruction b specifies the address of a certain register in the R part and changes the structure according to the contents of that register. In the CB instruction of c, each bit in the B part specifies a structure change with 1 or 0 for the structure change function. Therefore, if part B is 24 bits, structural changes of up to 24 functions can be specified at the same time. Although other forms of similar structure change commands are possible, they are omitted here.

Figure 13 shows the structure change instruction decoder 1 in Figure 11.
In the detailed diagram of 130, the area within a broken line frame 1301 corresponds to the decoder 1130. 1300 corresponds to the register ( _iRE ) 1120 in FIG. This register contains only the OP part in the case of the CD instruction, and the CR
Valid data is set in the OP and X portions in the case of an instruction, and in the OP and X, Y, and Z portions in the case of a CB instruction. Signal line 1351 in decoder 1301
135n correspond to each signal line 1171 to 117n constituting the signal line group 1142 in FIG.
Corresponds to ~113n.

1320 decodes the instruction code transmitted by signal line 1302 and sets the corresponding output signal to 1 only for the instruction shown in FIG. That is, the signal lines 1321N to 132nN are each
It becomes 1 when CDONA, CDONB, ..., and the signal lines 1321F to 132nF are CDOFA, respectively.
CDOFB, becomes 1 when... On the other hand, signal line 13
30 becomes 1 when there is a CR command, and signal line 13
31 becomes 1 for the CB instruction. Signal line 1310
conveys the B part of the CB instruction, and each bit 1311 to 1
The signal line 1331 passes through the gate every 31n.
, they are output to signal lines 1341 to 134n, respectively.

1351 to 135n correspond to clock enable signals 1181 to 118n in FIG. 11, and START signals sent from the command generation control circuit.
When the iNSTRUCTioN signal comes, all signals become 1 in the CR and CB instructions, and only the signal specified by the CD instruction becomes 1 in the CD instruction. Also, in the case of CD command, signal lines 1341 to 134n are used for CDON.
Among them, only the determined signal becomes 1, and in the case of CDOF, the signal becomes 0.

Returning to FIG. 11 again, at the same time that the CD, CR, and CB instructions are set from the buffer in the instruction fetching circuit 1100 to the register _iR0 , the serialization control circuit 1113 is activated. This serialization control circuit 1113 prohibits the execution of subsequent instructions (clockwise) until all instructions held in the instruction register (iR) in FIG.
(do not turn on L ₀ ), control ends when all registers iR are free. Also, during this period, the instructions held in register iR are executed in the order as programmed. The above operation is called instruction serialization. Therefore, the last instruction executed during serialization processing is the structure change instruction of the present invention. This instruction is executed (START iNST−
When RUCTioN arrives, all previous instructions have been completed, making it possible to change the structure of the hardware or firmware.

When the CD instruction is executed, signal line 1 in Figure 11
The signal determined by the instruction among 131 to 113n becomes 1 when it is CDON, and 0 when it is CDOF (for example, 1131 becomes 1 in CDONA,
In CDOF B, 1132 becomes 0). At the same time, the value of the signal line 1140 is 0, and the value of the signal line 1141 is 1, so the signal lines 1131 to 11
The value of 3n is transmitted as is to signal lines 1161 to 116n. Also, among the signal lines 1171 to 117n, only the signal determined by the command becomes 1 (for example, in CDONA and CDOFA, only 1171 is 1), so among the latches 1181 to 118n, only the latch connected to the function to be changed by the command becomes 1. The value is set to .

When the CR instruction is executed, the data in the external register (located in the external device 3 in FIG. 1) specified by the R section is read in advance and written to the data register DR. Next, START
When iNST-RUCTioN arrives, the value of the signal line 1140 is 1, the value of the signal line 1141 is 0, and the values of the signal lines 1171 to 117n are all 1.
Therefore, the values of each bit 1151-115n of data 1104 read from data register DR are set in latches 1181-118n, respectively. In order to execute this instruction, it is necessary to write in advance data defining the value of the bit corresponding to the function to be changed into the register designated by the R section.

When the CB instruction is executed, signal line 1 in Figure 11
The bit pattern of the bit pattern portion B appears as it is in 131 to 113n. At this time, the signal line 1140 becomes 0, the signal line 1141 becomes 1, and the signal lines 1171-117n all become 1, so the value of B is set in the latches 1181-118n as is.

Note that the value of n shown in FIGS. 11 and 13 only needs to be the same as the number of structural change functions. Furthermore, in the CD instruction, although the case where one structure is changed with one instruction has been described, it is also possible to change a plurality of structures with one instruction. Similarly, in the CR and CB instructions, one bit may be used to change multiple structures.

Effects of the Invention As described above, the present invention is very advantageous for programmers and the like when creating software.
This is because by inserting the structure change instruction according to the present invention into the software, it is possible to change the structure of the computer to the most suitable structure for the software.
However, the following two points need to be kept in mind. ()
In order to effectively utilize the present invention, a programmer must have some knowledge of the hardware or firmware to which the structure is to be modified. () When the instructions according to the present invention are executed,
This results in time loss.

Countermeasures for the above two points are described below. ()
This is not a problem for OSs (operating systems) because programmers who create them already have some knowledge of hardware. For other general users, it can be used by programmers with a certain level of knowledge who want to make their software even faster.
Regarding (), frequent use of the instructions according to the present invention will lead to a decrease in performance as a whole, so in order for the benefits of changing the structure to be greater than the loss caused by executing the instructions, the frequency of the instructions should be reduced. There is a need to.

However, for example, in scientific and technical computers that aim to increase speed, the frequency of structural changes may be low, so the loss is extremely small. Furthermore, the execution time of the instructions of the present invention is very small compared to vector instructions that process a large amount of data in one instruction, so the loss in parentheses does not pose a problem. Also, even in general-purpose machines, when the program is changed, for example when using TSS, the time loss for this is quite large, so if the instructions of the present invention are executed at that point, the loss in () can be ignored. It will be as small as possible.

As described above, by effectively utilizing the present invention, the above-mentioned great merits can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional instruction control device without a structure change function, Fig. 2 is a detailed diagram of its flag control circuit, and Fig. 3 is a diagram showing an example of a conventional instruction control device that does not have a structure change function. FIG. 4 and FIG. 5 are explanatory diagrams showing the structural changes of the main parts thereof, and FIG. 6 is a main part structure diagram showing the added parts to the flag control circuit due to the structural changes in FIG. 4. FIG. 7 is a schematic configuration diagram of the entire information processing device that processes multiple data at high speed, FIG. 8 is an explanatory diagram of a vector register group provided in the vector data processing device, and FIG. 9 is an illustration of access to the register group. A time chart showing the timing, FIG. 10 is a block diagram of a part of the memory access control device provided in the vector data processing device that can be structurally changed, and FIG. 11 shows various structure change signals by decoding structure change commands. FIG. 12 is an explanatory diagram showing examples of control instructions (structural change instructions) of the present invention, and FIG. 13 is a detailed diagram of a structure change instruction decoder. In the drawing, OP is the instruction code part of the control command, R is the part that specifies the register, and B is the bit pattern part.

Claims (1)

[Scope of Claims] 1. A memory comprising a plurality of access pipes; a memory comprising a plurality of banks; a memory comprising a plurality of banks in which a plurality of access timings are determined for each of the plurality of access pipes for the plurality of banks; A mode in which each of the plurality of access pipes accesses the plurality of banks according to the timing without overlapping, and one access pipe among the plurality of access pipes accesses all or any of the timing points of the plurality of access timings. An information processing device comprising: a change function for switching between a mode for accessing all of the plurality of banks at a timing of , and the change function is activated by a control command. 2. The information processing device according to claim 1, wherein the control command activates one or more structure change functions directly or in its command code section. 3. The control instruction has a part that specifies a register,
An information processing apparatus according to claims 1 and 2, characterized in that a structure change function is activated according to the contents of the register. 4. Claims 1 to 4, characterized in that the control command has a bit part that activates one or more structural change functions, and any bit activates only the corresponding structure change function. The information processing device according to item 3.