JPH0465400U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram of the present invention, Figures 2 and 3 are flowcharts showing the processing of the microcomputer, Figure 4 is an explanatory diagram of the operation key arrangement of the present invention, and Figure 5 is the conventional operation key. Explanatory diagram of the array,
Fig. 6 is an explanatory diagram of the display, Fig. 7 is an explanatory diagram of early reflected sound and reverberant sound, Fig. 8 is an internal configuration diagram of the DSP,
FIG. 9 is a detailed diagram of the initial delay section, FIG. 10 is a detailed diagram of the early reflected sound generation section, FIG. 11 is a detailed diagram of the reverberation sound generation section, and FIG. 12 is an explanatory diagram of the operation of the reverberation sound generation section. . In the figure, 10 is a digital signal processor DSP, 20
is a microcomputer, 30 is a group of operation keys, F
UNC is a function key, UP (+) is an up key, DOWN (-) is a down key, 40 is a display, 50 is an A/D converter, 60 is a D/A converter, and 70 is a speaker.

Claims (1)

[Claims for Utility Model Registration] A digital signal processor 10 that performs sound field correction on a digitized audio signal; a microcomputer 20 that provides various correction coefficients to the processor; and a microcomputer 20 that provides various instructions to the microcomputer. a display 40 whose display is controlled by the microcomputer; Function key FUNC cyclically selects each adjustment item of delay time LRT and initial delay time ERT of early reflection sound, UP key UP increases the level or time of each adjustment item, and decreases the level or time of each adjustment item. A sound field control device comprising: a DOWN key DOWN, and the display is controlled to display items and current values that can be adjusted by the UP key or the DOWN key.