JPH0464032B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a test signal generation method using a logic gate circuit in which the delay time of an output signal with respect to an input signal is adjustable.

Prior Art and Problems Integrated circuit testers (IC testers) are equipped with a large number of output signal pins, and various signals are applied to the integrated circuit through these pins to check the output status.
In this case, it may be desirable to apply the various signals mentioned above at exactly the same timing, but the configuration of each circuit that generates the various signals is different, and the number of gates included is different, so it is on the order of nanoseconds (ns). However, there are variations in the timing of generation of these various signals.

Purpose of the Invention The present invention provides a logic gate circuit that outputs various signals, by adding a fine adjustment circuit for varying the delay time of the output signal with respect to the input signal, that is, the signal propagation delay time Tpd, and adjusting the fine adjustment circuit. By doing this, the output timing is changed so that each logic gate can output at the same timing.

Structure of the Invention The present invention includes a group of input gates connected to a plurality of input terminal pins, a group of internal gates connected to the input gate group and generating a test signal, and a plurality of output terminals connected to the output terminal pin. , an input terminal connected to the internal gate; one base connected to the input terminal receiving a signal from the internal gate; a pair of emitter-coupled transistors; and a first transistor connected to the emitter side. a gate circuit having a current source transistor; an output stage emitter follower transistor whose base receives the output of the gate circuit and whose emitter is connected to a second constant current source and the output terminal; and the emitter follower transistor. an output gate group having a variable base capacitance transistor connected to the base of the transistor; and a third constant current source connected to the variable base capacitance transistor; A counter that measures the time difference between the output signal output from the output terminal pin is connected between the input terminal pin and the output terminal pin, and the additional delay time required to make the time difference the same for all output signals. is determined by an arithmetic circuit, and a control voltage corresponding to the additional delay time is applied to the bases of the second and third constant current source transistors,
After controlling the constant current value flowing through the second constant current transistor and controlling the base capacitance of the variable base capacitance transistor, and connecting the input terminal pin and the output terminal pin to the chip, the output terminal pin is controlled. The present invention is characterized in that it is possible to control the signal delay to a constant value, and this will be described in detail below with reference to embodiments.

Embodiment of the Invention FIG. 1 shows a logic gate circuit used in the present invention, Q1 and Q2 are emitter-coupled transistors, Q3 is a transistor serving as a constant current source, and R1 to R
3 is a resistor, and these constitute an ECL (emitter pull logic) circuit. Q4 is a transistor used as an emitter follower, Q8 is a transistor constituting a constant current source, and R4 is a resistor. Q8 and R4 serve as a load resistance of the emitter follower transistor Q4. Vi is the input voltage to the logic gate circuit composed of these, Vr is the reference voltage,
Vo is the output voltage, and Vs is the voltage that determines the constant current value. The reference voltage Vr is a threshold value for H (high) and L (low) of the input voltage Vi, and when Vi is higher than Vr,
If so, transistor Q1 on, Q2 off, output
Vo becomes H, and if Vi is L lower than Vr, Q1 is off, Q2 is on, and Vo is L.

In this circuit, the output voltage Vo is delayed by a certain amount of time with respect to the input voltage Vi, but the delay time is constant depending on the current value. In this circuit, in order to make this adjustable, an emitter follower circuit that functions as a load capacitance consisting of transistors Q5 to Q7, Q9 and a resistor R5 is connected in parallel to the emitter follower circuit of the output stage, and the control voltage Vc applied to the terminal T is used to adjust the emitter follower circuit. Controls the current value flowing into the load circuit. Transistor Q5
~Q7 are connected in parallel, and their bases are connected together with the base of transistor Q4 to the output end of the ECL circuit. This means that the base capacitances of the transistors Q5 to Q7 are connected to the output terminal of the ECL circuit, and the delay time Tpd increases. Also, the base capacitance of transistors Q5 to Q7 varies depending on the value of the current flowing through each transistor.
9 adjusts the current value flowing through the transistors Q5 to Q7 by the control voltage Vc, so the transistor Q
The base capacitances of transistors 5 to Q7 are controlled by the control voltage Vc, and thus the delay time Tpd can be adjusted by the control voltage Vc. In addition, in this circuit, the control voltage Vc is also applied to the base of the transistor Q8, so
The current value of the output stage is also adjusted by the control voltage Vc,
This also adjusts the delay time Tpd.

Transistors Q8 and Q by increasing the control voltage Vc
When the current of 9 is increased, the operation of the emitter follower circuit becomes faster and the delay time Tpd becomes smaller. On the contrary, by lowering the control voltage Vc, the transistor Q8,
When the current of Q9 is reduced, the operation of the emitter follower circuit becomes slower and the delay time becomes longer. FIG. 2 shows the relationship between control voltage Vc and signal propagation delay time Tpd. The horizontal axis of this figure is the control voltage Vc (V), the vertical axis is the signal propagation delay time Tpd (nS), and the dotted curve C2
is the delay characteristic when the transistor Q8 is used alone without the load circuits Q5 to Q7, Q9, and the curve C1 is the overall delay characteristic when the load circuit is added. As the number of transistors Q5, Q6, . . . increases, the load capacitance increases accordingly, and thus the delay time Tpd increases. In this circuit, the control voltage Vc is commonly applied to the transistor Q8 of the output stage emitter follower circuit and the transistor Q9 of the load circuit, but if the control voltage Vc is applied independently to the transistors Q8 and Q9, even more precise adjustment can be achieved. can be done.

Furthermore, by adding load circuits Q5 to Q7 as shown in FIG. 2, the range of the delay time Tpd that can be changed by the control voltage Vc becomes larger, and more accurate adjustment can be performed.

As another embodiment, the delay time Tpd can also be adjusted by controlling the voltage Vs applied to the terminal _T2 connected to the base of the constant current transistor Q3 of the ECL circuit including the transistors Q1 and Q2. That is, when Vs is made large, the ECL circuit operates at high speed and the delay time Tpd becomes small, while when Vs is made small, the ECL circuit operates at low speed and the delay time Tpd becomes large.

Therefore, Tpd can be changed even if the voltage Vc to terminal T ₁ is controlled or the voltage Vs to terminal T ₂ is controlled, and both can be controlled simultaneously, only one, or both independently. is possible.

FIG. 3 shows another logic gate circuit used in the present invention, in which the same parts as in FIG. 1 are given the same reference numerals. Transistors Q41 and Q81 and resistor R41,
Transistors Q42 and Q82 and resistor R42, transistors Q43 and Q83 and Q43 each constitute an emitter follower, and transistors Q81 to Q8
3 becomes their constant current source. That is, the emitter follower in FIG. 1 is composed of three stages of cascade-connected emitter followers in FIG.
Receives Vc.

In this circuit, if you increase the control voltage Vc and increase the current value of transistors Q3, Q81 to Q83,
The operating speed of both the ECL circuit and the emitter follower circuit increases, and the delay time Tpd decreases. When the control voltage Vc is lowered, the opposite operation occurs.
Figure 4 shows the delay characteristics of this circuit. Solid curve C1
shows the delay characteristics of the entire circuit, and the dotted curve C2 shows the delay characteristics when only the ECL circuit is controlled by Vc.

This is better than simply controlling the base potential of the constant current transistor Q3 of the ECL circuit with Vc.
Emitter follower constant current transistor Q81~
This shows that if Q83 is also controlled at the same time, the delay time Tpd can be made larger than if the control voltage Vc is similarly lowered. moreover,
The use of a multi-stage emitter follower also increases the overall delay time Tpd, indicating that Tpd can be adjusted with higher precision by controlling Vc. Of course, in this embodiment as well, only one or both of the transistor Q3 and the transistors Q81 to Q83 may be controlled independently.

FIG. 5 shows an IC tester implementing the method of the invention. Reference numeral 10 designates a generation unit for various test signals, 12 a group of input terminal pins thereof, 14 a group of output terminal pins, and 16 a group of control terminal pins. G1 is input gate group, G
2 is an internal gate group, G3 is an output gate group, and the circuit of the present invention is applied to the output gate group G3. The circuit of the present invention shown in FIG. 1 or 3 is provided as many as the number of output terminal pins. Reference numeral 20 denotes a control unit that includes a counter that measures the time difference between the input and output signals, thus Tpd, for each input and output terminal pin, and calculates the additional delay time necessary to make the delay time Tpd the same for all output pins, and calculates the additional delay time required to make the delay time Tpd the same for all output pins. A control circuit CNT that includes an arithmetic circuit and a table that outputs the control voltage Vc for the additional delay time, a memory MEM in which the control voltage Vc (digital value) for each output terminal pin is written, and each terminal pin read from the memory. Digital-to-analog converter DAC that converts the control voltage (digital value) into analog voltage
Equipped with. The number of DACs is equal to the number of output terminal pins,
A register is provided on the input side, memory read data is set in the register, and a control voltage Vc for each terminal pin is output to each DAC during an IC test. Of course, a generation circuit for the specified control voltage Vc is provided on each terminal pin side, that is, in the circuits shown in FIGS. 1 and 3, so that there is only one DAC in FIG. 5, and the DAC is made to output the Vc of each terminal pin. , the Vc may be outputted to each of the voltage generating circuits described above. Assuming that the delay of the output stage gate circuit in Figs. 1 and 3 is constant,
The above-mentioned measurement of Tpd, determination of Vc, etc. need only be performed once, and in this way, various test voltages can be accurately output all at once from this IC tester.

The test signal generation section 10 and the control section 20 are one
They can be assembled into LSIs or individual ICs. Control voltage Vc when combined into individual ICs
The terminal T receiving the signal becomes the outer terminal pin of the IC of the test signal generating section.

Effects of the Invention As explained above, in the present invention, since a circuit for adjusting the signal propagation delay time Tpd is added to the logic gate circuit, the gate circuit can be used in the output stage to simultaneously output each signal, which is extremely effective. It is.

[Brief explanation of the drawing]

Figures 1 and 3 are circuit diagrams of logic gates used in the present invention, Figures 2 and 4 are graphs showing operating characteristics, and Figure 5 is a block diagram showing an IC tester implementing the method of the present invention. . In the drawing, Q1 and Q2 are a pair of transistors that constitute ECL, Q3, Q8, Q9, and Q81 to Q8.
3 is a constant current source transistor, MEM, CNT,
DAC is a delay time adjustment circuit that outputs a control voltage.

Claims (1)

[Claims] 1. An input gate group G1 connected to a plurality of input terminal pins; an internal gate group G2 connected to the input gate group and generating a test signal; and a plurality of output terminals connected to the output terminal pins. a pair of emitter-coupled transistors, one base of which is connected to an input terminal that receives a signal from the internal gate; and a first transistor connected to the emitter side of the transistor. a gate circuit having a constant current source transistor; an output stage emitter follower transistor whose base receives the output of the gate circuit and whose emitter is connected to the second constant current source transistor and the output terminal; an output gate group G3 having a variable base capacitance transistor connected to the base of the ivy follower transistor and a third constant current source transistor connected to the variable base capacitance transistor; A counter that measures the time difference between the applied input signal and the output signal output from the output terminal pin is connected between the input terminal pin and the output terminal pin, and the time difference is made the same for all output signals. A necessary additional delay time is determined by an arithmetic circuit, a control voltage corresponding to the additional delay time is applied to the bases of the second and third constant current source transistors, and a constant current flowing through the second constant current source transistor is determined. Controls the current value,
and controlling the base capacitance of the variable base capacitance transistor, making it possible to control the delay of the output signal of the output terminal pin to a constant value after the input terminal pin and the output terminal pin are connected to the chip. test signal generation method.