JPH0463372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus that uses an array of integral light receiving elements to extract a constant level of contrast output even when subject brightness changes, and automatically performs focus detection.

BACKGROUND ART Many applications have been filed and products have been made for devices that perform focus detection using a contrast method, triangulation method, etc., using a conventional MOS type photodetector array or an integral type photodetector array such as a CCD. By the way, if the output of the integral type light receiving element is V, then C is a constant determined by the shape and sensitivity, L is the average illuminance of the irradiated light, and T is the time during which the light with the illuminance L is irradiated, V=C It is given by the formula ×L×T. In the conventional method of obtaining a constant light integrated voltage V, the change in brightness L of the subject is
A constant output was obtained by changing the integration time T. By the way, in this method, when the subject brightness decreases by half, the integration time inevitably doubles, and especially in the case of low brightness, this integration time becomes extremely long. This caused inconvenience in use due to the response speed of the device and the effects of camera shake. Also, if the integration time is limited to a certain time,
This method has the disadvantage that the optical integrated voltage decreases and focus detection cannot be performed.

The present invention is intended to overcome the above-mentioned disadvantages, and its purpose is to provide focus detection that has a fast response speed even at low volatility and is less affected by camera shake, and to provide focus detection at low brightness. It is about improving one's abilities.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Focus detection of the present invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

First, the basic configuration of the focus detection according to the present invention will be described in the first section.
This will be explained with reference to the figures. FIG. 1 shows the basic configuration of the focus detection according to the present invention as a circuit block diagram. The drive circuit 100 is connected to the integrating type light receiving element array 200, outputs an integration start pulse and a drive pulse, and also outputs a monitor diode 50.
0, a reference time generation circuit 800, and a clock circuit, and output an integration start pulse. The integrating type light receiving element array 200 includes an integration end control circuit 900 and an amplifier 3.
00, inputs an integration end signal to end the integration, and outputs the output to the amplifier 300. The amplifier 300 performs amplification using an externally settable amplification factor and outputs a constant level optical integrated voltage to the focus detection circuit 400. The focus detection circuit 400 performs focus detection processing using the input voltage from the amplifier 300. The monitor diode 500 is a comparison circuit 600
is connected to outputs an optically integrated voltage for monitoring.
On the other hand, a brightness modulation level generation circuit 700 as a reference value transformation circuit is also connected to the comparison circuit 600 and outputs a brightness modulation level as a reference value set from the outside. The comparison circuit 600 is the integration end control circuit 9
00 and the clock circuit 1000, and compares the output of the monitor diode 500 with the output of the brightness modulation level generation circuit 700 and outputs an output. The reference time generation circuit 800 is connected to the integration end control circuit 900 and outputs a signal when the integration time reaches a certain set time. The integration end control circuit 900 outputs an integration end signal to the integrating type light-receiving element array 900 when either the comparator circuit 600 or the reference time generating circuit 800 outputs an output. The clock circuit 1000 measures the time from the integration start pulse of the drive circuit 100 until the integration end signal of the comparator circuit 600 is output. A controller 1100, which has a function as a control means, is connected to each part and performs integration time adjustment, amplification factor adjustment, brightness modulation level adjustment, and timing management.

Next, the functions of the basic structure of the present invention constructed as described above will be explained with reference to FIG. In FIG. 2, the x-axis shows the integration time of the monitor diode 500, and the y-axis shows the output of the monitor diode 500 or the brightness modulation level of the brightness modulation level generation circuit 700. The greater the slope of the line, the brighter it is.
The smaller the brightness, the darker it is, and the monitor diode 500 performs integration with a slope corresponding to the brightness, and ends the integration when the set brightness modulation level is reached. Thick solid line parts 1-3, 4-7, 8 in the diagram
~11,12~15,16~19,20~23,
. . . is a series of possible integration end points of the monitor diode 500 when the focus detection of the present invention is operated, and is a collection of straight line portions corresponding to the brightness modulation level. Furthermore, the dotted line portion in the figure shows the transition of the integration end point when the brightness modulation level changes by one step for the same brightness integration. Furthermore, for brightness modulation levels 1, 1/2, 1/4, . . ., amplification factors 1, 2, 4, . . . to obtain a constant output, and constant outputs 1, 1, 1, . . . ... is shown on the right side of the graph in a form corresponding to the brightness modulation level. In Figure 2, the initial value of the brightness modulation level is 1 to simplify the explanation.
With a change of 1/2 times per stage, an output of 1 is obtained with the amplification factor at the initial value of 1 and a change of 2 times per stage.
More generally, a constant output mk can be obtained by setting the brightness modulation level initial value m to 1/n times per stage, and the initial value k of the amplification factor to n times per stage. First, as the brightness decreases, the integration time becomes longer within the arbitrarily set brightness modulation level → T ₁
The integration end point moves in the direction of →T ₂ →T ₃ →T ₄ .
And the integral time is T ₄ as the first specified time
Alternatively, if it takes T ₄ or more, the output of the reference time generation circuit 800 is sent to the controller 1100, and the brightness modulation level is lowered by one step under the control of the controller 1100, and the integration time is changed from T ₄ to T for the same brightness. It will be shortened to ₂ . At this time, the output of the controller 1100 is sent to the amplifier 300,
Since the amplification factor is increased by one step, the output does not change.
If it gets even darker, T ₂ →T ₃ →
After a change in T ₄ , the brightness modulation level is lowered by one step when the integration time becomes longer than T ₄ or T ₄ , and for the same brightness, the integration time becomes shorter from T ₄ to T ₂ .
Therefore, when the brightness decreases from a very bright state to a dark state, the integration end point will change from 1 → 2 → 3.
→5→6→7→9→10→11→13→14→15→17→18
Move according to →19→21→22→23. Next, a case where the brightness increases will be explained. As the brightness increases, the integration time becomes shorter within a given brightness modulation level, →T ₄ →T ₃ →T ₂
→The integration end point moves in the direction of T ₁ . and,
The integral time is T ₁ as the second specified time or
When the time becomes shorter than T ₁ , the output of the timing circuit 1000 goes to the controller 1100, and the brightness modulation level is increased by one step under the control of the controller 1100. For the same brightness, the integration time becomes shorter than T1. It becomes longer from ₁ to T ₃ . At this time, the output of the controller 1100 is sent to the amplifier 300, and the amplification factor is lowered by one step, so the output does not change. Similarly, when the brightness becomes even brighter, after the change from T ₃ → T ₂ → T ₁ , when the integration time becomes shorter than T ₁ or T ₁ , the brightness modulation level is raised by one step and the brightness remains the same. For , the integration time is T ₁
→Lengthens to T ₃ . Therefore, when changing from a very dark state to a very bright state, the integration end point is 23 → 22 → 21 → 20 → 18 → 17 → 16 → 14 → 13
Move according to →12→10→9→8→6→5→4→3→2→1.

By the operation described above, by setting the brightness modulation level corresponding to the brightness, it is possible to always obtain the integrated output in a time shorter than the fixed time _T4 , and the amplification factor corresponding to the brightness modulation level can be set. By providing this, a drop in output can be prevented and a constant integrated output voltage can always be obtained. Note that since the time condition for level transition has hysteresis as shown in the figure, even if the brightness changes somewhat after the transition, it remains within the set level and a more stable output can be obtained.

Next, specific embodiments of the present invention are shown in FIGS. 3 to 2.
This will be explained in detail with reference to FIG.

FIG. 3 shows an example of the configuration of an amplifier 300 according to the present invention. The inverting input terminals of the operational amplifier 302 and the operational amplifier 304 are connected through a resistor R ₃ 306,
The difference in the input voltages of the non-inverting input terminals of each operational amplifier is applied across a resistor R ₃ 306, and the resulting current is applied to each operational amplifier 302, 304.
A resistor R ₄ 3 connected between the output and the inverting input terminal of
By supplying 08,310 (R ₃ +2R ₄ )/
R Performs _3x differential amplification. The amplified voltages at points A and B are input to the inverting amplifier 320 at the next stage. The inverting amplifier 320 connects the operational amplifier 322 and the inverting input terminal of the operational amplifier 322 to the operational amplifier 30.
a resistor R ₁ 324 connected between the output of 2, and a resistor 326 connected between the inverting input terminal and the output;
Resistor R ₁ 328 connected between the non-inverting input terminal and the output of the operational amplifier 304, the non-inverting input terminal and GND
and a resistor R ₂ 330 connected between the
It is inverted and amplified with an amplification factor of R ₂ /R ₁ and output to the resistor divider 340 at the next stage. The resistor divider 340 is a resistor connected in series between the operational amplifier 322 and GND.
4R342, 2R344, R346, R348,
Dividing point of each resistor and next stage operational amplifier buffer 36
0 non-inverting input terminal, and controls switching by the output of the 4-bit register 350.
MOS switch 352, 354, 356, 358
Consisted of. The potential at the dividing point of each resistor is
Assuming that the voltage corresponding to the MOS switch 352 is 1,
Given by 1, 1/2, 1/4, 1/8 respectively, B3,
Selected by signals B2, B1, and B0. The 4-bit register 350 is connected to the control circuit 1100.
The data output to B3 to B0 is written by operating the CS terminal. The operational amplifier buffer 360 takes out as a buffer the output finally obtained by the first stage amplifier, the next stage inverting amplifier, and the final stage resistor divider. With the above configuration, the amplifier 300 is integrated with the integrating type photodetector array 200.
Amplify the difference between the signal input from and the noise by {(R ₃ + 2R ₄ )/R ₃ } (R ₂ /R ₁ ) × (set attenuation rate) times (1, 1/2, 1/4, 1/8) and print the output.

FIG. 4 shows another configuration example of the amplifier 300. As in FIG. 3, the noise output and signal output of the integral type photodetector array 200 are input to the non-inverting inputs of the operational amplifier 372 and the operational amplifier 378, respectively. or,
The internal configuration of resistive divider 370 is the same as that of resistive divider 340 in FIG. operational amplifier 372
The common terminal of the MOS switch of the resistor divider 370 is connected to the inverting input terminal of the resistor divider 370, and the common terminal of the MOS switch of the resistor divider 370 is connected to the output terminal of the resistor divider 370 via the resistor 374.
4R380 side is connected. operational amplifier 37
The R386 side of the resistance dividing section of the resistance divider 370 is connected to the inverting input terminal of No. 8. A resistor 4R37 is connected between the output of the operational amplifier 378 and the inverting input terminal.
6 is connected. This configuration performs amplification of 16R/Z times (Z=R, 2R, 4R, 8R) and outputs the result to the inverting amplifier 320. Inverting amplifier 320 is the same as that described in FIG. With the above configuration, the difference between signal and noise is (16R/Z) x (R ₂ /
_R1 ) is amplified and output.

Next, an embodiment of the monitor diode 500 will be described with reference to FIGS. 5 to 7. FIG. 5 shows an example where integration is performed from a low potential to a high potential, and a monitor diode 502 is connected between the power supply and a MOS switch, and the other end of the MOS switch is
Connected to GND. When the gate of the MOS switch goes high, the monitor diode 502 is charged, and when it goes low, integration is performed. FIG. 6 shows an example in which integration is performed from a high potential to a low potential, and a monitor diode 502 is connected between one end of a MOS switch and GND, and the other end of the MOS switch is connected to a power supply. When the gate of the MOS switch goes low, the monitor diode 5
02 is charged and becomes High, integration is performed. FIG. 7 shows a case in which integration is performed from a low potential to a high potential, and an output is produced based on the average integrated value of several monitor diodes. Several monitor diodes 502 are connected in parallel,
One end is connected to the power supply and the other end is connected to the MOS switch.
The other end of the MOS switch is connected to GND.
When the gate of the MOS switch goes high, the monitor diode 502 is charged, and when it goes low, it starts integrating.

Next, an example of the comparison circuit 600 is shown in FIGS.
This will be explained with reference to FIG. Figures 8 and 9
The figure is realized using a commercially available bipolar comparator, and the circuit in Figure 8 obtains a low output when the signal S is higher than the reference voltage R.
The circuit shown in FIG. 9 obtains a High output. 8 and 9 are circuits realized by bipolar comparators, whereas FIG. 10 is a circuit realized by CMOS. The signal S and the reference voltage R are connected to one end of a capacitor C612 constituting an AC amplifier 610 via SW1 and SW2, respectively. The AC amplifier 610 is connected to the capacitor C.
612, an inverter 614 connected to it, and a switch SW3 connected between the input and output of the inverter, and the amplification result is transferred to a flip-flop 620.
output to the D terminal. First, SW3 is closed and the input/output potential of inverter 614 is set to V _DD /2. Next, when SW1 is closed, capacitor C612 is charged to a potential difference between the signal potential and V _DD /2. In this state, open SW3 and SW1, then SW2
When the capacitor C612 is closed, one end of the capacitor C612 changes to the reference potential R, but the other end of the capacitor C612 is connected only to the input of the high impedance inverter 614 and there is no place for current to flow, so the capacitor C612 Potential does not change. Therefore, the difference in signal voltages applied to one end of capacitor C612 is added to the potential of capacitor C612 and output to the other end. The inverter 614 inverts the output due to the potential change applied to the threshold level, and outputs the comparison result to the flip-flop 620. The flip-flop holds the result by the signal _.phi.3 inputted to the clock terminal and outputs the result.

Next, an embodiment of the brightness modulation level generation circuit 700 will be described with reference to FIGS. 11 to 13. Figure 11 shows a circuit that generates a reference voltage based on GND.Resistors R ₀ 712, 4R714, 2R716, R71 are connected in series from the power supply to GND.
8, a resistor divider 710 consisting of R720, a MOS switch 722 whose one end is connected to each dividing point of the resistor divider 710, and whose other end is connected to the output,
Outputting a selection signal to the gate of switch 722 4
It controls the chip select terminal of the 4-bit register 730, receives setting data from the controller 1100, controls the gate of the MOS switch, and outputs a reference voltage.

FIG. 12 shows a circuit for generating a reference voltage based on the power supply, and is another embodiment of the resistor divider 710 shown in FIG. R74 in series from power supply to GND
2, R744, 2R746, 4R748, R ₀ 750
is connected to generate a voltage by resistor division.

FIG. 13 shows another embodiment of the brightness modulation level generation circuit 700, including an 8-bit register 750 that exchanges data with the controller, and an analog voltage that is connected to the 8-bit register 750 and that corresponds to the set digital amount. The brightness modulation level is generated under the control of the controller.

Next, FIG. 14, which is a specific embodiment of the reference time generation circuit, will be described. Oscillator 802 is connected to the clock terminal of counter 804 and provides a reference clock to counter 804. An integration start signal from the drive circuit 100 is connected to a reset terminal of the counter 804, and the start of integration is synchronized. Counter 804 outputs an output to integral end control circuit 900 after a certain set time.

Next, a specific example of the integration end control circuit 900 will be described. FIG. 15 shows a case where an OR circuit is used, and when the output of the comparison circuit 600 is High or the output of the reference time generation circuit 800 is High, the integration end control signal High is output to the integrating type light receiving element array 200. FIG. 16 shows a case where the output of the comparison circuit 600 is realized by an AND circuit.
When the output of the reference time generating circuit 800 is Low, an integration end control signal Low is output to the integrating type light receiving element array 200.

Next, FIG. 17, which is a specific example of the clock circuit 1000, will be described. Frequency division counter 100
2 inputs the output of the oscillator 802, divides it and ORs it.
Output to the input of circuit 1004. OR circuit 100
4 receives the output of the comparison circuit 600, gates the output of the frequency division counter 1002 only during the integration time, and outputs the output to the clock terminal of the counter 1006. The counter 1006 receives the integration start signal from the drive circuit at its reset terminal, and measures the integration time in synchronization with the integration start signal. The 3-state buffer receives the output of the counter 1006 and outputs an output when the CS terminal is selected.

Finally, FIG. 18, which is an embodiment of the controller 1100, will be described. FIG. 18 shows a controller 1100 connected to a one-chip microcomputer 8.
The program flowchart of this one-chip microcomputer is shown in FIGS. 19 to 21. The integration start pulse of the drive circuit 100 is input to the T0 terminal of this one-chip microcomputer, and the operation of the system is synchronized. The T1 terminal is an external timer interrupt terminal, which inputs the output of the reference time generation circuit 800, detects a low level input, and executes a timer interrupt processing routine. INT
The terminal is an external interrupt terminal, which inputs the output of the comparator circuit 600, detects a low level input, and
Execute external interrupt handling routine. Either the timer interrupt processing routine or the external interrupt processing routine is executed for one integration. Port 1 0~
2 bits (P10 to P12) are respectively connected to the CS terminal of the register of the amplifier 300 and the brightness modulation level generation circuit 7.
It is connected to the CS terminal of the register 00 and the CS terminal of the register of the clock circuit 1000, and controls reading and writing to each register. The data read and written at this time is bus port (BUS) 8.
Transferred using all or part of a line of bits.

Next, the operation of the present focus detection device having the above configuration will be explained using the flowcharts shown in FIGS. 19 to 21.
This will be explained along with the operation of the hardware configuration. Note that the processing based on this flowchart is performed by the controller 1.
100.

FIG. 19 is a flowchart of the main routine. When the power is turned on, the step
In S11 and S12, the brightness modulation level and amplification factor are initialized. The initial value of the brightness modulation level is stored in the internal register R2 of the brightness modulation level generation circuit 700 in FIG.
0 internal register R3.

When this initial setting is completed, in the step between the coupler and the connector, the process waits for the completion of the hardware setting before the start of integration by the integrating type light receiving element array 200 and the start of integration. First, in steps S13 and S14, interrupts are prohibited, and then a timer (clock circuit 1000) for measuring the integral time is set, and in steps S15,
Wait for the start of integration in S16. The controller (microcomputer) 1100 monitors the T0 terminal (see Fig. 18), and after the T0 terminal becomes high level,
The start of integration is known by detecting that the signal has fallen to the low level. As mentioned above, the integration start pulse of the drive circuit 100 is input to the T0 terminal, and this processing synchronizes the operation of the system.

When integration is started, interrupts are enabled (step S17) and a timer is started (step S18). After this, in step S19, an interrupt operation is awaited. Note that in this interrupt wait process, the CPU waits for an interrupt signal to be input from the reference time generation circuit 800 or the comparison circuit 600 to the INT terminal or the T1 terminal. Then, the reference time generation circuit 800
When an interrupt is received from the comparator circuit 600, the timer interrupt processing routine (processing from the connector) shown in FIG. 20 is started, and when an interrupt signal is received from the comparison circuit 600, the external interrupt processing routine (processing from the connector) shown in FIG. Start.

When the timer starts, as described above, the comparison circuit 600 or the reference time generation circuit 80 is activated depending on the subject brightness received by the monitor diode 500.
The integration end control circuit 900 that receives the pulse (interrupt signal) from 0 ends the integration of the integrating type light receiving element array 200.

As mentioned above, the reason why the integration ends with the output of the reference time generation circuit 800 is when the integration reaches the specified time T ₄
This is the case when the brightness of the subject is low (when the output of the monitor diode does not reach the brightness modulation level within the specified time _T4 ).
In this case, the controller 1100 detects that a low level signal is input from the reference time generation circuit 800 to the T1 terminal, and starts the timer interrupt processing routine shown in FIG. 20.

In this timer interrupt processing routine, since the subject has low brightness, the amplifier 300 changes (increases) the amplification factor of the output of the integrating type light receiving element array 200, and at the same time, since the integration does not end within the specified time _T4 , The brightness modulation level by the brightness modulation level generation circuit 700 is changed (down) in the direction that the integration ends within the specified time _T4 .

For this purpose, first, in step S20, it is determined whether the current amplification factor by the amplifier 300 is the maximum. If this amplification factor is the maximum, it is not possible to further increase the amplification factor of the output of the integrating type photodetector array 200, so the process jumps to step 24 and sets the current brightness modulation level generated by the brightness modulation level generation circuit 700 to the minimum value. Let's move on to determining whether or not there is.

On the other hand, if it is determined in step S20 that the amplification factor is not the maximum, the amplification factor is increased in steps S21 to S23 and its stored value is changed. When the amplification factor is increased by one step, the output of the integrating type light receiving element array 200 is amplified twice as much as before and is applied to the focus detection circuit 400, so that it is possible to deal with low brightness objects.

If it is determined in step S24 that the brightness modulation level is the minimum, the integration time is set to the specified time _T4 .
It is impossible to change the brightness modulation level in the direction of further shortening (the lowermost horizontal line and time axis in Figure 2).
(This corresponds to the case where the integration time is longer than the point 23 where _T4 intersects), in step S28, interrupts are prohibited, a stack operation is performed, and the return is made to the connector of the main flow.

If it is determined in step S24 that the brightness modulation level is not the minimum, the brightness modulation level is lowered by one step in steps S25 to S27, and this is stored. In FIG. 2, for example, when the brightness modulation level is 1 and the integral line of the monitor diode 500 passes through points I ₁ , I ₂ , I ₃ , the point I ₁ (specified time
This means that the luminance modulation level is reduced to _1/2 and the integration is adjusted to end at point I ₂ (integration time T 2 ), whereas the integration was completed at point I 2 (integration time T ₂ ). In other words,
For objects of the same brightness, the integration time is T ₄
In the direction of becoming shorter (however, the shortest integration time is T ₁ )
At the same time, the amplification factor is increased by the reduction in the integration time, and the output level to the focus detection circuit 400 is held constant.

The above processing is continued until the integration time becomes shorter than T ₄ , so the focus detection circuit 400 can detect the output of the integration type photodetector array 200 at an appropriate level with an appropriate integration time even for a low-luminance object. Obtainable.

Next, the integration end control circuit 900
Integration ends when a pulse output from 0 is received, as described above, when the integration time is shorter than the first specified time _T4 , that is, when the subject is of high brightness. In this case, the controller 1100
is first sent from the comparison circuit 600 via the INT terminal.
The output of the low level signal is detected and the external interrupt processing routine (processing from the connector) shown in FIG. 21 is started.

In this high-brightness external interrupt processing routine, when the brightness is so high that the integration time becomes shorter than the second specified time _T1 , the brightness modulation level generated by the brightness modulation level generation circuit 700 is changed (increased) in the direction that the integration time becomes longer. At the same time, the amplification factor of the output of the integrating type light receiving element array 200 by the amplifier 300 is changed (down). Note that when the integration time is greater than or equal to T ₁ , that is, greater than or equal to T ₁ and less than or equal to T ₄ , nothing is done because it is within normal time.

In this routine, first, in step S30, the current integral time measured by the clock circuit 1000 (the time when the integral level of the output of monitor diode 00 reaches the set brightness modulation level) is input, and this current integral time is secondly counted. In step S31, it is determined whether or not the specified time T1 is longer than the specified time _T1 . For a high-brightness subject, if the current integration time is longer than the second specified time _T1 , there is no need to lengthen the integration time (if it is longer than the specified time _T4 , the timer interrupt processing routine is entered). Fly to S40,
Disable interrupts, perform stack operations, and return to the main flow connector.

On the other hand, if it is determined in step S31 that the current integration time is shorter than the specified time _T4 , it is determined in step S32 whether the current amplification factor by the amplifier 300 is the minimum. If this amplification factor is the minimum, the amplification factor of the output of the integrating type photodetector array 200 cannot be lowered, so the process jumps to step 36 and checks whether the current brightness modulation level generated by the brightness modulation level generation circuit 700 is the maximum. Let's move on to the decision whether or not.

On the other hand, if it is determined in step S32 that the amplification factor is not the minimum, the amplification factor is decreased in steps S33 to S35 and its stored value is changed. When the amplification factor is decreased by one stage, the output of the integrating type photodetector array 200 becomes 1/2 times that of the previous one, and the output from the focus detection circuit 4 increases.
00, it is possible to deal with high-brightness objects.

If it is determined in step S32 that the brightness modulation level is the maximum, it is impossible to change (down) the brightness modulation level in the direction of making the integration time longer than _T1 (as shown in the uppermost part of Fig. 2). The horizontal line is the time axis
(corresponds to the case where the integration time is shorter than the point where it intersects T ₁ ), interrupts are prohibited in step S40,
Perform a stack operation and return to the main flow connector.

If it is determined in step S6 that the brightness modulation level is not the maximum, the brightness modulation level is increased by one step in steps S37 to S39, and this is stored. In FIG. 2, for example, when the brightness modulation level is 1/4 and the integral straight line of the monitor diode 500 passes through the points I ₁ , I ₂ , I ₃ , the point I ₃ (the integral time
This means that the luminance modulation level is increased to _1/2 so that the integration ends at point I ₂ (integration time T _{2 ), whereas the integration ends at point I 2 (integration time T 2} ). In other words,
For objects of the same brightness, the integration time is T ₁
In the direction of increasing length (however, the longest integration time is T ₄ )
At the same time, the output level to the focus detection circuit 400 is held constant by lowering the amplification factor by the length of the integration time.

The above processing is continued until the integration time becomes longer than T ₁ , so the focus detection circuit 400 can detect the output of the integration type photodetector array 200 at an appropriate level with an appropriate integration time even for a high-brightness object. Obtainable.

As described above, according to this embodiment, the integration time is T ₄
If it takes longer than T1, change the integration time to 1/2 and change the amplification factor to twice the current value. If the integration time is shorter than _T1 , change the integration time to 2 times and change the amplification factor to 1/2 of the current value. Since the change is made twice, distance measurement data at an appropriate level can be obtained within the integration time T ₁ to T ₄ .

As described above, in order to maintain the output level of the amplifier within a certain range, the camera focus detection device of the present invention lowers the reference value by a predetermined step when the measurement time becomes longer than the first specified time. When the amplification factor is increased by a predetermined step and the measurement time becomes shorter than a second predetermined time shorter than the first predetermined time, the reference value is increased by a predetermined step and the amplification factor is lowered by a predetermined step. Therefore, desired data can always be obtained within the first specified time (T ₄ ) and at least the second specified time (T ₁ ), thereby providing a focus detection device with fast response. Also,
Since the dynamic range can be changed according to the brightness of the subject, it is also possible to detect focus on darker subjects, improving focus detection ability. Furthermore, since the data detection time can always be shorter than the set time _T4 , it is possible to prevent the effects of camera shake, etc., to enable high-speed focus detection, and to provide a device that is more user-friendly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram corresponding to the claims, Fig. 2 is a graph explaining the functions of the structure of the present invention, Figs. 3 to 18 are illustrations of one embodiment of each component of the present invention, and Fig. 19 21 are flowcharts for explaining one embodiment of the controller. 100... Drive circuit, 200... Integral type light receiving element, 300... Amplifier, 400... Focus detection circuit, 500... Monitor guide, 600... Comparison circuit, 700... Brightness modulation level generation circuit, 80
0... Reference time generation circuit, 900... Integration end control circuit, 1000... Timing circuit, 1100... Controller.

Claims (1)

[Claims] 1. An integral type light receiving element array; A monitor diode that outputs an integrated voltage corresponding to the average illuminance of the integral type light receiving element array; A reference value setting circuit that can change a reference value in steps; The monitor diode a comparison circuit that detects that the output of the monitor diode has reached the reference value by comparing the output of the monitor diode with a reference value set by the reference value setting circuit; a clock circuit that measures time; an integration end control circuit that stops the integration of the integrating light receiving element array at the time of the detection or when the measured time exceeds a first specified time; an integral output of the integrating type light receiving element array an amplifier capable of changing stepwise the amplification factor for amplifying; and, in order to maintain the output level of the amplifier within a certain range, when the pre-measurement time becomes longer than the first specified time, the reference value is set to a predetermined value; When the measurement time becomes shorter than a second specified time that is shorter than the first specified time, the reference value is increased by a predetermined step and the amplification factor is increased by a predetermined step. A focus detection device comprising: control means for lowering the focus; 2. The control means recited in claim 1 is:
When the measurement time becomes longer than the first specified time, the reference value is changed to 1/2, the amplification factor is doubled, and the measurement time becomes longer than the second specified time.
The focus detection device doubles the reference value and increases the amplification factor by 1/2 when the time becomes shorter than a second prescribed time that is shorter than 1/2 of the prescribed time.