JPH0462647A - Memory controller - Google Patents

Abstract

PURPOSE:To attain the connection between the memories of different access speeds by detecting the type of an extension memory connected to a memory connection means by a detection means and setting variably the control signal for the reading/writing operations. CONSTITUTION:A CPU 1 generates the image data based on the print data inputted from a host device 11 through a host control part 2 and then writes the image data into a page buffer provided in a RAM 7. If a conversion subject font contained in the print data is included in an extension ROM provided on an extension ROM board 8, the CPU 1 reads the extension ROM of the board 8 and designates a reading subject memory to read the font corresponding to a character code. A timing signal generating part 3 outputs a timing signal for each memory when an address is outputted from the CPU 1 for access to each memory area since the CPU 1 arranges the memories so as to secure the coincidence with a memory map.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device that reads and writes information to and from a memory connected to an expansion memory board.

[Prior Art] In recent years, page printers such as laser beam printers, i.e., image data to be output for each page, are produced based on print data or a print program output from a host device such as a host computer or word processor. Page printers that are characterized by generating and printing information have become popular. The page printer is mainly composed of an image forming controller and a printer engine. The image forming controller generates bitmap image data based on print data or a print program output from the host device, and controls the output of the image data to a printer engine (image output unit). Based on the image data output from the image forming controller, the printer engine forms an image by exposing the photoreceptor to laser light, and then performs printing through a sequence of toner development, transfer to paper, and fixing.

The former image forming controller uses Postscript (P
ostScript) and other descriptive languages have become mainstream. The image forming controller generally includes a microprocessor that processes print data in the page description language at high speed, and a RAM that includes image memory for one page.

It consists of a code ROM that stores control programs, a font ROM' that stores font data, and other communication control sections.

In addition, recent image forming controllers support extended R, which supports various page description languages and font data.
It has an interface (I/F 1 part) for connecting the OM, or an I/F part for expansion RAM to improve processing performance by adding the above-mentioned RAM, and the above-mentioned RAM and ROM can be connected to these I/F parts. Installed expansion memory board or I
There are an increasing number of configurations that allow connection of C memory cards.

[Problems to be Solved by the Invention] However, the expansion ROM I/F of the image forming controller in the conventional apparatus described above is limited to the type of memory (code R
OM, font ROM, or RAM) are uniquely fixed I/Fs, and the operation timing for each I/F, that is, the access speed, is also fixed. For this reason, the conventional device has the inconvenience that memory specifications are limited and memories with different access timings cannot be connected.

Therefore, the purpose of the present invention is to eliminate such problems,
It is an object of the present invention to provide a memory control device capable of reading/writing information by connecting various types of memories with different access speeds as expansion memories.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a memory connecting means to which one or more expansion memories having different read/write speeds can be attached and detached, and a memory connecting means to which one or more expansion memories having different read/write speeds can be attached. A detection means for detecting the type of the connected expansion memory, and variably setting the generation timing of a control signal for reading/writing to the expansion memory in accordance with the type of expansion memory detected by the detection means. The invention is characterized in that it comprises a timing signal generating means for generating a timing signal.

[Function 1] In the present invention, the type of expansion memory connected to the memory connection means is detected by the detection means, and control signals for reading/writing are variably set in accordance with the type of memory. Therefore, it is possible to connect memories with different access speeds interchangeably, or to connect a plurality of memories with different access speeds.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration of a printer control device to which the present invention is applied. In the figure, 1 is a central processing unit (central processing unit) that centrally controls the entire printer control device.
CPU). The CPUI generates image data to be output to the printer engine 12 from print data such as character codes or a print program input from the host device 11 through the host control unit 2 . After the CPUI finishes generating image data, it communicates with the printer engine 12 through the printer control unit 9 to execute printing.

2 is a host control unit that controls communication between the host device 11 and the CPUI. 3 is a timing signal generator, which generates code ROM 5. Font ROM6. RAM? and performs read/write control of the expansion ROM board 8.

4 is an input/output interface (Ilo) control unit, and C
The I10 area located on the PUI memory space is
When the address is specified by I, select each of the following I10 units specified by the address, that is, the host control unit 2 or the printer control unit 92 and the display control unit 10, and select the CPU
enable communication with

A code ROM 5 stores a program for controlling the operation of the CPU. A font ROM 6 stores character fonts, ie, bitmap fonts or outline fonts, necessary when generating image data from print data including text characters.

A RAM 7 is used as a work area for the CPUI and as a page buffer for storing one page worth of image data to be output to the printer engine. Normal RA
M7 is constituted by DRAM. Reference numeral 8 denotes an expansion ROM board, which is composed of additional font data or a ROM for storing font data, and is detachably connected to the printer control device via a connector. As shown in FIG. 1(B), the expansion ROM board 8 has a connection position determined in advance for each type of access speed, and has a dedicated ID code terminal that changes the potential of the connection pin when a memory is installed. and an IDB that generates an IDA signal indicating that the memory is connected to the printer control device and a signal specifying the access speed corresponding to the type of memory.
Generate a signal. The expansion ROM board 8 operates as a memory connection means and a detection means.

Reference numeral 9 denotes a printer control unit that controls communication between the CPUI and the printer engine 12 and controls the output timing of image data. Reference numeral 10 denotes a display control unit that controls data display on the display unit 13 and manually switches the display unit. 1
Reference numeral 1 denotes a host device such as a host computer or a word processor that forms and outputs print data or a print program.

Reference numeral 12 denotes a printer engine that exposes, develops, transfers, and fixes image data output from the printer control device using an electrophotographic process and prints out the image data. Reference numeral 13 denotes a display section consisting of display means and operation switches for displaying the operating status of the printer control device and printer engine.

In this embodiment, addresses specified by the CPH are assigned to the memory as shown in FIG. That is, the code ROM5 containing the interrupt vector table is arranged starting from address 0000000H, and then, moving toward higher addresses, font ROM6 starts from address m, 0OOOOOH, ROM7 starts from address m2000000H, and expansion ROM starts from address m3000000H.
The I10 section of the board 8 is arranged starting from address m4000000H.

Next, the operation sequence in the above configuration will be explained.

Based on print data output from the host device 11 and input through the host control unit 2, the CPUI generates image data. After this, the CPUI sends the generated image data to RA
Write to the page buffer located in M7. At this time, if the print data is a text character and has a code, the font ROM 6 reads the font data that matches the character code to generate image data.

In addition, if the font to be converted in the print data exists in the expansion ROM on the connected expansion ROM board 8, the CPU
I specifies the expansion ROM of the expansion ROM board 8 as the memory to be read, and reads the character code and corresponding font from this expansion ROM. Since each CPUI has a memory arrangement that matches the memory map shown in FIG. 2, when an address for accessing each memory area is output from the CPU 1, the timing signal generating unit 3 Output the corresponding timing signal.

After the CPUI finishes generating image data for one page, it instructs the printer engine 12 to start printing through the printer control unit 9. The printer control unit 9 outputs image data to the printer engine at a predetermined timing synchronized with vertical and horizontal synchronization signals output from the printer engine 12. The CPUI displays on the display unit 13 the operating status of each part of the printing device during communication with the host device and image data generation, the operating status of the printer engine during printing, the error status when an error occurs, and the like. At this time, the above status information is transmitted to the display unit 13 through the display control unit IO.
Output to. Further, the CPUI inputs user instructions from the operation switches through the display control unit 11, and performs processing such as changing the print mode.

Next, the configuration and operation of the timing signal generator 3 shown in FIG. 1 will be explained.

FIG. 3 shows the circuit configuration of the timing signal generating section 3 which operates as the timing signal generating means of the present invention.

In the same figure, 14 is a memory selector, and CPLI
Address ADH, address strobe signal AS, and read/write signal R output from I onto the address bus
/W, a signal for selecting the above-mentioned memory is output to the memory to be accessed. In this example, the C0DEC3 signal is sent to code ROM5, the FONTC3 signal is sent to font ROM6, and the RAMC5 signal is sent to RAM7.
signal, and outputs an EXROM signal to the expansion ROM timing generator 19.

In addition, the DRA output from the clock generator 16
Refresh signal REFRESH to M (RAM7)
When the memory selector 14 inputs the RAMC5 signal, the memory selector 14 outputs the RAMC5 signal. 15 is a multiplexer (MIX), which separates and inputs the address of the lower n bits and upper n bits to the lower 2n bits of the address ADH, the upper n bits are used as a row address, and the lower n bits are inputted. The MA bus is output as a column address. In this case, if the 5ELCADR signal is output, the lower n bits are selected, and if the 5ELCADR signal is not output, the upper n bits are selected.

16 is a clock generator which generates a memory control clock signal M (:LK and a CPU clock signal CPUC) based on a basic clock signal inputted from a crystal oscillator 17.
LK, generates the refresh signal REFRESH.

Note that in this example, the frequency of the MCLK signal is output as twice the frequency of CPUCLK.

18 is a RAS/CAS generator, RAMC5
If the signal is output, the control signal RA to the DRAM
Sm.

It generates CAS[Il (m is arbitrary and represents the number of banks) and outputs 5ELCADR for selecting the column address to MUX15. 19
is a timing generator for expansion ROM, and when the EXRQM signal is output from the memory selector 14,
EXROMCS signal and enable signal E with timings that correspond to the ID code shown in FIG.
Outputs X'ROMENB.

20 are path observers, each with memory and 1
When the read or write operation for the 10th copy is completed, a data transfer acknowledge signal D indicating that
Generate TACK and output to CPUI. The path observers 20 each receive memory select signals C0DEC3 and F.
rocs signal output from ONTC3, RAMC5 and IO control unit 4, and expansion ROM enable signal E
XROMENB is manually operated to output the data transfer acknowledge signal DTACK in synchronization with CPUCLK.

Next, FIGS. 4, 5, 7, and 8 show the operation timing of the timing signal generator in FIG. 3. Figure 4 shows code ROM5 and font ROM
The operation timing for B is shown.

As shown in Figure 4, the CPUI bus cycle is 3CPL.
It is executed in 6 states: I clock T, to T6.

CPLII outputs address data on the address bus ADR from T1 to T6, and outputs an AS signal during the period from 2 to T5. The memory selector 4 outputs the CODECS signal or the FONTC5 signal while the AS signal is being output.

The path observer 20 notifies CPt1l that the bus cycle has ended by outputting the DTACK signal from the beginning of T3 to the middle of T6.

Further, FIG. 5 shows the operation timing for RAM7 (DRAM). When the address data on the ADR is in the RAM area, the RAMC5 signal is output from the memory selector 14 as described above. RAS/CAS generator 1
8 strobes the row address on the MA bus by outputting the RAS signal at the beginning of T3, and outputs the 5ELCADR signal in the middle of T3 to output the column address on the MA bus. Then, the column address is strobed by the CAS output at the beginning of T4. In addition, the following signals RAS, C
AS and bPLL; υ is output to l(AM until δ1 reactor output is no longer available. Also, DTACK
Signals are also output in the same manner as in FIG.

Next, FIG. 6 shows the relationship between the value of IDB in the ID code terminal and the wait number of CPUCLK in the bus cycle when the expansion ROM board 8 is connected.

When IDB=00, the bus cycle is executed in 3 clock cycles as in FIG. 4, and when IDB=01, the bus cycle is executed in 4 clock cycles with an I CPUCLK wait inserted between T4 and T. Similarly, when IDB=10, it is executed in 5 clock cycles, and when IDB=11, it is executed in 6 clock cycles. Figure 4 shows the extended RO when IDB = 00, that is, no wait cycle is inserted.
Figure 5 shows the operation timing for the M board.
If B=01, wait cycle I CPUCLK
The operation timing is shown when only the number of minutes is inserted.

In Figure 5, cput monitors the DTACK signal,
If the DTACK signal is not output at T3, wait cycles (Tw: 2) are automatically inserted after T4. When wait cycles are inserted for I CPUCLK, the EXROMENB signal is output for the first time at T4, and the DTACK signal is output from the beginning of the next Tw.

Next, a second embodiment of the present invention will be described. In this example, FIG. 9 shows a block diagram of a printer control device that interfaces with an extended memory board and has the type of memory board and the type of operation timing as an ID code terminal.

In this figure, the same parts as in FIG. 1 are denoted by the same reference numerals, and detailed explanations are omitted. In FIG. 9, 3a is a timing signal generator, which generates control signals for the memory, and
Outputs memory addresses for RAM 7 and extended memory board 8a. Reference numeral 8a denotes an expansion memory board, which can be equipped with a code ROM, font ROM, or RAM as an expansion memory, and has an ID code terminal indicating the type of memory to be expanded and the type of operation timing.

The expansion memory board 8a is shown in the memory map of FIG.
Set m3A000000 as the starting address so that
H address, m3.000000H address, m3coo00
Address 00H is code ROM and font ROM respectively.
, are arranged with respect to the RAM, and identify the memory to be accessed from the address data output from (:PUl onto the address bus A), and generate a control signal corresponding to that memory.

FIG. 11 shows the configuration of the timing signal generating section 3a having such a function.

In the figure, 14a is the next signal C0D that selects each memory based on the address data on the address bus ADR.
EC3, FONTCS, RAMC5 and EXMEM
This is a memory selector that outputs . 15a is a multiplexer MI that generates an n-bit multiplexer address MA of RAM (DRAM) from the 2n-bit ADRA using the 5ELCADR signal and outputs it using the MAENB signal.
It is X.

21 is an expansion memory control unit, which is an expansion memory board 8a.
The ID code signal outputted from the memory selector 14; that is, the ID multiplied signal OA indicating the type of memory and the ID signal ID indicating the type of operation timing are inputted to the memory selector 14.
The extended memory select signal EXMEM output from a is input. EX for access to code ROM
AC: S signal, E when accessing font ROM
XBC3 signal, EXC (:
S signal is output, and an enable signal EXMENB is output to the path observer 20.

22 is RAM 7 and expansion memory (RAM) board 8a
23 is an AND gate that generates the output enable signal MAENB of the MOX 15a when 23 is selected. 24 is the output enable signal MAE
This is a state buffer that prohibits the address data on the address bus ADRA from being output onto the address bus ADRB while NB is being output. That is, R.A.
When M7 or expansion memory (RAM) board 8a is selected, the MA double signal output from multiplexer MUX15a is output onto the address bus ADRB; when other expansion memory boards; code ROM or font ROM are selected, the address is output. Outputs the address bus on bus ADRA onto address ADRB.

Next, FIG. 12 shows the relationship between the ID code signal ID output from the expansion memory board 8a and the type of memory, and the relationship between the IO code signal IDB and the memory operation timing is the same as in FIG. The wait cycle is also inserted between T4 and T5 in exactly the same way as in FIG.

As explained above, in this embodiment, the expansion memory board added to the printer control device is provided with an ID code terminal indicating the memory operation timing and an ID code terminal indicating the type of memory, and an ID code terminal indicating the memory type. By providing a timing signal generator that selects each memory based on data and generates operation timing for each memory to control access, it is possible to flexibly deal with memory expansion and control of the printer control device. became.

In addition, although the example shows memory expansion using an expansion ROM board or an expansion memory board, there is no problem in applying it to expansion using an IC memory card, etc. in addition to these memories, and the configuration shown in the example It is not limited to this.

Further, by applying the present invention to various electronic devices, not only can memory expansion be easily performed, but the memory is not limited to the type of memory.

[Effects of the Invention] As explained above, according to the present invention, memories with different access speeds can be used for expansion. There is no need to fix the generation timing of the control signal to suit a slow memory (it is possible to select and use a desired memory depending on the purpose of arithmetic processing).

In addition, if you do not need to increase the calculation processing speed,
Since it is also possible to use an inexpensive memory with a slow access speed, it is possible to contribute to reducing the manufacturing cost of the device.

Furthermore, an effect can be obtained in that it can be used for general purposes for reading/writing in various electronic devices using expansion memory.

[Brief explanation of drawings]

FIG. 1(A) is a block diagram showing the circuit configuration of the printer control device in the first embodiment of the present invention, and FIG.
A block diagram showing an example of the connection of the expansion ROM board in Figure (A), Figure 2 is a memory map showing the address space of the embodiment of the present invention, and Figure 3 is a block diagram showing the circuit configuration of the timing signal generation section in Figure 1. , FIG. 4 shows the code ROM and font R of the embodiment of the present invention.
FIG. 5 is a timing chart showing the generation timing of control signals for the OM; FIG. 5 is a timing chart showing the generation timing of control signals for the RAM (DRAM) of the embodiment of the present invention; FIG. 6 is a timing chart of the expansion ROM board of the embodiment of the present invention. FIGS. 7 and 8 are timing charts showing the generation timing of control signals for the expansion ROM board according to the embodiment of the present invention. FIGS. FIG. 9 is a block diagram showing the circuit configuration of the printer control device in the second embodiment of the invention, FIG. 1C is a memory map showing the address space in the second embodiment of the invention, and FIG. 11 is a block diagram showing the circuit configuration of the printer control device in the second embodiment of the invention. FIG. 12 is a block diagram showing the circuit configuration of the timing signal generating section, and is an explanatory diagram showing the relationship between the ID code from the extended memory board and the type of memory in the second embodiment of the present invention. 1...cpu. 2... Host control section, 3.3a... Timing signal generation section, 4... I10
Control unit, 5... Code ROM, 6... Font ROM. 7... RAM, 8... Expansion ROM board, 8a... Extension memory board, 9... Printer control unit, 10... Display control unit, 11... Host device, 12... Printer Engine, 13...Display unit, 14, 14a...Memory selector, 15.15a...Multiplexer, 16...Clock generator, 17...Crystal oscillator, 18...RAS/CAS generator, 19 ... Expansion ROM timing generator, 20 ... Path observer, 21 ... Extension memory control unit, 22 ... AND gate, 23 ... NOT gate, 24 ... 3-state buffer. Figure (B) Figure 6 Figure 7 Figure 5 Figure 8

Claims (1)

[Scope of Claims] 1) Memory connection means to which one or more expansion memories having different read/write speeds can be attached and removed; and detection means for detecting the type of expansion memory connected to the memory connection means; A memory characterized by comprising timing signal generation means for variably setting the generation timing of a control signal for reading/writing to/from the expansion memory in accordance with the type of expansion memory detected by the detection means. Control device.