JPH0461688A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To execute the write operation and the read-out operation by providing a write recovery circuit operated at the time when write is finished, and an intermediate potential precharge circuit which operates at the time of read-out, and also, gives such a potential as the gain of a read-out means becomes large to the wiring. CONSTITUTION:A write recovery circuit 2 is constituted of three pMOS transistors 31-33, and to each source of the pMOS transistors 31, 32, a power supply voltase Vcc is supplied, and to each drain thereof, data lines 5. 6 are connected. Also, an intermediate potential precharge circuit 5 is constituted of one pMOS transistor 33, two nMOS transistors 33, 36, and an inverter 37. In such a state, at the time of write, especially, at the time of write recovery, the write recovery circuit 2 operates, and at the time of read-out, the intermediate potential precharge circuit 3 operates. This intermediate potential precharge circuit 3 precharges the potential of the wiring to the intermediate potential by which the gain of a read-out means becomes large. In such a way, the read- out means for sensing the potential of its wiring executes an output corresponding to data at a high speed.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory such as an SRAM (static RAM) in which signals are written or read via a pair of bit lines or data lines. [Summary of the Invention] The present invention provides a semiconductor memory in which information is read and written to each cell of a plurality of memory cells via a pair of wirings, and the present invention provides a write recovery circuit that operates at least when writing is completed, and a write recovery circuit that operates at the time of reading. In addition, by providing the wiring with an intermediate potential precharge circuit that applies a potential that increases the gain of the reading means, it is possible to realize faster writing and reading operations. In a semiconductor memory having an end-type sense amplifier, high-speed reading is achieved by providing clamping means between nodes forming a pair of sense amplifiers before the final stage. [Prior Art] Semiconductor memories such as SRAMs are required to have a larger capacity and higher speed. One technique for increasing speed is data line and bit line equalization technology, which shorts a pair of wires at complementary potentials to prepare for transition by the next data. In particular, the speed is increased by starting the operation with a pulse from an ATD (Address Transition Detection) circuit. Further, as a circuit technology related to these data lines and bit lines, a data line load circuit is required to prevent disturbances from connected data lines and the like when a word line is selected. FIG. 7 is a circuit diagram showing an example of a conventional semiconductor memory. This semiconductor memory has a plurality of memory cells 100 arranged in a matrix, and each of these memory cells 100 is selected row by row by a word line WL. Furthermore, each memory cell 100 has a pair of bit lines 10 for each column.
1,102 are connected and these bits 110
1 and 102 are connected to the data lines 104 and 105 via column selection transistors 103 and 103, and the terminals thereof are connected to the pinto line load circuits 106 and 106.
04.105 is a wiring provided between the bit line and the sense amplifier, and a data line load circuit 107 consisting of a PMOS transistor and a write control switch 108,1
A write circuit is connected through 08. A pair of data I#! i. 4.105 is connected to the dual-end type first-stage sense amplifiers 109, 109, and the pair of output terminals are connected to the next-stage sense amplifiers 110, 11.
Connected to 0. These sense amplifiers 109.11
A pMO5) transistor 111, 111 for equalization is provided at the output terminal 0, and the output of the sense amplifier 110 is read out to the outside of the chip via an output circuit 112. FIG. 8 is a waveform diagram illustrating the operation of the conventional semiconductor memory shown in FIG. Each pulse of ΦP ((B) in Figure 8) and equalize signal ΦEQ ((C) in Figure 8)
Occurs in az. Here, when the previous cycle is a read cycle,
Level difference Δ between a pair of data lines 104 and 105 before precharging. is a small value, and is at levels D and D ((d) in FIG. 8) on the side of the power supply voltage Vce. Also, when the previous cycle is a write cycle, level E in the diagram
), D (as shown by the broken line in FIG. 8(d)), the level difference Δ between the data m104 and 105 before precharging is set to a value close to the full swing, and one side is set to the power supply voltage Vcc.
g! The other level is the level on the ground voltage GND side. Then, when the data line load circuit 107 is activated by the precharge signal ΦP at time tag, the data lines on the low level side are boosted with equalization, and the level of each data line changes to high level at time toz. Also, at time t, the equalize signal ΦEQ causes pMO3) transistor 1 to
11 and 111 become conductive, and each sense amplifier 109
, 110 outputs SA+, SA+ ((f) in Figure 8)
, S A z , and S A t (01O in FIG. 8) reach a potential approximately halfway between the power supply voltage Vcc and the ground voltage GND at time t03. When such a data line precharge operation is completed, word a W L (e) is selected, and its data appears on data lines 104 and 105 as a level difference. Then, sensing the level difference between the data lines 104 and 105, it is amplified by the sense amplifier 109 in the first stage.
A level difference appears in the outputs SA, , SA, GE). Subsequently, the output S A t, S of the next stage sense amplifier 110
A similar level difference appears in A t (g)L. [Problems to be Solved by the Invention] In the semiconductor memory having the circuit structure shown in FIG. 7, even when transitioning from a write operation to a read operation (at the time of write recovery), the operation of the data line load circuit 107 causes the data line 104. The potential of 1'05 is pulled up, and data in the memory cell 100 is prevented from being destroyed. However, during a read operation, data lines 104 .
When the potential of the sense amplifier 105 is pulled-amplified to near the t source voltage Vcc, the gain of the sense amplifier 109 becomes small, making it difficult to fully utilize the capability of the sense amplifier 109. Furthermore, when the potential difference between the data line pair 104 and 105 becomes large, even if the equalizing pMO transistor 111 provided in the sense amplifiers 109 and 110 is activated, the potential of the data line pair 104 and 105 is sufficiently reduced. Balancing cannot be achieved, resulting in problems such as a slow reading speed and the need to increase the size of the pMOS transistor ill. Therefore, in view of the above-mentioned technical problems, the present invention aims to provide a semiconductor memory that achieves a sufficiently high speed. [Means for Solving the Problems] In order to achieve the above-mentioned object, a semiconductor memory of the present invention includes a plurality of memory cells, a pair of wirings respectively connected to the memory cells, and the above-mentioned connection via the wirings. a writing means for writing information into the memory cell; a reading means for reading information from the memory cell via the wiring; a write recovery circuit that applies a potential to the wiring to prevent data destruction; and an intermediate potential precharge circuit that precharges the pair of wirings to an intermediate potential at which the gain of the reading means is greater than other potentials during a read operation. It is characterized by having the following. Here, the write recovery circuit and the intermediate potential precharge circuit may be structured to be controlled by a control circuit thereof, and for example, the signal from the control circuit may be based on a write enable signal WE or the like. I can do it. Note that the above-mentioned wiring is a conductor line used for reading and writing, such as a data line and a bit line. Further, another semiconductor memory of the present invention is a semiconductor memory having a multi-stage dual-end type sense amplifier,
The present invention is characterized in that a clamping means is provided between nodes forming a pair of sense amplifiers before the final stage. Here, as an example of the clamp means, a diode-connected pMO3) transistor or nMO5) transistor can be used. [Operation] In the semiconductor memory of the present invention, the data line load circuit is not uniformly activated at the end of each cycle, but the write recovery circuit is activated during writing, particularly during write recovery, and the intermediate potential precharge circuit is activated during reading. Operate. Since the intermediate potential precharge circuit precharges the potential of the wiring to an intermediate potential that increases the gain of the reading means, the reading means that senses the potential of the wiring quickly outputs data in accordance with the data. Further, in another semiconductor memory of the present invention, since a clamping means is provided between the nodes, the potential of the node provided with the clamping means has a small swing width. Therefore, since the swing width becomes smaller, the equalization time becomes shorter, and as a result, high-speed reading becomes possible. [Example] A preferred example of the present invention will be described with reference to the drawings. First Embodiment This embodiment is an SRAM and has a circuit configuration as shown in FIG. The SRAM of this embodiment has a plurality of memory cells 10, some of which are shown in the figure and others omitted.The memory cells 10 are arranged in a matrix, and each row is connected to a decoder (not shown). The selected word line WL is selected by the selected word line WL. Each memory cell 10 consists of a flip-flop circuit and an access transistor in which the input terminal and output terminal of a pair of inverters (not shown) are connected to each other. A pair of bit lines 11.12 are connected to each column of memory cells 10, and a common bit line pair 11.12 is used for memory cells 10 in the same column. At the terminal ends of these via lines 11 and 12, pMOS transistors 13 and 14 are provided as bit line load circuits. Ground voltage is applied to the gates of the pMOS transistors 13 and 14, and data destruction is prevented by pulling up the bit lines 11 and 12 with an appropriate load. A data line 56 is connected to such bit lines 1.1.12 via column selection transistors 15-18. Note that a plurality of bit lines are connected to the pair of data lines 5.6, but for selecting the 0 column, which is omitted in the figure,
nMO5) transistor 15 and pMOs) transistor I6
and pM. A set of S transistor 17 and nMOS transistor 18 is connected between bit line 11 and data vA5 and between bit line 12 and data!, respectively. 116. A column selection signal Y is supplied to the gates of the nMO5) transistors 15 and 18, and a column selection signal Y having a level opposite to that of the column selection signal Y is supplied to the gates of the pMOS transistors 16 and 17. Therefore, when the column selection signal Y becomes high level, that column is selected. In addition,
Column selection signal Yy is supplied from a column decoder (not shown) in response to an address signal. The pair of data lines 5.6 are connected to a data line load circuit 1 indicated by a broken line in the figure, and are controlled to a predetermined potential by this data line load circuit 1. In the SRAM of this embodiment, the data line load circuit 1 is composed of a write recovery circuit 2, an intermediate potential precharge circuit 3, and a control circuit 4 for these. The write recovery circuit 2, as described later,
It operates at the end of writing and has a function of pulling up the potentials of the data lines 5 and 6. Further, the intermediate potential precharge circuit 3 operates during reading and precharges the potentials of the data lines 5 and 6 to a potential at which the sense amplifier 7 has a large gain. The control circuit 4 is a circuit for switching and controlling which of the write recovery circuit 2 and the intermediate potential precharge circuit 3 is activated, and is, for example, an ATD.
These switching operations are performed based on a precharge signal from a circuit (address transition detection circuit), etc., and a write enable signal WE. Furthermore, data from a write buffer (not shown) is supplied to the pair of data lines 5.6 via MOS transistors 19 to 22 that function as write control switches. pMOs transistor 21 and nMO5
A data signal is supplied to the data line 6 via the transistor 22, and a signal of the opposite voltage to the data signal is supplied to the data line 5 via the PMO5) transistor 20 and the nMO5) transistor 19. pMOs) Ranjisk 20.2
A write enable signal WE is supplied to the gate of nMO3 transistor 19.22, and a write enable signal WE is supplied to the gate of nMO3) transistor 19.22. A sense amplifier 7 is further connected to the pair of data lines 5.6.
is connected. This sense amplifier 7 has a function of amplifying the potential difference appearing between the pair of data lines 5 and 6. Also,
The sense amplifier 7 is supplied with an equalization signal ΦEQ and performs necessary equalization. The output of the sense amplifier 7 is sent to the output circuit 23, and data is read from the output circuit 23. Next, a specific circuit configuration of the data line load circuit 1 will be explained with reference to FIG. First, the write recovery circuit 2 is composed of three PMOS transistors 31, 32, and 33. The sources of the transistors 31 and 32 (pMOs) are supplied with the power supply voltage Vcc, and the data lines 5 and 6 are connected to their respective drains. Further, the pMOS transistor 33 has one source and drain connected to the data line 5 and the other source and drain connected to the data line 6. These p
A signal from the control circuit 4 is supplied to the gates of the MoS transistors 31 to 33. This write recovery circuit 2
The signal that activates is also generated during a write operation or during a precharge period immediately before a read operation begins after a write operation is completed. Note that the configuration of the write recovery circuit 2 itself is the same as that of a conventional data line load circuit (see FIG. 7), and the period during which it is activated is different in this embodiment. The intermediate potential precharge circuit 3 includes two pMOS transistors 34 and two nMOS transistors 35.3.
6 and an inverter 37. The pMOS transistor 34 is a transistor for balancing the data M56, and the two nMOS transistors 35.3
Reference numeral 6 denotes a transistor for pulling down the potential of the data lines 5 and 6 to an intermediate potential. Here, the intermediate potential is the potential at which the sense amplifier 7 has the highest sensitivity. For example, when the voltage flt voltage Vcc and the ground voltage GND are used to operate the sense amplifier 7, the intermediate potential is set to Vcc/2, which is half of the power supply voltage Vcc. nMO5) A signal from the control circuit 4 is input to the gates of the transistors 35 and 36 via the inverter 37. Further, the signal from the control circuit 4 is transmitted to the pMOSMOS
It is also supplied to transistor 34. Therefore, each MOS transistor 34 is controlled by a signal from the control circuit 4.
.about.36 may become conductive all at once. The intermediate potential precharge circuit 3 is activated when continuous read operations are performed, or in other words, when the write recovery circuit 2 is not activated. During reading, the potentials of the data lines 5 and 6 are raised to near the power supply voltage Vce due to charging by the PMO3I transistors 13 and 14, which are load transistors of the bit lines 11 and 12. Therefore, the nMOS transistors 35 and 36 become conductive, thereby lowering their potential to an intermediate potential. The control circuit 4 is a circuit for controlling switching between the write recovery circuit 2 and the intermediate potential precharge circuit 3. This control circuit 4 consists of two two-man powered NAND circuits 38.3
9 and an inverter 40. Two NAND circuits 3
8.39 is supplied with a precharge signal ΦP that provides precharge timing in the form of a pulse. Further, another input terminal of the NAND circuit 39 is supplied with a write enable signal WE. A write enable signal WE is supplied to the other input terminal of the NAND circuit 38 via an inverter 40. Here, the write enable signal WE becomes a low level during a write operation, and becomes a high level during a read operation. Therefore,
During a read operation, the NAND circuit 39 side outputs a control signal for the intermediate potential precharge circuit 3 at the timing of the pulse of the precharge signal ΦP, and conversely, during a write operation, the NAND circuit 38 side outputs a control signal for the intermediate potential precharge circuit 3 at the timing of the pulse of the precharge signal ΦP. A control signal for the write recovery circuit 2 is output at the timing of . Next, a specific circuit of the sense amplifier 7 will be explained with reference to FIG. The sense amplifier 7 is a so-called static type sense amplifier, and is composed of two differential amplifiers. One differential amplifier is configured by a current mirror-connected pMOS transistor 41, nMOS transistors 43 and 44 whose gates are supplied with an input signal, and an nMOS transistor 49 that functions as a constant current source and a switch, and is current mirror connected. PMOS transistor 4
5.46, an nMO3 transistor 47.48 whose gate is supplied with an input signal, and an nMOS transistor 49 which functions as a constant current source and a switch constitute another differential amplifier. Data line 5 is nMOS transistor 43
．． 48, and the data line 6 is connected to nMO5) transistors 44 and 47. Further, the nMOS transistor 47 is supplied with a sense amplifier first bull signal SE for operating the sense amplifier 7 only for a predetermined period. In this sense amplifier 7, the gate potential of the input nMOS transistor is set to ■. If the potential difference between the data lines 5 and 5 is ΔV, the rate of change in the gate potential of the input nMO transistor 5) can be expressed as Δv/vas. Therefore, the gate potential of the nMO5) transistor for input. from Vcc as in the conventional case to Vc as in this embodiment.
By setting it to c/2, since Δ■ is substantially constant, a rate of change approximately twice is obtained, which is approximately twice the change in the conductance of the input nMO3) transistor. Therefore, the sense amplifier 7 can obtain a large gain, and the sense amplifier 7 can operate at high speed. Next, referring to FIG. 4, the SRA of this embodiment will be described.
The operation of M will be explained. First, in a write operation, the write enable signal WE(
(a) in FIG. 4 is set to a low level as shown by the broken line. In this state, it is assumed that the address signal (0 in FIG. 4)) changes at time t1. Such a transition of the address signal is detected by the ATD circuit, and as a result, a pulse is generated in the precharge signal ΦP ((C) in FIG. 4) at time L2. At the stage before this time L2, if the previous cycle is a write cycle, the level DD of the pair of data lines 5 and 6 is almost at full swing, as shown in (fl in FIG. 4). The potential difference Δ is on. And the time

A pulse is generated in the precharge signal ΦP at [, and this pulse is supplied to the NAND circuits 38 and 39. Then,
Since the write enable signal WE is at a low level, only the NAND circuit 38 is activated, the output of the NAND circuit 39 remains at a high level, and the NAND circuit 83 is activated.
B's output changes to low level. That is, only the write recovery circuit 2 enters the operating state, and the intermediate potential precharge circuit 3 does not operate. As the output of the NAND circuit 38 changes to low level, the pMO5) transistors 3], 32 of the write recovery circuit 2
．． 33 changes to a conductive state. As a result, the potential difference Δ between the data lines 5.6 through the pMO5) transistor 33,
At the same time, pMO5) transistor 32,
33, the levels D and D of the pair of data lines 5 and 6 are raised to near the power supply voltage Vcc. Subsequently, at time t, the level of the precharge signal ΦP returns to a low level, and as a result, the operation of the write recovery circuit 2 is stopped by a signal from the control circuit 4. Further, around the timing of ill t s, the potential of a certain word line WL ((8) in FIG. 4) changes from a low level to a high level by a row decoder (not shown). Then,
The access transistor of the selected memory cell 10 is turned on and the flip-flop circuit within the memory cell 10 is connected to the data line 5.6 via the bit line 11.12. Here, as mentioned above, data lines 5.6. The potentials of bit lines 11 and 12 are pulled up to near power supply voltage Vcc. Therefore, data destruction is prevented when the memory cell 10 is accessed, especially when the write operation is completed and the read operation is switched (during write recovery). In order to ensure operation during write recovery, it is also possible to combine a delay circuit, a logic circuit, etc., and operate the write recovery circuit 2 based on the result of detecting the transition of the write enable signal WE. The writing means operates before and after the timing of selecting the word line WL, and during writing, the MOS as a switch is activated.
) Since the transistors 19 to 22 are all in the on state, a potential difference Δ is created between the pair of data lines 5.6 according to the data to be written. The potential difference Δ1 of this data line 5.6, which will be applied earlier, is applied to the bit line 11.12 as it is.
The data is transmitted to the memory cell 10 via the memory cell 10, and the data in the flip-flop circuit of the memory cell 10 is left unchanged or inverted. Next, when reading data, the write enable signal WE ((a) in FIG. 4) is set to a high level as shown by the solid line. The address signal ((b) in FIG. 4) transitions at time L1, which is detected by the ATD circuit, and a pulse is generated in the precharge signal ΦP ((c) in FIG. 4) at time L2. As a result, the equalization signal ΦEQ ((d) in FIG. 4) which is also supplied to the sense amplifier 7 at time t2
) also generates a pulse. At the stage before time t, if the previous cycle is a read cycle, the level DD of the pair of data lines 5.6 is equal to the power supply voltage Vcc, as shown in FIG. 4(e).
The potential difference Δ is at a level close to . Then, at time t2, a pulse is generated in the precharge signal ΦP, and this pulse is supplied to the NAND circuits 38 and 39. Then,
Since the write enable signal WE is at a high level, only the NAND circuit 39 is activated and the output of the NAND circuit 39 is turned to a low level, contrary to the write operation (including during ride recovery). That is, only the intermediate potential precharge circuit 3 operates, and the write recovery circuit 2 does not operate. In this intermediate potential precharge circuit 3, the NAND circuit 3
When the signal from 9 becomes low level, pMO3) transistor 34 becomes conductive, equalizing the pair of data lines 5 and 6. In addition, n via the inverter 37
A high level signal is input to the gates of MO5) range transistors 35.36, and these nMOS transistors 35.
36 becomes conductive. As a result, the levels D and D of the data line 5.6 are set between the power supply voltage Vcc and the ground voltage GND by resistance division between the bit line load pMO transistor 13.14 and the nMOS transistor 35.36. It will be precharged to intermediate potential Vcc/2. Further, by generating a pulse in the equalization signal ΦEQ, the dual-end sense amplifier 7 is also equalized. The output signal SA2. of the sense amplifier 7 shown in (5) in FIG. SAt is balanced by the equalization signal ΦEQ. Next, at time t3, the pulse generation of the equalize signal ΦEQ and the precharge signal ΦP is stopped, and in the data line load circuit 1, the operation of the intermediate potential precharge circuit 3 is stopped. In accordance with this timing, the word line W+ is selected by a row decoder (not shown), and its potential changes from a low level to a high level as shown in FIG. , the access transistor of the selected memory cell 10 becomes conductive, and the drive transistor forming the flip-flop circuit first creates a potential difference between the pair of bit lines 11.12, and correspondingly, a potential difference also appears on the data line 5.6. A potential difference occurs.At this time,
The potential difference that occurs between the pair of data lines 5.6 is because the data line 5.6 has already been precharged to the intermediate potential Vcc/2 as described above, so a potential difference occurs near the intermediate potential Vcc/2. I will do it. This intermediate potential Vcc/
2, a large gain of the sense amplifier 7 can be obtained, and therefore the output level SA of the sense amplifier 7 is
SAt will transition at high speed in response to data. As described above, in the SRAM of this embodiment, during continuous readout, the potential of the data line 5.6 is set to the intermediate potential at which the gain of the sense amplifier 7 increases, and the intermediate potential precharge circuit 3
It is precharged with. Therefore, the sense amplifier 7 can be sensed at high speed, and high-speed reading can be realized. At the same time, at the end of a write operation such as during write recovery, the write recovery circuit 2 operates and the data line 5
, 6 is pulled up. This prevents data from being destroyed during access. Second Embodiment The SRAM of this embodiment has a multi-stage dual-end sense amplifier, and a MOS transistor connected to a diode as a clamping means is formed at an intermediate output terminal, so that high speed operation is possible. This is an example of realizing readout. The main part is shown in Fig. 5. It should be noted that the portions of this embodiment other than those shown in FIG. 5 have the same configuration as that shown in FIG. 1, and their explanation will be omitted here for the sake of brevity. FIG. 5 shows the circuit configuration of the sense amplifier 7. The differential amplifiers 51 and 52 constitute the first stage dual-end sense amplifier, and the differential amplifiers 53 and 54 constitute the next stage dual-end sense amplifier. be done. The differential amplifier 5152 that constitutes the first stage sense amplifier is
A pair of data lines 5, 6 are connected to the input terminal. One data line 5 is connected to one input terminal of a differential amplifier 51 and one input terminal of a differential amplifier 52 . The other data line 6 is connected to one input terminal of the differential amplifier 51 and to the tenth input terminal of the differential amplifier 52. An equalizing pMOS transistor 57 is connected between the output terminals of the differential amplifiers 51 and 52, and a clamp circuit 50 is also provided. pMO
s) An equalization signal ΦE is applied to the gate of the transistor 57.
Q is supplied, and this equalize signal ΦEQ causes pM
Os) ON/OFF of the transistor 57 is controlled. The clamp circuit 50 includes a pair of nMO3) transistors 55.5
Consists of 6. The source of the nMOS transistor 55 is connected to the output terminal of the differential amplifier 51, and the gate and train of the nMOS transistor 55 are connected to the output terminal of the differential amplifier 52. The source of the nMO3) transistor 56 is connected to the output terminal of the differential amplifier 52, and the gate and drain of the nMOS transistor 55 are connected to the output terminal of the differential amplifier 51. These nMOS transistors 55
56 respectively function as diodes, the level of the output terminals of the differential amplifiers 51 and 52 is the same as that of the nMO.
The potential difference can be suppressed to within the dark value voltage vth of the s transistor. In addition, the input of the sense amplifier usually has sufficient gain if there is a certain potential difference, so the dark value voltage V
1. Even if the potential difference is suppressed to within h, no problem will occur. The output terminal of the first-stage sense amplifier provided with the lamp circuit 50 is further provided with a next-stage sense amplifier. The sense amplifier in the next stage also consists of differential amplifiers 53 and 54 like the first stage, and the output terminal of the differential amplifier 5 is connected to the input terminal of the differential amplifier 53 and the input terminal of the differential amplifier 54. , the differential amplifier 52 is connected to one input terminal of the differential amplifier 53 and ten input terminals of the differential amplifier 54.
output terminal is connected. And between the two output terminals of this next-stage sense amplifier, there is also a pMO for equalization.
s) A transistor 58 is formed, and this PMOS transistor 58 receives an equalization signal ΦE input to its gate.
Controlled by Q. The two output terminals of the sense amplifier in the next stage are connected to the output circuit 23.
The read data will be outputted via 3. Next, the operation of the SRAM sense amplifier of this embodiment will be explained with reference to FIG. 6, with the output of the sense amplifier in the first stage being signal 5ASA, and the output of the sense amplifier in the next stage being signals SA, SAt. explain. In the SRAM of this embodiment, as shown in FIG. 6(d), the output signals SA, , SA of the first stage sense amplifier. The difference between them is determined by the clamp circuit 50 as a potential difference ΔVCLP ('=
:Dark value Dark value voltage is suppressed within the Vt plate. Therefore, high-speed reading is possible. That is, first of all, in the previous read cycle the diode-connected pMOS transistors 55, 56
Due to the operation of , the output signal S A of the first stage sense amplifier
Suppose that the potential difference between + and S A + is ΔV CLP. At this time, the sense amplifier at the next stage has a sufficient gain, so that its output signal SA 2.3 A t has a potential difference close to a full swing. At this stage, the address signal ((a) in FIG. 6) is
21, and as a result, the equalize signal ΦEQ (sixth
Assume that the pulse shown in (b) in the figure occurs at time tzz. The equalizing signal ΦEQ activates the equalizing PMOS transistors 57 and 58, and output signals SA, , SA, and output signals SAA are activated. The potential difference of SA2 is eliminated. At this time, the potential difference between the output terminals of the first-stage sense amplifier was suppressed to ΔV CLP by the operation of the clamp circuit 50.
Equalization is completed quickly, and at time t31, the potential difference between the two has already disappeared. In this way, in the SRAM of this embodiment, the potential difference between the output terminals of sense amplifiers that are not in the final stage is suppressed to within a certain value △V eLP, so equalization in the next cycle can proceed at high speed, and the overall Readout time can also be shortened.
:Become. Next, at time tzs, the generation of pulses of the equalize signal ΦEQ is stopped, a word line is selected at that timing, and the data of the selected memory cell is precharged to, for example, Vcc/2 via the focus line. It appears at level DD of data 15.6 ((C) in FIG. 6). Then, due to the potential difference, a potential difference occurs between the output signals SA, , SA of the first stage sense amplifier from time tsz, and as a result, the output signal S of the next stage sense amplifier
A potential difference also occurs at AzSA. And time L3
3, the potential difference between the output signals SA, SA of the first-stage sense amplifiers reaches ΔV CLP, but after that, only the forward current flows in the pMO3) transistor 5556 of the clamp circuit 50, and the potential difference of ΔVC1,P or more No potential difference occurs at the output terminal of the dual-ended first-stage sense amplifier. As described above, in the SRAM of this embodiment, a clamp circuit 50 is provided between the pair of sense amplifiers (output terminals) before the last l, and this clamp circuit 50 keeps the potential difference between the pair of nodes constant. It can be suppressed to within the value ΔV eLP. Therefore, the equalization time can be shortened and high-speed reading can be achieved. Note that in the above embodiment, the number of stages of the sense amplifier is 2.
Although the sense amplifier has three stages, the sense amplifier may have three stages, four stages, or even more stages. Furthermore, in this embodiment, the clamp circuit 50 is connected to two nMO
5) Although the transistors 55 and 56 are used, it is also possible to use pMOS transistors. [Effects of the Invention] As described above, in the semiconductor memory of the present invention, the write recovery circuit operates during writing, particularly during write recovery, and the intermediate potential precharge circuit operates during reading. Since the intermediate potential precharge circuit precharges the potential of the wiring to an intermediate potential that increases the gain of the reading means, the reading means can sense data at high speed, and high-speed reading is realized. Further, in another semiconductor memory of the present invention, since a clamping means is provided between the nodes, the potential between the pair of nodes is suppressed to a certain value or less. Therefore, a high-speed equalization operation, etc. can be performed, and high-speed reading can be performed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a semiconductor memory of the present invention, Part 2 is a circuit diagram of a data line load circuit of that example, FIG. 3 is a circuit diagram showing an example of the sense amplifier of the above example, and FIG. is above −
FIG. 5 is a timing chart for explaining the operation of the example; FIG. 5 is a circuit diagram showing another example of the semiconductor memory of the present invention; FIG.
FIG. 7 is a circuit diagram showing an example of a conventional semiconductor memory, and FIG. 8 is a timing chart explaining the operation of an example of the conventional semiconductor memory. It is. 1...Data line load circuit 2...Write recovery circuit 3...Intermediate potential precharge circuit 4...Control circuit 5.6...Data line 7...Sense amplifier 10...Memory cell 11.12...Focus line 13.14...PMOS transistor 50...Clamp circuit 51-54...Differential amplifier 55.56...pMO5) Transistor Patent applicant
Sony Corporation Representative Patent Attorney Akira Koike (and 2 others) Morohizuki no Yai Todoromoto x Mo, Rime example se] Sufu> 7° of the fairy tale 3rd figure ther / 7 sure - 1 times fart cut - still J Fig. 2 EAD Taimi〉1000 Yards Fig. 4 Ise 2 Shishi Pumepi and 43-'' Fig. 5 Taimi〉Guchi 7-to Fig. 6

Claims (2)

[Claims] (1) A plurality of memory cells, a pair of wires respectively connected to the memory cells, a writing means for writing information into the memory cells via the wires, and a write means for writing information into the memory cells via the wires; a reading means for reading information; a write recovery circuit that applies a potential to prevent data destruction to the pair of wirings at least when the writing operation by the writing means ends and switching to a reading operation; and an intermediate potential precharge circuit for precharging the pair of wirings to an intermediate potential whose gain is greater than other potentials. (2) A semiconductor memory having multi-stage dual-end sense amplifiers, characterized in that clamping means is provided between nodes serving as a pair of sense amplifiers before the final stage.