JPH04609Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a 1-magnification scanner equipped with a reading head in which a plurality of line image sensors are arranged in a staggered manner.

[Prior Art] In general, a scanner provided as an image input means in a facsimile device etc. inputs an image on a main scanning line using one line image sensor, for example.
The image is projected onto a CCD (charge-coupled device) line sensor for photoelectric conversion.

In many cases, the longitudinal dimension of this line image sensor is approximately one-eighth of the length of the main scanning line.
Because it is quite short, a lens system is required to project the image on the main scanning line onto the line image sensor, and an optical path length of about 300 mm must be secured for image formation. In this case, a large amount of space is required for this reading system, making it difficult to downsize the scanner and hindering the downsizing of facsimile machines and the like.

Therefore, in order to solve this inconvenience,
In recent years, full-size scanners have been put into practical use.

This same-size scanner is equipped with a reading head that has a scanning width that is the same length as the main scanning line and has cells that are approximately the same size as pixels. It is something that is projected onto. Therefore, since an optical path for reducing the image is not required, the distance between the document and the reading head can be shortened (for example, about 20 mm), and the scanner can be configured in a compact size.

By the way, the resolution of the image in the main scanning direction is, for example, 8 dots/mm (the resolution of a typical G facsimile machine), and if the reading width of a standard A4 size document is 216 mm, then the pixels per main scanning line are The number is 1728.

Therefore, a line image sensor such as a CCD (charge-coupled device) line sensor, which has 1728 light-receiving cells of about 0.1 mm square arranged at equal intervals over a width of 216 mm, may be used as the reading head. Since such line image sensors are expensive, conventionally a reading head 1 is used in which a plurality of line image sensors are arranged in a staggered manner to increase the reading width as shown in FIG.

The reading head 1 is formed by arranging four line image sensors C1 to C4 in a staggered manner while overlapping each other by a predetermined length. It is off by l.

The line image sensors C1 to C4 are driven by clock drivers DR1 to DR4 of the read head drive section 2, and the output signals thereof are subjected to direct current components removed by DC regenerative amplifier circuits AP1 to AP4, peak hold circuits, Analog/digital converter (hereinafter referred to as A/D converter), random access memory (hereinafter referred to as RAM), and digital/digital converter (hereinafter referred to as A/D converter), random access memory (hereinafter referred to as RAM),
They are respectively added to shading correction circuits SA1 to SA4 each consisting of an analog converter (hereinafter abbreviated as a D/A converter). Note that the clock generator 3 outputs a reference clock signal to the clock drivers DR1 to DR4.

These shading correction circuits SA1 to SA4 are
The line image sensors C1 to C4 are
The variation in the output signal corresponding to each light-receiving cell is corrected.

That is, first, before actually reading the image information of the original, a reference white portion of the original pressure plate or the like is read by a line image sensor, and the peak time of the output signal of the line image sensor at this time is held in a peak hold circuit.

Next, the output signal of this peak hold circuit is given to the A/D converter as a reference signal, the reference white part is read again in this state, and the output signal corresponding to each light receiving cell of the line image sensor at this time is sent to the A/D converter. The converter converts digital signals (e.g. 4
bit) and store this digital signal in RAM.

As a result, data corresponding to each light-receiving cell when the line image sensor reads the reference white portion is stored in the RAM.

Then, at the stage of actually reading the image information of the original, the data read out from the RAM corresponding to each light receiving cell is converted into an analog signal by a D/A converter, and this analog signal is sent to the A/D converter. The output signal of the line image sensor corresponding to each light receiving cell is sent to the A/D while being given as a reference signal.
Convert it to a digital signal using a converter. The digital signals AD1 to AD4 at this time are outputted to the next stage circuit as output signals of the line image sensors C1 to C4.

In this case, the output signal of the peak hold circuit is given as the reference signal of the D/A converter, and the output signal of the address counter 4 is used as the reference signal of the D/A converter.
RAM address is specified.

In this way, the output analog signal of each line image sensor is converted into a digital signal based on the all-white level for each light-receiving cell, so that variations in the output signal for each light-receiving cell are corrected.

Now, since the line image sensors C1 and C3 are in the leading position, the digital signals AD1 and AD
3 is added to the delay circuit 5 and delayed by the number of main scanning lines corresponding to the length l.

Therefore, the output signal AD1' of the delay circuit 5,
AD3' and signals AD2 and AD4 correspond to the same main scanning line.

These signals AD1', AD2, AD3', AD4
One main scanning line segment is stored in the buffers 6 and 7, and then sequentially read out so that the signals are appropriately continuous at the overlapping portions of each line sensor.

These buffers 6 and 7 have a so-called double buffer function, and when one is in a data write state, the other is in a data read state, thereby realizing high-speed data transfer processing. Therefore, the operating speed of the read counter 8 for reading data is set to four times the operating speed of the write counter 9 for writing data.

The output signals of the buffers 6 and 7 are outputted as image data DG to the next stage device (MTF correction circuit, halftone conversion circuit, etc.) via the output section 10.

The threshold level designator 11 is operated by the user according to the density of the document, and its output signal changes the partial pressure ratio of the reference signal in the A/D converter, and as a result, each shading correction The output signals of the A/D converters of circuits SA1 to SA4 change at the same rate.

Although such a conventional device has a high data transfer speed, it requires buffers 6 and 7, a read counter 8, and a write counter 9, and therefore requires one shading correction circuit for each line image sensor. Therefore, the structure is complicated and the cost is extremely high.

[Purpose] The present invention was devised to eliminate the drawbacks of the prior art described above, and it divides line image sensors into two groups: those that read the preceding main scanning line and those that do not. The object of the present invention is to provide a 1x scanner that allows a group to share a shading correction circuit, thereby significantly reducing costs.

[Structure] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows an embodiment of the present invention.

In the same figure, line image sensors C1 and C
3 is a start pulse SH1 output from clock drivers DR11 and DR13 (see Figure 3k)
The line image sensors C2 and C4 are driven simultaneously by the clock drivers DR12 and DR1.
Driving is started at the same time with a start pulse SH2 (see FIG. 3, 1) output from 4.

The output signal of the DC regenerative amplifier circuit AP1, that is, the output signal of the line image sensor C1 (see Figure 3a), is applied to the analog switch AS1 and the peak hold circuit PH1, and the output signal of the DC regenerative amplifier circuit AP1 is applied to the analog switch AS1 and the peak hold circuit PH1.
The output signal of AP2, that is, the output signal of line image sensor C2 (see FIG. 3b) is applied to analog switch AS2 and peak hold circuit PH2, and the output signal of DC regenerative amplifier circuit AP3, that is, the output signal of line image sensor C3 (see FIG. 3b) is applied to analog switch AS2 and peak hold circuit PH2. Third
(see Figure 3) is applied to the analog switch AS1 and the peak hold circuit PH3, and the output signal of the DC regenerative amplifier circuit AP4, that is, the output signal of the line image sensor C4 (see Figure 3 d) is applied to the analog switch AS2 and the peak hold circuit PH3. PH
Added to 4.

Analog switch AS1 is a DC regenerative amplifier circuit.
The output signal of AP1 or AP3 is switched and applied to the shading correction circuit SA11, and the output signal of the peak hold circuit PH1 or PH3 is switched and applied to the shading correction circuit SA11.

Analog switch AS2 is a DC regenerative amplifier circuit.
The output signal of AP2 or AP4 is switched and applied to the shading correction circuit SA12, and the output signal of the peak hold circuit PH2 or PH4 is switched and applied to the shading correction circuit SA12.

The timing generator 21 generates signals SC1 (see FIG. 3e) and SC2 at predetermined timings.
(See Figure 3 f) and output the analog switch.
AS1 and AS2 are switched and operated, whereby the output signals of line image sensors C1 to C4 are sequentially outputted via shading correction circuits SA11 and SA12.

The output signal of the shading correction circuit SA11 is delayed by a predetermined number of lines via the delay circuit 5,
The signal AD11 (see Figure 3g) is applied to one input terminal of the gate circuit 22, and the output signal AD12 of the shading correction circuit SA12 (see Figure 3h) is applied to one input terminal of the gate circuit 22.
is applied to the other input terminal of the gate circuit 22.

In addition, the timing generator 21 outputs a signal SC3 at a predetermined timing (see Figure 3 i).
is applied to the signal AD12 selection input terminal of the gate circuit 22, and a signal obtained by inverting this signal SC3 by the inverter 23 is applied to the signal AD12 of the gate circuit 22.
11 selection input terminal.

As a result, as shown in FIG. 3J, continuous image data DG is output from the gate circuit 22 at each overlapping portion of the line image sensors C1 to C4.

Note that the RAM of the shading correction circuits SA11 and SA12 in this embodiment requires a capacity capable of storing image signals for two line image sensors. In addition, the shading correction circuit SA11,
Since SA12 includes peak hold circuits PH1 to PH4, it performs the same function as the shading correction circuits SA1 to SA4 shown in FIG. 1, so a description thereof will be omitted. Similarly, in FIG. 2, parts that are the same or equivalent to those in FIG.

In this way, the line image sensor C1~
The output signal of C4 is continuous in the overlapping portion and is output as image data on one main scanning line.

In addition, switching between analog switches AS1 and AS2 is performed when these analog switches AS1 and AS2 are ineffective, so the DC regenerative amplifier circuit AP
The output signals of AP1 to AP4 are not affected by noise during switching.

[Effects] As explained above, according to the present invention, only two sets of shading correction circuits are required, and no special elements are required, so the advantage is that it is possible to realize a 1x scanner with significantly reduced costs. have

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional example of a same-magnification scanner, Fig. 2 is a block diagram showing an embodiment of the present invention, and Figs. 3 a to 1 are waveforms showing the operation of the main parts of Fig. It is a diagram. 1...reading head, 2...reading head drive section,
3... Clock generator, 4... Address counter, 21... Timing generator, 22
...Gate circuit, 23...Inverter, AS1,
AS2...Analog switch, DR11 to DR14
...Clock driver, PH1 to PH4...Peak hold circuit, SA11, SA12...Shading correction circuit.

Claims (1)

[Scope of utility model registration request] A plurality of line image sensors are arranged in a staggered manner, and the output signal of each line image sensor is corrected for shading, and the signal of the line image sensor whose reading position is ahead is delayed by a predetermined number of lines to correspond to one reading line. In a same-magnification scanner that outputs an image signal, a first selection means for selecting an output signal of one line image sensor from a first group consisting of those having a preceding reading position among the plurality of line image sensors; A second method for selecting an output signal of one line image sensor from a second group consisting of a plurality of line image sensors other than those whose reading positions are preceding.
selection means, and first and second shading correction means for shading correction of the output signals of the first and second selection means, and sequentially starts driving the plurality of line image sensors at a predetermined timing, The second switching means is activated when any of the line image sensors forming the first group is being driven; and when any of the line image sensors forming the second group is being driven; A life-size scanner characterized in that the first switching means is activated.