JPH0460864A - Communication register multiplexing system - Google Patents

Abstract

PURPOSE:To multiplex parallel processing more than physical communication register through a time division system by using the physical communication registers of only the same number as the number of processors by controlling the physical communication register and a logical communication register on a memory to hold the image of the physical communication register as occasion demands. CONSTITUTION:A logical communication register initializing means 11 to make all the logical communication registers into an idle state, a logical communication register securing means 12 to take out one of the logical communication registers in the idle state and make it into a usable state, a logical communication register change-over means 13, a logical communication register releasing means 14 to return the logical communication register after use to the idle state, and a physical communication register initializing means 15 to turn all the physical communication register to the idle state are provided. Further, a physical communication register securing means 16 to take out one of the physical communication registers and turn it to the usable state and a physical communication register change-over means 17 to change a communication register to the designated physical communication register are provided. Thus, the parallel processing more than the physical communication registers is multiplexed by the time division system by using the physical communication register of the actually existing communication register of only the same number as the number of processors.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is used in an operating system of a multiprocessor system that enables parallel processing of user programs, and when allocating communication registers to each user program that performs parallel processing. This invention relates to a communication register multiplexing method.

(Prior Art) Parallel processing of user programs is realized by simultaneously assigning a plurality of processors to one user program according to the requests of the user program. However, each processor cannot operate completely independently from beginning to end. This is because there is a dependency relationship between the data handled by each processor. Here, it becomes necessary to control synchronization between processors.

In parallel processing with small granularity, the time required for synchronization control between processors becomes closer to the time required to process program parts that can operate in parallel without synchronization. If the time required for synchronous control becomes longer, the time required for synchronous control becomes dominant in the overall program execution time.

In other words, even if a program is parallelized to a certain extent, the overhead of synchronization control will eat up the effect of parallelization because the number of times synchronization control will increase, and performance will hardly improve. The degree of granularity in which parallelization improves performance depends on the time required for synchronous control of the system. The shorter this time, the more effective parallelization down to finer granularity becomes. Therefore, in order to perform faster parallel processing, it is necessary to reduce the time required for synchronization control between processors as much as possible.

In a normal system, an operating system (hereinafter abbreviated as O8) is in charge of synchronization control between processors. When performing synchronous control, the processor
A call (called a supervisor call, system call, etc.) is made to call the part that implements synchronous control inside O8. However, in this method, no matter how fast the part that performs synchronous control operates, the OS call simultaneously performs other operations such as billing control, so the process as a whole takes a considerable amount of time.

Therefore, in order to reduce the time required for synchronous control as much as possible, a method was devised to perform synchronous control using communication registers. In multiprocessor systems, each processor has a separate set of common registers. On the other hand, a communication register is a register that can be referenced by multiple processors. It can be thought of as a register version of shared memory. Access performance is faster than general shared memory, but slower than general registers. Koichi・
4. This is because exclusive control of access from multiple processors is required. Furthermore, its capacity is considerably smaller than that of shared memory, and is comparable in capacity to that of a general register. Access to the communication register is performed using a special instruction for communication register access.

Now, synchronization control using this communication register is performed as follows. One processor checks a bit in the communications register and repeats the check until that bit is turned on. This is called a spinlock. The other processor turns on that bit when a certain condition is met. The processor holding the spinlock can then proceed. The important point is that this communication register can be directly accessed by the user program (object of the -F module). In other words, there is no need to call O8 for synchronization control. For this reason, fairly high-speed synchronous control can be achieved. Note that this method can generally be implemented using a shared memory, but since a communication register is much faster than a shared memory, using a communication register enables faster synchronization control.

As the number of processors increases, a user program may want to perform multiple independent parallel processes at the same time. For example, when the scale of a parallel processing program becomes large and it is developed by dividing it into several partial programs, this requirement occurs.In large programs, some of the partial programs can also perform parallel processing. When each part that can be parallelized is parallelized, the result is that another parallel process is performed within one parallel process. This is called multiplexing of parallel processes. Multiplexing of parallel processes is This occurs when one program that is part of a parallel process starts another parallel process.When such parallel processes are multiplexed, independent synchronization control is required for each parallel process. Since it is advantageous to have faster synchronization control for each parallel process, I would like to use communication registers if possible.However, in order to achieve this, separate communication register areas are required for each parallel process.Parallel As the degree of multiplicity of processing increases,
It will no longer fit in one set of communication registers. In addition, work is required to allocate an area on the communication register to each parallel process. In this way, when multiplexing parallel processing using communication registers, it is necessary to solve the problem of capacity and allocation of communication registers.

A hardware system shown in FIG. 13 has been proposed as a communication register that takes into account the multiplexing of parallel processing as described above. The number of communication registers is the same as the number of processors. Each processor 130 has a communication register 13 that it can access.
2 can be selected using the selector switch 131. Conversely, it is possible to know which communication register the device is currently connected to.

This function to know the connection communication register is possible by storing the information when switching the communication register.
This can also be achieved with software. If hardware such as that shown in FIG. 13 is used, it is not difficult to provide separate communication registers for each set of processors. When assigning one parallel process to a certain set of processors, a changeover switch may be operated so that all processors in the set can refer to the same communication register. However, it is necessary to allocate a communication register separate from other parallel processing. Parallel processing communication register access does not require operation of a changeover switch, so performance does not deteriorate. In this method, the capacity of the communication register is increased by preparing communication registers for the number of processors, and the problem of communication register allocation is solved by allocating a separate communication register for each parallel process. In other words, one set of dedicated communication registers can be secured for each parallel process.

(Problems to be Solved by the Invention) A method of simply allocating communication registers from a number of processors to each parallel process has a limit to the effective use of system resources. For example, a certain processor that constitutes parallel processing may perform Ilo and wait for its completion. In this case, in the conventional method, the processor that issued Ilo ends up completely in a waiting state. Other processors that perform parallel processing in cooperation with this processor also
Although it can continue to operate for a while, it enters a waiting state at the time of synchronization control with the processor waiting for I10 to complete. Other parallel processing can be performed during these wait states. Therefore, multiplexing by time division becomes effective for multiplexing parallel processing.

In such time-sharing multiplexing of parallel processing, the O8 realizes program multiplexing by switching the programs executed by each processor depending on the situation. At this time, a series of processor operations within one parallel processing program is called a task (some systems call it a thread). In systems that do not use time-sharing multiplexing, a processor is assigned to each task at the beginning of the program, and processing continues in that state until the end. However, in the time-sharing method, when a task enters a waiting state such as waiting for I10, it is possible to execute another part of the program by switching the processor that was executing that task to another task. becomes. In this case, a set of parallel processing is performed as parallel operations of several tasks. Therefore, it is necessary to allocate a communication register to each set of tasks.

Now, in the multiplexing method of parallel processing that performs time division, there are cases where the number of tasks exceeds the number of processors configured in the system. Therefore, if you think about it simply, communication registers are also required because of the number of processors. The required number is the number of parallel processes that can be executed simultaneously. However, the execution referred to here also includes short-term waiting states such as waiting for I10.

In Figure 14, multiplexing of parallel processing will be considered in more detail. FIG. 14 shows a situation where three parallel processes A, B, and C are operating. A has two tasks 143, both of which are being executed by the processor 140. B has three tasks 143, two of which are running and the other is in a waiting state. Similarly C
has four tasks 143, and all tasks 143 are in a waiting state.There are three execution states for each parallel process depending on the combination of the execution states of each task 143. In other words, all tasks are executed (
A), one in which all tasks are in the waiting state (C), and one in which there are tasks in both states (B). At this time, one communication register 144 is actually allocated to parallel processing A, and each It needs to be accessible from task 143.

Similarly, parallel processing B also has one communication register 14.
4 is required. However, since the task 143 in the waiting state never accesses the communication register 144, if it is guaranteed that B's communication register 144 will be visible when it is executed again, the communication register 144 will actually be accessed.
It does not need to be connected to 4. Since parallel processing C does not execute any task 143, the physical communication register 144 is not required. However, when each task 143 starts execution again, the communication register 144 with exactly the same image must be visible. Although it is possible to use a physical communication register 144 as the communication register 144 of C, it is also possible to place it in a general memory as long as it can hold the contents. Keep the contents in memory.

When any task starts running, allocate the physical communication register 144, copy the contents held in memory to it, and then start the task! All you have to do is operate 43. The communication register for this parallel processing C is considered to be a virtual communication register 142.

Therefore, the communication register multiplexing method of the present invention uses the physical communication register, which is an existing communication register that only exists in the number of processors, and uses the physical communication register and the necessary The purpose of this is to control the logical communication register, which is a virtual communication register on the memory that holds the image.

(Means for Solving the Problems) The communication register multiplexing method of the present invention is a communication register multiplexing method used in the operating system of a multiprocessor system that enables parallel processing of user programs, and is a communication register multiplexing method that is used for virtual communication A logical communication register initialization means that makes all the logical communication registers that are registers empty, a logical communication register securing means that takes out one free logical communication register and makes it usable, and a communication register that is visible to the processor is specified. a logical communication register switching means for switching to a logical communication register that has been used; a logical communication register release means for returning a logical communication register that has been used to an empty state; and a physical communication register that turns all existing physical communication registers into an empty state. initialization means; physical communication register securing means that is called by the logical communication register switching means to take out one physical communication register that is in an empty state or a pending state and makes it usable; the logical communication register switching means and the logical communication register securing means; and physical communication register switching means that is called from register release means and switches a communication register visible to the processor to a specified physical communication register.

(Example) Next, the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the embodiment of the present invention includes a logical communication register initialization means 11 that makes all logical communication registers, which are virtual communication registers, empty, and takes out one empty logical communication register. logical communication register securing means 12 for making the logical communication register available for use; logical communication register switching means 13 for switching the communication register visible from the processor to a specified logical communication register; and logical communication register release means for returning the used logical communication register to an empty state. means 14, physical communication register initialization means 15 which makes all of the physical communication registers which are existing communication registers empty, and one physical communication register which is called from the logical communication register switching means 13 and is in an empty state or a pending state. Physical communication register securing means 16 that takes out and makes it usable, and physical communication register switching that is called by logical communication register switching means 13 and logical communication register release means 14 and switches the communication register visible from the processor to a specified physical communication register. It consists of means 17.

FIG. 2 shows the state transition of the physical communication register. Each physical communication register 20 is always in one of the following three states. That is, an empty state 21 that is not used by any processor regardless of the specific logical communication register;
A pending state 22 holds the contents of a specific logical communication register and is not used by any processor, and a used state 23 holds the contents of a specific logical communication register and is used by any processor. . The usage state 23 is further subdivided into N states from 1 in use to N in use (the number of processors). In this sense, zero pending state 22 can be considered to be in use. The pseudo communication register 24 in FIG. 2 is a virtual communication register which means that when a processor is connected to it, the processor is not connected to any communication register.

Therefore, similar control is possible without using this concept. The present invention will be explained using this concept for simplicity.

FIG. 3 is a flowchart showing the processing of the physical communication register initialization means 15. The physical communication register initialization means 15 registers all the physical communication registers in an empty state in step 31, sets N pseudo communication registers in use in step 32, and sets the changeover switch between the processor and the communication register in step 33. to make each processor disconnected from any communication register. If you are sure that the user will not access the communication register by mistake when the processor is associated with the pseudo communication register, you can leave an arbitrary connection instead of disconnecting the processor and the communication register. There is no problem even if you leave it there. This also applies to the subsequent scenes where the connection between the processor and the communication register is controlled.

FIG. 4 is a flowchart showing the processing of the physical communication register securing means 16. The physical communication register securing means 16 first searches for an empty physical communication register in step 41. If there is an empty physical communication register, in step 42 the physical communication register found in step 41 is changed to a pending state, and in step 43 the identifier of the physical communication register found in step 41 is changed to a pending state. Call it and pass it on. If there is no vacant physical communication register, a pending physical communication register is searched for in step 44. If there is a pending physical communication register, in step 43, step 4
The identifier of the physical communication register found in step 4 is called and passed to the source. If there is no pending physical communication register, in step 45, the identifier of the physical communication register connected to the processor at that time is detected;
In step 43, the identifier of the physical communication register detected in step 45 is called and passed to the source.

FIG. 5 is a flow chart showing the processing of the physical communication register switching means 17. In step 51, the physical communication register switching means 17 detects the identifier of the physical communication register connected to the processor at that time, and in step 52, the state of the physical communication register detected in step 51 is changed to n in use. (n-1> is changed while in use. Note that n is a number between 1 and N, and the value differs depending on the time. Next, in step 53, the physical communication register specified by the caller is changed. While using m states of (m+1>
change while in use. Note that m is a numerical value between 0 and (N-1), and varies depending on the time. Finally, in step 54, the processor is connected to the physical communication register specified by the caller.

FIG. 6 shows the state transition of the logical communication register.

Each logical communication register 60 is always in one of three states described below. That is, an empty state 61 that is not used by a specific task, an allocated state 62 that is used by some tasks but whose image is not loaded into a specific physical communication register, and an unused state 62 that is not used by some tasks. In-use state 63, where the image is being loaded into a particular physical communication register.

FIG. 7 is a flowchart showing the processing of the logical communication register initializing means 11. In step 71, the logical communication register initializing means 11 registers all the logical communication registers as empty.

FIG. 8 is a flowchart showing the processing of the logical communication register securing means 12. The logical communication register securing means 12 takes out one free logical communication register in step 81, changes the logical communication register taken out in step 81 to an allocated state in step 83, and changes the logical communication register taken out in step 81 to an allocated state in step 83. Calls the logical communication register identifier and passes it to the source.

FIG. 9 is a flow chart showing the processing of the logical communication register switching means 13. In step 91, the logical communication register switching means 13 checks whether the logical communication register specified by the caller is in use. If it is not in use, the physical communication register securing means 16 is called to take out the physical communication register in an empty or pending state, and in step 92, the physical communication register taken out by the physical communication register securing means 16 retains its image. Logical communications registers that are currently in use. If there is, in step 93, the contents of the physical communication register retrieved by the physical communication register securing means 16 are saved in the physical communication register retrieved in step 92, and in step 94, the contents of the physical communication register retrieved in step 92 are saved. The state is changed to the allocated state, and in step 95, the contents of the logical communication register specified by the caller are restored to the physical communication register taken out by the physical communication register securing means 16.

In step 96, the state of the logical communication register specified by the caller is changed to the in-use state, and then the physical communication register switching means 17 is called to transfer the processor to the physical communication register taken out by the physical communication register securing means 16. Connect to. If the physical communication register retrieved by the physical communication register securing means 16 in step 92 is not in the logical communication register in use that holds its image, the content of the logical communication register specified by the caller is determined in step 95. is restored to the physical communication register taken out by the physical communication register securing means 16,
In step 96, the state of the logical communication register specified by the caller is changed to the in-use state, the physical communication register switching means 17 is called, and the processor is connected to the physical communication register taken out by the physical communication register securing means 16. do.

If the logical communication register specified by the caller is in use in step 91, the physical communication register switching means 17 is called. Connects the processor to the physical communication register holding the contents of the logical communication register specified by the caller.

FIG. 10 is a flowchart showing the processing of the logical communication register release means 14. In step 101, the logical communication register release means 14 compares the logical communication register connected to its own processor with the logical communication register specified by the caller. If the two logical communication registers are the same, the physical communication register switching means 17 is called to connect the processor to the pseudo communication register, and in step 102, the logical communication register specified by the caller is made vacant. If the two logical communication registers are different in step 101, then in step 102 the logical communication register specified by the ζ-sounding source is made vacant.

Next, with reference to FIG. 11, a description will be given of how parallel processing is multiplexed using the communication register multiplexing method of the present invention.

First, when starting up the system, the logical communication register initialization means 11 and the physical communication register initialization means 15 are executed.
Initialization for communication register control is completed.

Next, when the parallel processing program is started, the program starts the first parallel processing. At this time,
While generating multiple tasks 111, one logical communication register 11 is created using the logical communication register securing means 12.
0 is secured, and each task 111 is connected to its logical communication register 110 using the logical communication register switching means 13. This state is state A in FIG. At this time, as can be seen from FIG. 8, the logical communication register securing means 12 only secures a logical communication register (that is, a save area for the physical communication register) and changes the state of the logical communication register to the allocated state. .

Logical communication register switching El' for the first task after that
Stage 13 is executed in a situation where the specified logical communication register is in the allocated state and there are still some physical communication registers in the free state. Therefore, one free physical communication register is secured as shown in FIG. 4, the image of the logical communication register is restored to that physical communication register as shown in FIG. The processor on which the task is running is connected to the physical communication register secured as shown in the figure. At this time, the state of the previously connected physical communication registers (pseudo communication registers in this case) is set to (N to 1) in use, and conversely, the state of the newly connected physical communication register is set to la in use. do. When the logical communication register switching means 13 of the second and subsequent tasks is executed, the specified logical communication register is in use, so as shown in FIG. 9, the physical communication register holding the image of the logical communication register is register(
In other words, the processor executing each task is connected to the physical communication register connected to the first task. At this time as well, the pseudo communication register and the assigned physical communication register undergo necessary state transitions. As a result of these operations, the processor executing the task becomes connected to a certain physical communication register.

Next, one of the tasks calls the logical communication register securing means 12 to secure the second logical communication register. As a result, state B in FIG. 11 is reached. The logical communication register securing means 12 at this time also only secures a new logical communication register, as shown in FIG. At this time, the second logical communication register becomes allocated.

Subsequently, a task that starts another parallel process uses the logical communication register switching means 13 to switch the accessible communication register to the second logical communication register. As a result, state C in FIG. 11 is reached. At this time, the logical communication register switching means 13 is executed in a state where the designated logical communication register is in the allocated state and there are still empty physical communication registers. Therefore, as shown in FIG. 4, one free physical communication register is secured, and as shown in FIG. 9, the image of the logical communication register is restored to the secured physical communication register, and as shown in FIG. Connect the processor executing this task to the newly allocated physical communication register, as shown in . At this time, the second logical communication register is in use, and one of the second physical communication registers is in use. vice versa,
The number of uses of the first physical communication register decreases by one.

As a result, a processor running a task other than the task that switched the logical communication register will be connected to the first physical communication register, and a processor running the task that switched the logical communication register will be connected to the second physical communication register. It will be connected to the communication register.

Subsequently, the number of tasks necessary for the second parallel processing is generated, and each task is connected to the second logical communication register by the logical communication register switching means 13. As a result, the state shown in FIG. 11 is obtained.

At this time, the logical communication register switching means 13 is executed when the designated logical communication register is in use. Therefore, as shown in FIGS. 9 and 5, the processors executing the tasks that make up the second parallel process are connected to the second physical communication register. As a result, two physics 3ff! A situation arises in which several processors are connected to each of the communication registers. In this state, two parallel processes are progressing simultaneously using separate physical communication registers.

When the second parallel process finishes, all tasks disappear, leaving only one task behind. As a result, state E in Figure 11
become. When a task disappears, the processor that was executing the disappearing task switches to another executable task. In the task switching process, the logical communication register switching means 13 is called in order to switch the communication register to the logical communication register connected to the task to which the task is to be switched. On the other hand, when there are no executable tasks,
The processor remains in a waiting state. Here, the explanation will be continued assuming a situation where there are no executable tasks. Therefore, at this timing, the logical communication register switching means 13 is not executed, and the connection relationship between the processor and the physical communication register does not change.

This relationship changes when an executable task appears and a task switch to that task occurs.

Subsequently, the remaining tasks are transferred to the logical communication register switching means 13.
Execute and switch the accessible logical communication register to the first logical communication register.

This means that the task has returned to the first parallel processing. As a result, state F in FIG. 11 is reached. At this time, the logical communication register switching means 13 is executed while the switching destination logical communication register (ie, the first logical communication register) is in use. Therefore, as shown in FIGS. 9 and 5, the processor executing the task is connected to the physical communication register that is assigned to the first logical communication register.

Finally, call the logical communication register release means 14,
When the second logical communication register is released, the state returns to a state where only one parallel processing is performed (state G in FIG. 11). At this time, the logical communication register release means 14 is executed on a task connected to a logical communication register other than the logical communication register to be released, so as shown in FIG. It simply transitions to the free state.

In this way, it is possible to nest multiple levels of parallel processing, and multiple tasks constituting one parallel processing can each execute separate parallel processing.

However, as a result of such multiplexing, a situation occurs in which the number of logical communication registers exceeds the number of processors (ie, the number of physical communication registers). Even in such a situation, if the communication register multiplexing method of the present invention is used, the communication registers will operate without error. This point will be explained in more detail below.

FIG. 12 shows how simultaneous parallel processing is executed by seven or more processors in a system having two processors and two physical communication registers. State O is a situation in which parallel processing A consisting of two tasks and parallel processing B consisting of three tasks are progressing simultaneously. The change from the empty state to this state is performed in the same manner as described in FIG. 11.

Now, in order to start the third parallel processing C in state 0,
When the third logical communication register is secured by the logical communication register securing means 12, the state becomes state 1.

At this time, the logical communication register securing means 12 only secures one logical communication register and puts it in a pending state, as shown in FIG. Therefore, at this point, the connection state between the processor and the physical communication register does not change.

Next, when a certain task of parallel processing B executes the logical communication register switching means 13 in order to start parallel processing C, state 2 is entered. At this time, the logical communication register switching means 13 determines that the logical communication register to be switched to is pending, all the physical communication registers are in use, and the logical communication register used in parallel processing B is used for other logical communication registers. The task inside is executed in a certain situation. Therefore, as shown in FIGS. 9, 4, and 5, the physical communication register assigned to parallel processing B saves its contents to the logical communication register and is switched to parallel processing C. At this time, the processor executing the task that called the logical communication register switching means 13 switches the connection of the physical communication register from the physical communication register for parallel processing B to the physical communication register for parallel processing C. However, since the physical communication register for parallel processing C after switching is the physical communication register for parallel processing B before switching, the connection relationship between the processor and the physical communication register does not change as a result.

Next, an explanation will be given of the operation when a task currently executing parallel processing A issues T10 and enters the I10 completion wait state. Here, the description will be made assuming that a certain task of parallel processing B is in an executable state at this time. In this case, Il
The processor that was executing the task that issued o executes task switching to the task of parallel processing B that is in an executable state.

This results in the system being in state 3. During task switching at this time, the logical communication register switching means 13 is called with the logical communication register designation for parallel processing B. The specified logical communication register for parallel processing B is in the allocated state, and one physical communication register is in use, so in the same way as from state 1 to state 2, the register for parallel processing A is The communication register image is saved, and the logical communication register image for parallel processing B is restored.

The processor that was executing the task that issued Ilo tries to switch physical communication registers, but it still ends up being connected to the same physical communication register.

After operating in this way for a while, the operation when the parallel processing C ends the processing will be explained.

Parallel processing C also generates several tasks and performs parallel processing, but in the end, only the task that returns to parallel processing B remains, and the other tasks disappear. Considering this situation as state 3,
I will explain the following.

The last task of the parallel processing C executes the logical communication register switching means 13 by specifying the logical communication register for the parallel processing B. As a result, the system enters state 4. At this time, the logical communication register to which the switch is made is already in use.
As shown in FIGS. 9 and 5, the processor is connected to the physical communication register already used for parallel processing B.

Finally, if the logical communication register securing means 14 is used to release the logical communication register for parallel processing C, state 5 is reached and parallel processing C is completely completed.

In this way, if the communication register multiplexing method of the present invention is used, even if parallel processing of a number greater than the number of processors is performed simultaneously in a time-divided manner, all parallel processing or communication registers can be used to operate correctly.

(Effects of the Invention) As explained above, in the system to which the communication register multiplexing method of the present invention is applied, it is possible to control the physical communication register and the logical communication register on the memory that holds the image when necessary. According to this, it becomes possible to time-division multiplex parallel processing using physical communication registers that are limited to the number of processors. At this time, the expansion of the communication register capacity is achieved by holding an image of the logical communication register in memory, and the allocation of communication registers is solved by allocating a separate logical communication register for each parallel process.

By using the communication register multiplexing method of the present invention, parallel processing can be written inside a subroutine whose parallelization situation is unknown, and multiple DO loops can be parallelized at multiple levels simultaneously. becomes possible. However, being able to do this means that it will logically work correctly even if several parallel processes are performed simultaneously within one program. The effect of speeding up program execution through parallelization can only be expected to increase up to the number of processors. By using the communication register multiplexing method of the present invention, multiplexing of parallel processing exceeding the number of processors can be described in the same way as multiplexing within the range of the number of processors, and in fact, multiplexing of parallel processing exceeding the number of processors can be described. When this occurs, a time-division multiplexing mechanism can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the communication register multiplexing system of the present invention, FIG. 2 is a state transition diagram of the physical communication register,
3 is a flowchart showing the processing of the physical communication register initialization means 15, FIG. 4 is a flowchart showing the processing of the physical communication register securing means 16, and FIG. 5 is a flowchart showing the processing of the physical communication register switching means 17.
6 is a state transition diagram of the logical communication register, FIG. 7 is a flowchart showing the processing of the logical communication register initialization means 11, and FIG. 8 is a flowchart showing the processing of the logical communication register securing means 1.
9 is a flowchart showing the processing of the logical communication register switching means 13, FIG. 10 is a flowchart showing the processing of the logical communication register release means 14, and FIG. 11 is the communication register multiplexing of the present invention. FIG. 12 is a diagram explaining the operation of multiple parallel processing using the communication register multiplexing method of the present invention when the number of processes exceeds 2 when -=Y. , FIG. 13 is a block diagram showing a conventional hardware-based multiple communication register configuration system, and FIG. 14 is a diagram explaining a simple concept of the multiple communication register system. 11...Logic communication register initialization means, 12...Logic communication register securing means, 13...Logic communication register switching means, 14...Logic communication register release means, 15
. . . Physical communication register initialization means, 16 . . . Physical communication register securing means, 17 . . . Physical communication register switching means.

Claims (1)

[Claims] In a communication register multiplexing method used in an operating system of a multiprocessor system that enables parallel processing of user programs, a logical communication register initialization means for setting all logical communication registers that are virtual communication registers to an empty state; Logical communication register securing means takes out one free logical communication register and makes it usable; logical communication register switching means switches the communication register visible from the processor to a designated logical communication register; a logical communication register release means that returns all of the physical communication registers that are existing communication registers to an empty state; and a physical communication register initialization means that is called from the logical communication register switching means to return to an empty state or a pending state. A physical communication register securing means that takes out one physical communication register and makes it usable, and a communication register that is called by the logical communication register switching means and the logical communication register release means and switches the communication register visible to the processor to the specified physical communication register. A communication register multiplexing method comprising physical communication register switching means.