JP2004086921A - Multiprocessor system and method for executing task in multiprocessor system thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a task executing method suitable to a task of fine granularity. <P>SOLUTION: This multiprocessor system comprises a step wherein whether or not there is a processor having a 'free state' among the processors 30-32 when a processor which is executing a task T1 among the processors 30-32 generates a new task T2, a step wherein when the processor having the 'free state' is detected, the task T2 begins to be executed by the processor by being assigned to the processor and the state of the processor is changed from the 'free state' to an 'execution state' to store a flag having a first value indicating that the execution of the task T1 is not interrupted. The system also includes a step wherein the execution of the task T1 is interrupted and the task T2 which is interrupted begins to be executed by the processor to store a flag having a second value indicating that the execution of the task T1 has been interrupted when the processor having a 'free state' is not detected. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a multiprocessor system including a plurality of processors that execute a plurality of tasks in parallel and a method of executing the tasks in the multiprocessor system.

In recent years, multiprocessor systems have attracted attention as one of the approaches to high performance by parallel processing of general-purpose computers. In a multiprocessor system, a shared memory type multiprocessor system in which a plurality of processors are connected to one bus and a main storage device is shared is mainly adopted.

(4) In such a multiprocessor system, since a plurality of processor chips are usually mounted on a printed circuit board, the processing speed of communication and synchronization using a bus between processors is slower than the processing speed of each processor. Therefore, it is used when the processing time of a task, which is a processing unit, is sufficiently longer than the communication or synchronization time between processors. In this case, the size of the task is called medium-grain size to coarse-grain size, and the number of executed instructions is about several thousands or more. In this way, by increasing the processing unit (roughening the granularity), the time for processor communication and synchronization is reduced relative to the task execution time.

Furthermore, in recent years, semiconductor integration technology has been rapidly developing. Therefore, many functional units and memories can be mounted in a chip. It is expected that multiple processors can be mounted on a single chip in a multiprocessor system in the future. In that case, the bus to which the processor is connected is also included in the chip, so that the speed of communication and synchronization between the processors increases the choice of the granularity of the task to be executed there. In other words, it is becoming possible to perform parallel processing in which the task size is fine and the number of instructions is several tens to several hundreds of instructions. It is expected that parallel processing of such fine-grained tasks will become mainstream in the future. This is because object-oriented programming and programming using a functional language, which have attracted attention in recent years, all conform to “parallel processing of fine-grained tasks”.

On the other hand, in a multiprocessor system, a plurality of tasks are assigned to a physically limited number of processors, so it is necessary to determine the execution order of the tasks and appropriately select which tasks are assigned to which processors. Done. In order to perform this processing dynamically, first, a task waiting to be executed is stored in a task management device such as a primary storage, and then a free processor is detected. If there is a free processor, the task is executed from the task waiting to be executed. A task to be selected is selected, and the selected task is assigned to a free processor. The task selection at this time is performed for the purpose of minimizing the execution time of the entire task. The process of deciding the execution order of such tasks and deciding to which processor the tasks are assigned is called scheduling, and there are various algorithms having different decision methods. Further, when a task to be executed is generated by task generation, there is a process of registering the task as a task waiting to be executed in the task management device.

FIG. 12 is a diagram illustrating the operation of a conventional processor allocation method in a multiprocessor system. In FIG. 12, the processor 2 generates a task, and registers the task 4 in the task management device as a task waiting to be executed. When detecting that the processor 1 is in the “free state”, the processor 0 selects one of the tasks waiting to be executed by the task management device according to the scheduling algorithm, and the selected task is assigned to the processor 1 by the processor 0. At this time, the processor 0 performs the scheduling process, and the processor 2 performs the task registration process.

For example, as shown in Japanese Patent Application Laid-Open No. 63-208948, an empty processor (processor 1 in FIG. 12) monitors a task ready queue (task management device in FIG. 12) and automatically executes a task waiting to be executed. Even in the case of performing the extraction processing, the processor in the “empty state” is performing the scheduling processing.

Further, as shown in, for example, Japanese Patent Application Laid-Open No. 62-190548, a requesting processor that requests a task monitors the state of the task in the requested processor, and the requested processor terminates the task. When the detection is detected, there is a method of appropriately selecting and assigning another task to the requested processor that has become an empty processor. In this method, the requesting processor performs a process of monitoring the state of the requested processor.

The above-described scheduling processing, task registration processing, or processing for monitoring a requested processor can be considered as overhead involved in assigning a task to a processor, although the contents are different, and accompanying the task processing. FIG. 13 shows a time chart of the processing time of the task and the processing time of the above-mentioned overhead. As shown in FIG. 13, when the granularity of the task is medium to coarse, the overhead processing time is relatively small with respect to the task processing time, so that the overhead processing time can be ignored.

However, in a multiprocessor system having overhead associated with task processing as described above, when fine-grained parallel processing is performed by speeding up communication and synchronization between processors, the relative processing time relative to the processing time of the task is increased. In addition, the overhead processing time increases.

FIG. 14 shows a time chart of the processing time of the task and the processing time of the overhead in the case of fine granularity. As shown in FIG. 14, the processing time of the overhead becomes relatively longer than the processing time of the task, and there is a problem that the processing time of the overhead cannot be ignored and the processing time of the entire work increases.

In view of the above problems, the present invention eliminates the above-described overhead by performing fine-grained parallel processing in a multiprocessor in which communication and synchronization between processors are high-speed, by not performing task management, scheduling, and monitoring of the task state. It is an object of the present invention to provide a method for unified, simple and fast dynamic assignment of tasks to alternative processors.

The method of the present invention is a method of executing a task in a multiprocessor system including a plurality of processors having an “empty state” and an “executing state”, wherein the first processor executes a first task among the plurality of processors. Detecting whether there is a second processor having an “empty state” among the plurality of processors when one processor generates a new second task; If it is detected, the execution of the second task by the second processor is started by allocating the second task to the second processor, and the state of the second processor is changed from “free” to “executed”. Changing to a “status” and storing a flag having a first value indicating that execution of the first task is not interrupted; If the processor is not detected, the execution of the first task by the first processor is interrupted, the execution of the second task by the first processor is started, and the execution of the first task is interrupted. Storing a flag having the indicated second value, thereby achieving the above object.

Determining whether the flag has the first value or the second value after the execution of the second task is completed; and determining whether the flag has the first value. When it is determined that the flag has the second value, the step of changing the state of the second processor from the “execution state” to the “free state”, and when it is determined that the flag has the second value, Restarting the execution of the first task by the first processor from the point where the execution of the first task has been interrupted.

そ れ ぞ れ Each of the plurality of processors may have an identifier for identifying the plurality of processors from each other, and the detection of the second processor having the “free state” may be performed using the identifier.

{Each of the plurality of processors may have a priority for determining a priority for assigning a task, and the assignment of the second task to the second processor may be performed based on the priority.

According to another method of the present invention, in a multiprocessor system including a plurality of processors having an “empty state” and an “executing state”, a “stop state”, a “first execution state”, and a “second execution state” are set. A method of executing a task having a “free state” among the plurality of processors when the first processor executing the first task among the plurality of processors generates a new second task. Detecting whether there is a second processor; and, if a second processor having an "empty state" is detected, assigning the second task to the second processor, The execution of the second task is started, the state of the second processor is changed from “free state” to “execution state”, and the state of the second task is changed from “stopped state” to “first execution state”. And, if no second processor having an “empty state” is detected, suspend execution of the first task by the first processor and start execution of the second task by the first processor And changing the state of the second task from the “stopped state” to the “second execution state”, thereby achieving the above object.

The method further comprises: after completion of the execution of the second task, determining a state of the second task; and determining that the second task has a “first execution state”, Changing the state of the two processors from "execution state" to "empty state" and changing the state of the second task from "first execution state" to "stop state"; If it is determined that the second task has the “execution state”, the method may further include a step of changing the state of the second task from the “second execution state” to the “stop state”.

そ れ ぞ れ Each of the plurality of processors may have an identifier for identifying the plurality of processors from each other, and the detection of the second processor having the “free state” may be performed using the identifier.

{Each of the plurality of processors may have a priority for determining a priority for assigning a task, and the assignment of the second task to the second processor may be performed based on the priority.

The multiprocessor system of the present invention manages the state of each of a plurality of processors that execute a plurality of tasks in parallel and the plurality of processors, and responds to an inquiry from each of the plurality of processors. State management means for returning an identifier, and each of the plurality of processors inquires of the state management means whether or not there is a "vacant" processor when a new task occurs. You. This achieves the above object.

The state management unit may include a unit that changes a current state to a next state in response to an inquiry from the processor, and a unit that outputs a response to the inquiry based on the next state. Good.

The multiprocessor system may further include an instruction cache memory and a data cache memory for each of the plurality of processors.

The multiprocessor system may further include a network for transferring instruction addresses and packet addresses among the plurality of processors.

そ れ ぞ れ Each of the plurality of tasks may be fine-grained.

According to the present invention, when a new task is generated by a certain processor, the execution of the task can be immediately started by another or its own processor. This eliminates the need for a mechanism for holding tasks and a mechanism for scheduling the execution order of tasks. Further, there is no need to perform a process of selecting a task waiting to be executed and assigning the selected task to a “vacant” processor.

結果 As a result, the time required for processor assignment is shorter than the task processing time. As a result, in a multiprocessor system, high-speed parallel processing with a fine granularity can be achieved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a multiprocessor system 1 of the present invention. The multiprocessor system 1 is implemented on an integrated circuit. The multiprocessor system 1 is connected to the main storage device 2 via a bus.

The multiprocessor system 1 includes element processor units 10 to 12. Each of the element processor units 10 to 12 has the same configuration. The number of element processor units included in the multiprocessor system 1 is not limited to three. Multiprocessor system 1 may include any number of element processor units.

The element processor units 10 to 12 have processors 30 to 32, instruction caches (IC) 33 to 35, and data caches (DC) 36 to 38, respectively. The instruction cache (IC) is a cache memory for storing instructions and is read-only. The data cache (DC) is a cache memory for storing data, and can be read and written.

The shared cache 20 is shared by the element processor units 10 to 12. The instruction set and the data set are usually stored in the main storage device 2. The data set is loaded into the shared cache 20 via the bus interface 23 as needed. The shared cache 20 preferably operates at a very high speed as compared with the main storage device 2. The data cache (DC) and the shared cache 20 are selectively used depending on the address. For example, when the address is in the range of 0x00000000 to 0x7ffffffff, the data cache (DC) is accessed, and when the address is in the range of 0x80000000 to 0xffffffff, the shared cache 20 is accessed.

The element processor units 10 to 12 are mutually connected via the network 21. The network 21 is used to transfer instruction addresses and packet addresses between the element processor units 10 to 12. The network 21 can be realized using, for example, a 3 × 3 crossbar switch.

The processor status management device 22 manages the status of the processors 30 to 32. Each of the processors 30 to 32 has one of an “execution state” and an “empty state”.

A fixed priority is assigned to each of the processors 30 to 32 in advance. Here, it is assumed that the processors 30 to 33 have the higher priority in this order. The priority is used to determine which of the plurality of processors is allowed to access the processor state management device 22 preferentially when a plurality of processors simultaneously access the processor state management device 22. used.

Each of the processors 30 to 32 has an identifier (ID) for distinguishing the processors 30 to 32 from each other. Typically, an identifier (ID) is represented by a number.

Each of the processors 30 to 32 holds the address of the packet therein. The address of the packet is held, for example, in a register (not shown) inside the processors 30 to 32. Thereby, the processors 30 to 32 can refer to the packet. Details of the packet will be described later with reference to FIG.

The multiprocessor system 1 has a function of executing a plurality of tasks in parallel. For example, the processor 31 can execute the task T2 while the processor 30 is executing the task T1.

で は In this specification, a “task” is defined as a set of an instruction set and a data set. The instruction set and the data set are both stored in the main storage device 2. Each of the processors 30 to 32 sequentially reads instructions from the instruction set, and interprets and executes the read instructions. The data set is referred to as necessary when the processors 30 to 32 interpret and execute the instruction read from the instruction set. A packet described later is at least a part of the data set.

Fig. 2 schematically shows the concept of a task. In this example, task 1 is defined by a set of instruction set 1 and data set 1, task 2 is defined by a set of instruction set 1 and data set 2, and task 3 is defined by instruction set 2 and data set 3. Defined by tuple. The instruction sets 1 and 2 and the data sets 1 to 3 are stored in the main storage device 2, respectively.

FIG. 3 shows a configuration example of the processor state management device 22 that manages the states of the processors 30 to 32. Processor state management device 22 includes a combinational circuit that provides outputs (ID0-ID2, NMP0-NMP2) in response to inputs (REQ0-REQ2, RESET0-RESET2). The combinational circuit determines the next state (nextS) according to the current state (S) and the inputs (REQ0 to REQ2, RESET0 to RESET2), and outputs (ID0 to ID2, NMP0 to NMP0) corresponding to the next state. NMP2). The transition from the current state (S) to the next state (nextS) is determined according to, for example, a state transition table shown in Table 1.

　図３において、Ｓは現在の状態、ＮｅｘｔＳは次の状態を示す。これらの状態は、プロセッサ３０〜３２の状態を示す。例えば、Ｓ＝００１は、プロセッサ３０の状態が「実行状態」であり、プロセッサ３１とプロセッサ３２の状態が「空き状態」であることを示している。ＮｅｘｔＳについても同様である。

In FIG. 3, S indicates the current state, and NextS indicates the next state. These states indicate the states of the processors 30 to 32. For example, S = 001 indicates that the state of the processor 30 is “execution state” and the states of the processors 31 and 32 are “empty state”. The same applies to NextS.

In FIG. 3, REQ0 to REQ2 represent requests input from the processors 30 to 32 to the processor state management device 22. These requests are for requesting the processor status management device 22 to obtain the identifier of the “free” processor. In Table 1, REQ0 to REQ2 are collectively described as REQ. For example, REQ = 101 indicates that REQ0 is 1 (asserted), REQ1 is 0 (negated), and REQ2 is 1 (asserted).

In FIG. 3, RESET0 to RESET2 represent resets input from the processors 30 to 32 to the processor state management device 22. These resets request the processor state management device 22 to change the state of the processors 30 to 32 held in the processor state management device 22 from the “execution state” to the “free state”. In Table 1, RESET0 to RESET2 are collectively described as RESET. For example, RESET = 010 indicates that RESET0 is 0 (negated), RESET1 is 1 (asserted), and RESET2 is 0 (negated).

In FIG. 3, ID0 to ID2 indicate signals for notifying the identifiers of the "free" processors in response to requests from the processors 30 to 32. These signals are output from the processor state management device 22 in response to requests from the processors 30 to 32. The meanings of the values of ID0 to ID2 are as follows.

$ 00: The processor 30 is in an "empty state".

$ 01: The processor 31 is in an "empty state".

# 10: The processor 32 is in the “empty state”.

In FIG. 3, NMP0 to NMP2 indicate signals for notifying that "an empty processor does not exist" in response to a request from the processors 30 to 32. These signals are output from the processor state management device 22 in response to requests from the processors 30 to 32. The meanings of the values of NMP0 to NMP2 are as follows.

$ 0: There is a processor in an "empty state". The identifier of the “free” processor is indicated by the values of ID0 to ID02.

$ 1: There is no "free" processor. In this case, the values of ID0 to ID2 are don't @ care.

Hereinafter, functions and operations of the processor state management device 22 will be described with reference to FIGS. The processor status management device 22 manages the status of all processors included in the multiprocessor system. Specifically, the processor status management device 22 stores the identifier of the processor and the status of the processor as a pair in the processor status management device 22. The processor identifier is used to identify a plurality of processors from each other. Typically, the processor identifier is represented by an integer. The state of the processor is either “execution state” or “empty state”.

(4) In response to a request from a certain processor, the processor state management device 22 determines whether or not there is a “free” processor. If there is a “vacant” processor, the processor state management device 22 returns the identifier of the “vacant” processor to the processor that issued the request. If there is no “empty” processor, the processor state management device 22 returns a message indicating that “an empty processor does not exist” to the processor that issued the request.

When there are a plurality of “free” processors, the processor state management device 22 returns the identifier of the processor with the highest priority among the plurality of “free” processors to the processor that issued the request. Further, when requests from a plurality of processors arrive at the processor state management device 22 at the same time, the above-described processing is performed in order from a plurality of processors that have issued the request, in descending order of priority.

FIGS. 4A and 4B show an example of the operation of the processor state management device 22. FIG. The processor state management device 22 manages the states of the four processors 0 to 3. In the example shown in FIG. 4A, the states of the processors 0 and 1 are “execution states”, and the states of the processors 2 and 3 are “empty states”. The request from the processor 0 and the request from the processor 1 are input to the processor state management device 22.

In response to the request from the processor 0, the processor state management device 22 returns the identifier of the "free" processor 2 to the processor 0, and in response to the request from the processor 1, the "free" processor 3 The identifier is returned to the processor 1 (see FIG. 4B). The identifier of the "empty" processor is returned according to the priority of the processor. Further, the processor state management device 22 changes the state of the processor 2 held in the processor state management device 22 from “free state” to “execution state”, and changes the state of the processor 3 from “free state” to “execution state”. State ”.

FIGS. 5A and 5B show another example of the operation of the processor state management device 22. FIG. The processor state management device 22 manages the states of the four processors 0 to 3. In the example illustrated in FIG. 5A, the states of the processor 0, the processor 1, and the processor 2 are “execution states”, and the state of the processor 3 is “empty state”. The request from the processor 0 and the request from the processor 1 are input to the processor state management device 22.

In response to the request from the processor 0, the processor state management device 22 returns the identifier of the "free" processor 3 to the processor 0, and in response to the request from the processor 1, "there is no free processor". Is returned to the processor 1 (see FIG. 5B). The message indicating that “there is no empty processor” is represented by, for example, a return code value output from the processor state management device 22. The identifier of the "empty" processor is returned according to the priority of the processor. Further, the processor state management device 22 changes the state of the processor 3 held in the processor state management device 22 from the “free state” to the “execution state”.

In the example shown in FIGS. 4 and 5, the number of processors managed by the processor state management device 22 is four. However, this is for convenience of explanation, and the present invention is not limited to a multiprocessor system having four processors. The present invention can be applied to a multi-processor system including any number of processors.

FIG. 6 shows the configuration of the packet 50. The packet 50 includes a lock bit area 51 for storing lock bits, a return bit area 52 for storing return bits, a return address area 53 for storing return addresses, and an argument area 54 for storing arguments. And a return value area 55 for storing a return value. The packet 50 is secured on the shared memory 20 for each task and owned by the task. Hereinafter, the “packet owned by the task” is simply referred to as “task packet”. The packet 50 is used for transferring data between tasks and holding task information.

ロ ッ ク The lock bit is stored in the lock bit area 51 of the packet 50. The lock bit indicates whether or not other tasks are prohibited from accessing the running task while the task owning the packet 50 is running. The lock bit being “1” indicates that access is prohibited. The lock bit being “0” indicates that access is not prohibited.

Return bits are stored in the return bit area 52 of the packet 50. The return bit indicates whether or not another task was interrupted before executing the task that owns the packet 50. The return bit being “0” indicates that “the other task is not interrupted before executing the task that owns the packet 50”. This corresponds to the case where the task that owns the packet 50 is assigned to the processor in the “empty state”. The fact that the return bit is "1" indicates that "before executing the task that owns the packet 50, another task was interrupted." This corresponds to a case where the processor executing the task interrupts the execution of the task and executes another task that owns the packet 50 because there is no “idle” processor.

リ タ ー ン The return address is stored in the return address area 53 of the packet 50. The return address is referred to only when the return bit is “1”. The return address indicates a return address to the interrupted task.

# The argument area 54 of the packet 50 stores an argument to the task that owns the packet 50.

The return value 55 of the packet 50 is stored in the return value area 55 of the task that owns the packet 50.

FIG. 7 shows a procedure in which the processors 30 to 32 interpret and execute the fork instruction. Each of the processors 30 to 32 reads an instruction from an instruction set stored in the main storage device 2. If the read instruction is a fork instruction, the processors 30 to 32 execute the processing shown in FIG.

Hereinafter, with reference to FIG. 7, a procedure in which the processor 30 interprets and executes the fork instruction will be described in detail for each step. The same applies to the case where the other processors 31 and 32 interpret and execute the fork instruction. The fork instruction takes, as operands, the start address of an instruction sequence indicating the processing content of a new task (hereinafter simply referred to as an instruction address) and the address of the packet 50 of the new task (hereinafter simply referred to as a packet address). .

Step (a): The processor 30 inquires of the processor state management device 22 whether or not there is an “idle” processor. Such an inquiry is achieved, for example, by the processor 30 sending a request (REQ0 = 1) to the processor state management device 22. In response to the request, the processor state management device 22 determines whether or not there is a “free” processor.

If there is an “empty” processor, the processor status management device 22 returns the identifier of the “empty” processor to the processor 30. The identifier of the processor in the “free state” is obtained, for example, by the processor 30 referring to the value of ID0 output from the processor state management device 22. If there are a plurality of "empty" processors, the identifier of the processor with the highest priority is obtained. When a plurality of processors interpret and execute a fork instruction at the same time, the processors interpret and execute the fork instructions in descending order of priority. In this way, the processor 30 obtains the identifier of the “free” processor.

If there is no “empty” processor, the processor state management device 22 returns a message to the effect that “an empty processor does not exist” to the processor 30. The message that “there is no free processor” is obtained, for example, by the processor 30 referring to the value of NMP0 output from the processor state management device 22.

Step (b): If there is an “empty” processor, the processor 30 performs the processing of steps (c) to (e). If there is no “idle” processor, the processor 30 performs the processing of steps (f) to (g).

Step (c): Here, it is assumed that the processor in the “free state” is the processor 31. In this case, the processor 30 transfers the task instruction address and the task packet address given as operands of the fork instruction to the processor 31 via the network 21.

Step (d): The processor 30 writes "1" in the lock bit area 51 of the packet 50 specified by the packet address of the task given as the operand of the fork instruction, and writes "0" in the return bit area 52. Thereafter, the processor 30 completes the processing of the fork instruction and performs the processing of the next instruction.

Step (e): The processor 31 receives the instruction address of the task and the packet address of the task from the processor 30 via the network 21. The processor 31 starts processing from the instruction specified by the received instruction address while referring to the packet 50 specified by the received packet address.

に よ り Through the above steps (a) to (e), the processor 30 independently executes processing different from the processing executed by the processor 31. That is, parallel processing is started by the processor 30 and the processor 31. The processing of the fork instruction ends here.

Step (f): The processor 30 writes "1" in the lock bit area 51 of the packet 50 specified by the packet address of the task given as the operand of the fork instruction, and writes "1" in the return bit area 52. Also, the address of the instruction following the fork instruction is written in the return address area 53. The processor 30 suspends the task being executed.

Step (g): The processor 30 refers to the packet 50 specified by the packet address of the task given as the operand of the fork instruction, and from the instruction specified by the instruction address of the task given as the operand of the fork instruction. Start processing. The processing of the fork instruction ends here.

Hereinafter, with reference to FIG. 8, a procedure in which the processor 30 interprets and executes the unlock instruction will be described in detail for each step. The same applies when the other processors 31 and 32 interpret and execute the unlock instruction.

Step (h): The processor 30 determines whether or not the value of the return bit area 52 of the packet 50 owned by the task being executed is “0”. When the value of the return bit area 52 is “0”, it indicates that there is no task whose processing has been interrupted by the processor 30. Therefore, when the value of the return bit area 52 is “0”, the processor 30 performs the process of step (i). When the value of the return bit area 52 is “1”, it indicates that there is a task whose processing has been interrupted by the processor 30. Therefore, when the value of the return bit area 52 is “1”, the processor 30 performs the processing of step (j).

Step (i): The processor 30 writes “0” in the lock bit area 51 of the packet 50 owned by the task being executed, and sets the state of the processor 30 to “free”. The processor 30 in the “empty state” does not perform the subsequent processing. The processing of the unlock instruction ends here.

Step (j): The processor 30 writes “0” in the lock bit area 51 of the packet 50 owned by the task being executed. Further, the processor 30 returns the interrupted task by processing the instruction from the address stored in the return address area 53. The processing of the unlock instruction ends here.

Table 2 shows how the state of the multiprocessor system changes in response to the interpretation and execution of the fork and unlock instructions. In the example shown in Table 2, it is assumed that the multiprocessor system has a processor P1 and a processor P2.

　図９に示されるように、マルチプロセッサシステムの状態は、プロセッサの状態とタスクの状態とに区分される。

As shown in FIG. 9, the state of the multiprocessor system is divided into a processor state and a task state.

The processor has two states. One state is “idle state” (IDLE), and the other state is “execution state (RUN)”. These states are the same as the states managed by the processor state management device 22. When the state of the processor is “RUN state (RUN)”, the processor is executing any task.

A task has three states. The first state is a “stop state (STOP)”, the second state is a “first execution state (EX1)”, and the third state is a “second execution state (EX2)”. is there. The "stop state (STOP)" is a state in which the processor is waiting for the execution of the task or has finished executing the task. The “first execution state (EX1)” is a state in which the current task is being executed without interrupting the execution of another task. The “second execution state (EX2)” is a state in which the execution of another task is suspended and the current task is being executed thereafter. When the state of the processor is “execution state (RUN)”, the state of the task executed by the processor is one of “first execution state (EX1)” and “second execution state (EX2)”. Is one of

再 び Referring again to Table 2, how the state of the multiprocessor system transitions will be described. The state of the multiprocessor system changes to the next state based on the event and the current state in response to the occurrence of the event. Here, the notation “Px.fork” indicates that an event “the processor Px has executed the fork instruction” has occurred, and the notation “Px.unlock” indicates that the “processor Px has executed the unlock instruction”. Event has occurred.

In the first row of Table 2, the processor P1 is in the “execution state” (executing the task T1), the processor P2 is in the “free state”, the task T1 is in the “first execution state”, and the task T2 is In the case of the "stop state", the state of the processor P2 is changed from the "free state" to the "execution state" (executing the task T2) in response to the event "the processor P1 has executed the fork instruction". , The state of the task T2 is changed from the “stopped state” to the “first execution state”. The reason for the state transition is that when the new task T2 is generated, the task T2 is assigned to the "free" processor P2.

In the second row of Table 2, when the next state in the first row of Table 2 is the current state, the state of the processor P2 is changed to "In response to the event that the processor P2 has executed the unlock instruction". This indicates that the state of the task T2 is changed from the “first execution state” to the “stopped state” from the “execution state” (the task T2 is being executed) to the “empty state”.

In the third row of Table 2, the processor P1 is in the “execution state” (executing the task T1), the processor P2 is in the “execution state” (executing another task), and the task T1 is in the “first execution state”. State "and the task T2 is" stopped ", the state of the processor P1 is changed to" execution state "(executing the task T1) in response to the event" processor P1 has executed the fork instruction ". Is changed to “execution state” (task T2 is being executed), and the state of task T2 is changed from “stopped state” to “second execution state”. This state transition occurs because the processor P1 interrupts the execution of the task T1 and starts the execution of the task T2 because there is no "idle" processor when the new task T2 is generated. It is.

In the fourth row of Table 2, when the next state in the third row of Table 2 is the current state, the state of the processor P1 changes to "In response to the event that the processor P1 has executed the unlock instruction". This indicates that the execution state is changed from "execution state" (task T2 is being executed) to "execution state" (task T1 is being executed), and the state of task T2 is changed from the "second execution state" to the "stopped state".

Hereinafter, an operation of the multiprocessor system 1 when a program including a fork instruction and an unlock instruction is processed in parallel will be described.

FIG. 10 shows the procedure of a program for calculating the sum (1 + 2 + 3 + 4) of 1 to 4 based on a binary tree. This program is divided into two parts, main and sum, where main is a main program and sum is a subroutine that can be called recursively and can be processed in parallel. The sum takes two arguments, n and m, and calculates the sum from n + 1 to m. main calls sum with n = 0 and m = 4 as arguments.

First, as an initial state, it is assumed that the processor 30 is executing main. The state of the processor 30 is an “execution state”. It is also assumed that the states of the processors 31 and 32 are “empty”.

Hereinafter, how the multiprocessor system 1 operates in each step (A) to (H) of the program will be described in detail.

Step (A): The processor 30 executes the sum subroutine using n = 0 and m = 4 as arguments. Specifically, the processor 30 secures the packet 50 (Pk1) on the shared cache memory 20, and stores the value 0 and the value 4 in the argument area 54 of the packet 50 (Pk1). Next, the processor 30 executes the exec instruction using the start address of the instruction of sum and the start address of the packet 50 (Pk1) as operands. The exec instruction is an instruction corresponding to only steps (f) and (g) in the processing procedure of the fork instruction shown in FIG. The exec instruction takes a task instruction address and a task packet address as operands in the same manner as the fork instruction.

The processor 30 writes “1” in the lock bit area 51 of the packet 50 (Pk1), writes “1” in the return bit area 52 of the packet 50 (Pk1), and writes the next instruction following the exec instruction in the return address area 53. The address is stored (see step (f) in FIG. 7). Further, the processor 30 starts executing the sum instruction while referring to the packet 50 (Pk1) (see step (g) in FIG. 7).

Step (B): The processor 30 reads the argument n and the argument m from the packet 50 (Pk1), and compares (n + 1) with m. If (n + 1) is equal to m, the process proceeds to step (G); otherwise, the process proceeds to step (C). When the sum subroutine is first called from main, since n = 0 and m = 4, (n + 1) is not equal to m. Therefore, the process proceeds to step (C).

Step (C): The processor 30 calculates k = (n + m) div2. Here, since (n + m) = 4, k = 2.

Step (D): The processor 30 executes the sum subroutine using n and k as arguments. Specifically, the processor 30 secures the packet 50 (Pk2) on the shared cache memory 20, and stores the value n (= 0) and the value k (= 2) in the argument area 54 of the packet 50 (Pk2). Store. Next, the processor 30 executes the fork instruction using the start address of the sum instruction and the start address of the packet 50 (Pk2) as operands.

Both the processor 31 and the processor 32 are in the “empty state”. The processor 30 obtains the identifier of the “empty” processor 31 according to the priority (see step (a) in FIG. 7). The processor 30 transfers the task instruction address and the task packet address to the processor 31 (see step (b) in FIG. 7). The processor 30 writes “1” in the lock bit area 51 of the packet 50 (Pk2) and writes “0” in the return bit area 52 of the packet 50 (Pk2) (see step (d) in FIG. 7). Further, the processor 31 starts executing the sum instruction while referring to the packet 50 (Pk2) (see step (e) in FIG. 7). Thus, the processor 30 and the processor 31 execute the sum subroutine in parallel.

Step (E): The processor 30 executes the sum subroutine using k and m as arguments. Specifically, the processor 30 secures the packet 50 (Pk3) on the shared cache memory 20 and stores the value k (= 2) and the value m (= 4) in the argument area 54 of the packet 50 (Pk3). Store. Next, the processor 30 executes the exec instruction using the start address of the sum instruction and the start address of the packet 50 (Pk3) as operands. Before the processor 30 starts executing the exec instruction, the packet 50 (Pk1) is saved in the stack area.

The processor 30 writes “1” in the lock bit area 51 of the packet 50 (Pk3), writes “1” in the return bit area 52 of the packet 50 (Pk3), and writes the next instruction following the exec instruction in the return address area 53. The address is stored (see step (f) in FIG. 7). The processor 30 starts executing the sum instruction while referring to the packet 50 (Pk3) (see step (g) in FIG. 7).

Step (F): After completing the execution of the sum subroutine called in step (E), the processor 30 restores the packet 50 (Pk1) saved in the stack area. After that, the processor 30 adds s1 and s2. Here, s1 indicates the result of the sum subroutine executed in step (D). Therefore, s1 is stored in the return value area 55 of the packet 50 (Pk2). s2 indicates the result of the sum subroutine executed in step (E). Therefore, s2 is stored in the return value area 55 of the packet 50 (Pk3). At the point in time when the processor 30 has finished executing the sum subroutine called in step (E), the task that owns the packet 50 (Pk2) may still be executing. After completing the execution of the task that owns the packet 50 (Pk2), the processor 30 reads the value stored in the return value area 55 of the packet 50 (Pk2) and sets the value as s1. Here, s1 = 3. Whether or not the execution of the task owning the packet 50 (Pk2) has been completed is determined by referring to the value of the lock bit area 51 of the packet 50 (Pk2). The fact that the value of the lock bit area 51 of the packet 50 (Pk2) is “0” indicates that the execution of the task that owns the packet 50 (Pk2) has been completed.

Similarly, after the execution of the task that owns the packet 50 (Pk3), the processor 30 reads the value stored in the return value area 55 of the packet 50 (Pk3), and sets the value as s2. Here, s2 = 7. The processor 30 calculates s1 + s2. As a result, s = 10 is obtained.

Step (H): The processor 30 stores the value of s in the return value area 55 of the packet 50 (Pk1). Thereafter, the processor 30 executes the unlock instruction.

The processor 30 determines whether or not the value stored in the return bit area 52 of the packet 50 (Pk1) is “1” (see step (h) in FIG. 8). Is “1”. Therefore, the processor 30 stores “0” in the lock bit area 51 of the packet 50 (Pk1) and executes the instruction from the address stored in the return address area 53 (see step (j) in FIG. 8). ). In this case, the processing is restarted from the instruction following the main step (A).

Step (G): If it is determined in step (B) that n + 1 = m, the process proceeds to step (G). The processor 30 substitutes the value of the argument m for s. Thereafter, the processing proceeds to step (H).

Note that the steps (B) to (H) described above are also executed in the sum subroutine called in step (D) and the sum subroutine called in step (E). This is because the sum subroutine is a subroutine that can be called recursively.

As described above, the sum of 1 to 4 (1 + 2 + 3 + 4) is calculated in parallel by recursively calling the sum subroutine. In this example, two tasks are generated by the fork instruction in step (D) and the exec instruction in step (E). The fork instruction is an instruction used for allocating a task to a processor in an "idle state" as long as there is a processor, and the exec instruction is an instruction used for allocating a task to its own processor.

FIG. 11 schematically shows the contents of the above-described processing. As shown in FIG. 11, two tasks sum (0,2) and task sum (2,4) are generated from the task sum (0,4) by a fork instruction and an exec instruction. Task sum (0,2) is assigned to processor 31, and task sum (2,4) is assigned to processor 30. Similarly, two more tasks are generated from each of the two tasks. As long as there is an "idle" processor, tasks are assigned to other processors.

(5) Task sum (2, 3) and task sum (3, 4) are generated from task sum (2, 4). However, both tasks are assigned to the processor 30. This is because, when the task (2, 3) is allocated, the "free" processor no longer exists.

As described above, each of the processors 30 to 32 in the multiprocessor system 1 of the present invention interprets and executes the fork instruction, and assigns a task to a processor in a “free state” when there is a “free state” processor. If there is no "state" processor, the execution of the task being executed is interrupted, and the task is assigned to that processor. In this way, the task to be processed is generated, and at the same time, the generated task is assigned to either the “free” processor or the processor that generated the task. As a result, the generated task is executed immediately. This eliminates the need for a mechanism for storing tasks to be processed and a mechanism for scheduling the execution order of tasks, which are required in the conventional multiprocessor system. In addition, when there is an “idle” processor, a task is always assigned to that processor, so that the utilization efficiency of the processor is high.

(4) Further, the fork instruction and the unlock instruction can be realized by simple hardware, and high-speed processing can be realized.

Therefore, in the multiprocessor system 1 mounted on the integrated circuit, the processing time of the task, such as the program for obtaining the sum of 0 to 4 illustrated, is shorter than the time required for the scheduling processing time and the time required for the management processing of the task waiting to be executed. The task execution method of the present invention is very useful when a small program is to be processed in parallel.

When an interrupt is received from outside the integrated circuit, the processor in the "empty state" is detected by using the processor state management device 22, and the processor with the lowest priority among the "empty states" is processed by the interrupt processing. Is performed, it is possible to reduce performance degradation due to interrupt processing.

The fact that all the processors of the integrated circuit are in the “empty state” can be detected by using the processor state management device 22. Therefore, in this case, deadlock can be avoided by performing exception processing in any of the processors.

As described above, according to the present invention, when a new task is generated by a certain processor, the execution of the task can be immediately started by another or its own processor. This eliminates the need for a mechanism for holding tasks and a mechanism for scheduling the execution order of tasks. Further, there is no need to perform a process of selecting a task waiting to be executed and assigning the selected task to a “vacant” processor.

結果 As a result, the time required for processor assignment is shorter than the task processing time. As a result, in a multiprocessor system, high-speed parallel processing with a fine granularity can be achieved.

FIG. 1 is a diagram showing a configuration of a multiprocessor system 1 of the present invention. It is a figure which shows the concept of a task typically. FIG. 2 is a diagram showing a configuration example of a processor state management device 22 in the multiprocessor system 1. FIGS. 4A and 4B are diagrams illustrating an example of the operation of the processor state management device 22. FIGS. (A) and (b) are diagrams illustrating another example of the operation of the processor state management device 22. FIG. 3 is a diagram illustrating a configuration of a packet 50. FIG. 4 is a diagram illustrating a procedure in which processors 30 to 32 interpret and execute a fork instruction. FIG. 4 is a diagram illustrating a procedure in which processors 30 to 32 interpret and execute an unlock instruction. FIG. 3 is a diagram illustrating a state of a processor and a state of a task. It is a figure which shows the procedure of the program which calculates the sum of 1 to 4 based on a binary tree. FIG. 11 is a diagram schematically illustrating processing contents of a program illustrated in FIG. 10. FIG. 9 is a diagram illustrating an operation of a conventional processor assignment method. 6 is a time chart showing the processing time of a task and the processing time of an overhead when the task has a medium to coarse granularity. 6 is a time chart showing a processing time of a task and a processing time of an overhead when the task has a fine granularity.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Multiprocessor system 2 Main storage device 10-12 Element processor unit 20 Shared cache 21 Network 22 Processor state management device 23 Bus interface 30-32 Processor 33-35 Instruction cache (IC)
36-38 Data cache (DC)

Claims (1)

A method for performing a task in a multiprocessor system including a plurality of processors having an “empty state” and an “execution state”,
When a first processor executing a first task among the plurality of processors generates a new second task, the first processor requests the execution of the second task. Detecting whether there is a second processor having an “empty state”;
As a result of the detection, when a second processor having an “empty state” is detected, the execution of the second task by the second processor is started by allocating the second task to the second processor. Changing the state of the second processor from an “empty state” to an “executing state” and storing a flag having a first value indicating that execution of the first task has not been interrupted;
As a result of the detection, if the second processor having the “free state” is not detected, the execution of the first task by the first processor is interrupted, and the execution of the second task by the first processor is started. Storing a flag having a second value indicating that execution of the first task has been interrupted.

Images