JPH0460475A - Lsi testing circuit - Google Patents

Abstract

PURPOSE:To facilitate observation of condition of an internal circuit from an external output pin by arranging a group of signals to be drawn at an optional point of the internal circuit and a selection circuit which switches the signal group from a group of external output signals to be supplied to an output buffer circuit. CONSTITUTION:Input signals from outside are inputted into a block 31 via an input buffer circuit 1 and are given as inputs of a block 32 and a selection circuit 4. Outputs of the block 32 are given as inputs of a block 33 and a circuit 4. Then, the circuit 4 switches output signals of the blocks 31 and 32 from an output of the block 33 to be inputted into an output buffer circuit 2. This enables observation of a state value of output from an LSI external output pin.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an LSI test circuit.

[Conventional technology]

In recent years, as LSIs have become more highly integrated, the ratio of the number of gates in an LSI internal circuit to the LSI external output pins has become extremely large.

Therefore, it has become extremely difficult to discover failures in LSI internal circuits by observing the LSI external output pins.

Conventional LSI test circuits that observe the state of LSI internal circuits that are difficult to observe using LSI external output pins are designed to switch flip-flops inside the LSI to form a shift register, and to switch the flip-flops on the shift-out side of the LSI to configure a shift register. There is a method (scanpath method) in which the state value of a flip-flop inside an LSI is observed from one LSI external output pin by connecting the output of the flop to an LSI external output pin.

[Problem to be solved by the invention]

With the above-mentioned conventional LSI test circuit, as LSIs become highly integrated, it has become difficult to observe the state of the LSI internal circuits from the LSI external output pins.

An object of the present invention is to provide an LSI test circuit that makes it easier to observe the state of an LSI internal circuit from an LSI external output pin.

[Means to solve the problem]

The LSI test circuit of the present invention includes an internal circuit, an input buffer circuit for supplying an input signal from an external terminal to the internal circuit, and an output buffer circuit for supplying an output signal from the internal circuit to the external terminal. The LSI includes a group of extraction signals at any point in an internal circuit, and a selection circuit that switches between the extraction signal group and a signal group output to the outside of the LSI and supplies the selected signal to an output buffer circuit.

Another LSI test circuit of the present invention includes an internal circuit, an input buffer circuit for supplying an input signal from an external terminal to the internal circuit, and an output signal for supplying an output signal from the internal circuit to the external terminal. LSI with a buffer circuit
In the block, an internal circuit is divided into a plurality of blocks, a first signal group distributed from an input buffer circuit to each block, and a first signal group provided on the input side of each block.
a first selection circuit that switches between a group of signals and a second group of signals between internal circuits and supplies them to each of the blocks;
and a second selection circuit that switches the output signal group of the block and supplies it to the output buffer circuit.

Furthermore, another LSI test circuit of the present invention includes an internal circuit, an input buffer circuit for supplying an input signal from an external terminal to the internal circuit, and an input buffer circuit for supplying an output signal from the internal circuit to the external terminal. L having an output buffer circuit
In SI, a block in which the internal circuit is divided into multiple parts,
and a selection circuit that switches between two signal groups: an input signal group of any block among the plurality of blocks and an output signal group of the block, and supplies the output signal group to the input of a block other than the block. .

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. Referring to FIG. 1, this embodiment includes an input buffer circuit 1 that inputs signals from the outside, an output buffer circuit 2 that supplies signals to an output terminal, and an internal circuit that can be divided into a plurality of blocks 31 to 33. , and a selection circuit 4 capable of selecting each block.

An input signal from outside the LSI is input to the input buffer circuit 1 and from there to the block 31. The output of block 31 becomes the input of block 32 and selection circuit 4. The output of the block 32 is input to the block 33 and the selection circuit 4. The 0 selection circuit 4 switches between the output signal of the block 31, the output signal of the block 32, and the output of the block 33 and inputs it to the output buffer circuit 2.

Thereby, by switching the selection circuit 4, the state value of the output signal of each block can be observed from the LSI external output bin.

Furthermore, the present invention also includes a configuration in which not only signals between blocks but also signal lines are drawn out from arbitrary points in the internal circuit and are switched and outputted by the selection circuit 4.

FIG. 2 shows a second embodiment of the invention. Referring to FIG. 2, this embodiment consists of an input buffer circuit 1 that inputs signals from the outside, an output buffer circuit 2 that supplies output signals to output terminals, and an internal circuit that can divide a plurality of blocks 31 to 33 in parallel. circuit and a selection circuit 5 that supplies signals to each block
1 to 53, and a selection circuit 4 that selects signals from each block.

An input signal from outside the LSI is input to the input buffer circuit 1, and from there to the selection circuits 1-53. L.S.
During the I test, selection circuits 51-53 select input signals from outside the LSI and output them to blocks 31-33.

During normal operation during LSIS testing, normal signals from other blocks or input buffer circuit 1 are selected,
Output to blocks 31-33. The outputs of blocks 31 to 33 are input to selection circuit 4. The selection circuit 4 switches the output signal of the block 31 , the output signal of the block 32 , and the output signal of the block 33 and inputs them to the output buffer circuit 2 .

This allows you to test each block and LS
The ratio of the number of gates in the LIS internal circuit to be tested to the number of I external output pins is reduced, making LSI testing easier.

FIG. 3 shows a third embodiment of the invention. Referring to FIG. 3, this embodiment includes an input buffer circuit 1 that inputs signals from the outside, an output buffer circuit 2 that supplies signals to an output terminal, and an internal circuit that can be divided into a plurality of blocks 31 to 33. , and selection circuits 51 to 53 connected to each block and capable of selecting each block.

An input signal from outside the LSI is input to the input buffer circuit 1, and from there to the block 31 and the selection circuit 51. The output of the block 31 becomes the input of the selection circuit 51. The selection circuit 51 switches between the output signal of the block 31 and the signal from the high power buffer circuit 1 bypassing the block 31 and inputs the signal to the block 32 and the selection circuit 52 .

The output of block 32 becomes the input of selection circuit 52. The selection circuit 52 selects the output signal of the block 32 and the output signal of the block 32.
The signal from the selection circuit 51 bypassed is switched and inputted to the block 33 and the selection circuit 53. block 33
The output of 0 is input to the selection circuit 53. The 0 selection circuit 53 switches between the output signal of the block 33 and the signal from the selection circuit 52 bypassing the block 33, and inputs the signal to the output buffer circuit 2.

Thereby, by switching the selection circuits 51 to 53, it is possible to bypass any block, and it is possible to test only the blocks that are not bypassed. That is, for blocks that do not bypass, LS
The ratio of the number of gates in the LSI internal circuit to be tested to the number of I external output bins is reduced, making LSI testing easier.

Furthermore, as another embodiment, a configuration in which a bypass circuit is provided only for an arbitrary block is included in the present invention. In this case, there is an advantage that the amount of hardware can be reduced compared to the third embodiment shown in FIG.

Further, although the three embodiments described above are described with respect to the case where the internal circuit is divided into three, the present invention also includes a configuration in which the internal circuit is divided into an arbitrary number of blocks.

〔Effect of the invention〕

As described above, the present invention has the effect of facilitating LSI testing by dividing the internal circuitry during testing of highly integrated LSIs.

[Brief explanation of drawings]

FIG. 1 shows a first embodiment of the invention, FIG. 2 shows a second embodiment of the invention, and FIG. 3 shows a third embodiment of the invention. 1... Input buffer circuit, 2... Output buffer circuit, 31-33... Internal circuit block, 4.51-53
...Selection circuit.

Claims (1)

[Claims] 1. An internal circuit, an input buffer circuit for supplying an input signal from an external terminal to the internal circuit, and an output buffer circuit for supplying an output signal from the internal circuit to the external terminal. The LSI is characterized in that it has a group of extraction signals at any point in the internal circuit, and a selection circuit that switches between the extraction signal group and a signal group output to the outside of the LSI and supplies it to an output buffer circuit. LSI test circuit. 2. In an LSI having an internal circuit, an input buffer circuit for supplying an input signal from an external terminal to the internal circuit, and an output buffer circuit for supplying an output signal from the internal circuit to the external terminal, A block in which the internal circuit is divided into a plurality of blocks, a first signal group distributed from the input buffer circuit to each block, and a second signal group provided on the input side of each block between the first signal group and the internal circuit. a first selection circuit that switches between a signal group and supplies the signal group to each block; and a first selection circuit that receives the output signal group of each block and switches the output signal group of a specific block among the plurality of blocks to an output buffer circuit. 1. An LSI test circuit comprising: a second selection circuit that supplies a second selection circuit; 3. In an LSI having an internal circuit, an input buffer circuit for supplying an input signal from an external terminal to the internal circuit, and an output buffer circuit for supplying an output signal from the internal circuit to the external terminal, A block in which the internal circuit is divided into a plurality of blocks, an input signal group of an arbitrary block among the plurality of blocks, and an output signal group of the block are switched, and the output signal group is switched to a block other than the block. 1. An LSI test circuit comprising: a selection circuit for supplying input signals.