JPH0458326A - Computer with built-in program - Google Patents

Abstract

PURPOSE:To reduce the instruction code volume by providing a FIFO memory which replaces a suboperand code having a large number of digits with a series number having a small number of digits and stores the addresses and the data generated with each instruction code in the address O and subsequent addresses at all times. CONSTITUTION:The value accordant with the series number covering the instruction code which uses the same suboperand codes at and after the second time through the instruction code which uses precedently the same suboperand codes for the former instruction code. Then an FIFO memory 12 stores the addresses and the data obtained with execution of each instruction code in accordance with the executing order of the instruction code series. Furthermore a means 10 is provided to read the addresses or the data processed with execution of an instruction code corresponding to the value subject to the series number out of the memory 12 as long as the suboperand code of a read-out instruction code and offers these addresses or data for execution of the instruction codes. Thus it is not required to add the undesired register store instructions into a program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a computer with a built-in program that sequentially reads instruction codes from a storage unit and interprets and executes them.

(Prior Art) A computer with a built-in program sequentially reads out a series of instruction codes (programs) stored in an addressed storage section (memory), and interprets and executes the instruction codes using a central processing unit (CPU). It is configured to perform operations corresponding to. An instruction code usually consists of an operation code indicating the type of instruction (execution, storage, setting, read) and an operand code indicating the object to be processed by the instruction. Generally, the operand code is one that reads necessary data by specifying a memory address. That is, a memory address encoded into a bit string is used as the operand code.

However, in a large-capacity memory, the number of digits in the address is enormous, so encoding this into a bit string requires a large number of bits. Therefore, if the same address is repeatedly specified as an operand code in one program series, a large number of bit strings must be repeatedly written. This made the program redundant and required a large amount of memory capacity to store it.

In order to improve this problem, a method has been adopted in which a small number of readable and writable registers are provided separately from the memory, and addresses and data used multiple times as operand codes are temporarily stored. According to this, the number of registers is extremely small compared to the number of memory addresses, so
By storing the register number as an operand code, the number of bits can be reduced.

In other words, when the same operand code is used in multiple instruction codes in a program series, the register number in which the operand code is stored should be written in the instruction code that uses the operand code from the second time onwards. can eliminate the above drawbacks.

However, in this method, it is necessary to add an instruction to store the operand code in a register to the operand code that is reused in the instruction code series of the program. In other words, it is necessary to write an extra operand code storage instruction specifying a register number immediately after each instruction code that includes an operand code to be reused, which increases the amount of the program.

Another possible method is to sequentially allocate the operand codes of the instruction code series to a limited number of registers, and when the registers become full, the first register is emptied and reassigned.

At this time, it is necessary to constantly monitor the register number in which the operand code of the currently targeted instruction code should be stored. In other words, the sequence order of instruction codes and register numbers do not correspond, so when programming (compilation work of source programs), it is necessary to determine what register number corresponds to the instruction code and select the desired register number ( This required the tedious work of writing registers containing the necessary operand codes into the instruction code.

(Problem to be solved by the invention) In this way, in the conventional computer with a built-in program,
A method has been adopted in which a small number of registers are provided and operand codes to be reused are stored in the registers, but this requires adding extra register storage instructions to many locations in the program, making the program redundant. . Furthermore, since the instruction code series and register numbers do not correspond, there is a drawback that the register numbers must be constantly monitored during programming.

SUMMARY OF THE INVENTION An object of the present invention is to provide a computer with a built-in program that does not require adding an extra register storage instruction to a program and does not require checking register numbers during programming.

[Structure of the invention]

(Means for Solving the Problems) The present invention sequentially reads an instruction code series consisting of a sub-operation code indicating the type of instruction and a sub-operand code indicating the target of the instruction from memory by addressing, and transfers the read instruction code to the CPU. In a built-in computer that interprets and executes a program, an instruction code that uses the same sub-operand code for the second time or later is determined by the number of series (number of instruction codes) from the instruction code to the instruction code that previously used the same sub-operand code. ) is stored. Furthermore, there is a first-in, first-out memory that sequentially stores addresses and data obtained (or used) by the execution of each instruction code in association with the execution order of the instruction code series, and a first-in, first-out memory that stores the addresses and data obtained (or used) by the execution of each instruction code sequentially, and the sub-operand codes of the read instruction codes are stored in accordance with the number of series. If the value is a value, the address or data processed by the execution of the instruction code corresponding to this value (in other words, the instruction code executed the number of sequences earlier than the read instruction code) is read from the first-in, first-out memory, and this is executed by the instruction in question. The method is characterized by comprising means for executing the code.

(Operation) According to the present invention, the (
(or used) addresses and data are stored in first-in-first-out memory according to execution order. Here, the sub-operation execution control unit in the CPU always writes the address and data from address O of the first-in, first-out memory. Therefore, there is no need to write an extra register storage instruction specifying a register number in the program as in the conventional case.

Furthermore, in a first-in, first-out memory, the address and data of the most recently executed instruction code are written to the youngest memory address. Here, the value according to the number of sequences (instruction code number) from the currently executed instruction code to the previously executed instruction code corresponds directly to the address of the previously executed instruction code and the memory address where the data is stored. are doing. Therefore, during programming, when finding the storage address of the previously used operand code, it is sufficient to simply write the value according to the number of series from the current instruction code to the instruction code that used the operand code first. In other words, it is no longer necessary to constantly check the register number during programming as in the conventional method.

(Embodiment) Hereinafter, an embodiment of a built-in program computer according to the present invention will be described with reference to the drawings. FIG. 1(a) is a diagram showing the format of the instruction code according to this embodiment, FIG. 1(b)
1 is a diagram showing the format of an instruction code consisting of a conventional extension section. Here, one instruction code consists of a sub-operation code and a sub-operand code (the first
The upper part of Figure (a) is substantially the same as the conventional operation code and operand code, but in this embodiment, as shown in the least significant bit of the sub-operand code, the operand code is a normal operand code and the number of sequences is written. (It is called this way because it includes a flag that identifies it.)
. As shown in FIG. 1(a), an instruction code whose least significant bit is 0 includes a sub-operation code indicating the type of instruction in its upper two bits. Here, there are four types: "execution", "storage", "setting", and "reading". Bits higher than this sub-operation code are sub-operand codes indicating the target of the instruction.

Here, as shown in FIG. 1(b), the upper bit of an instruction code whose least significant bit is 1 is an extension of the sub-operand code of the immediately preceding instruction code. Such extension can be performed multiple times by consecutively using instruction codes whose least significant bit is 1 (this extension is used when the number of bits of address or data to be used as an operand code is large).

Sub-operand codes are classified into two types depending on their least significant bits. As shown in the upper part of FIG. 1(a), when the least significant bit is 0, the contents of the most significant bit become the target of the instruction (sub-operation code) as is. (What kind of target is considered according to the type of each instruction will be described later.) This upper instruction code is used when the same sub-operand code does not appear before in the program. Next, as shown in the lower part of Figure 1(a), if the least significant bit is 1, the address or data generated by the previous instruction code (the address or data here is simply a name as an index) , and is irrelevant to the actual address or data (described later). Here, when the bit next to the least significant bit is O, it is an address specification, and when it is 1, it is a data specification. The integer value represented by the remaining bits excluding these lower two bits indicates the value according to the number of sequences, that is, the corresponding value of the number of codes from the relevant instruction code to the past instruction code that generated the required address or data. There is. This lower instruction code has a sub-operation code that is the same as the sub-operation code of the previous instruction code, and in order to reuse the generated address and data, the value according to the number of series is set to the instruction code. This is stored as a sub-operation code. Furthermore, in programming, when writing sub-operand codes for each instruction code, if the same sub-operand code has already been used in a past instruction code and you want to reuse the address or data processed there in that instruction code, It is sufficient to write a value according to the number of instruction codes (number of series on the program) from the instruction code to the past instruction code as the sub-operand code of the instruction code.

As described above, in the present invention, when each instruction code is executed, two types of information, address and data, are generated. These are processed by four types of sub-operation codes (however, the first
The instruction code (in the case of the instruction code shown in the upper part of Figure (a)) is shown below.

■Execution: Interprets the bit string indicated by the sub-operand code as an operation code and executes it. At this time, as the object (operand) of the operation, previously generated data is implicitly specified and used for each operation (for example, in the case of addition, data from one series before and two series before are used).

Then, the bit string (operation code) is used as an address, and the execution (operation) result is generated as data.

■Storage: Interpret the bit string indicated by the sub-operand code as a memory address, and write the data generated by the immediately previous instruction code there.

Then, the bit string (memory address) is used as an address, and the written data is generated again as data.

■Settings: Use the bit string indicated by the sub-operand code as data necessary for execution. Then, the storage address (program counter value) of the instruction code in the memory is set as an address, and the bit string is generated as data.

B) Read: Interpret the bit string indicated by the sub-operand code as a memory address, and read the stored contents from there. Then, the bit string (memory address) is used as an address, and the read data is generated again as data.

The addresses and data generated by each of these instructions are sequentially stored in a first-in, first-out memory (FIFO) and reused for the execution of subsequent instruction codes that use the same operand code (this will be described later).

FIG. 2 is a block diagram of a computer with a built-in program that interprets instruction codes according to the present invention. Here, a program written using instruction codes in the format shown in FIG. 1 is stored in the main memory 1, and the CPU 2 reads each instruction code one by one and interprets and executes the program. Here program counter 3
The address of address buffer 4. The instruction code is sent to the main memory 1 via the address bus 5, from which the corresponding instruction code is read, and sent via the data bus 6 and data buffer 7 to the sub-operation decoder 8. In the sub-operation decoder 8, the part of the sub-operand code of the instruction code excluding the least significant bit (Fig. 1(a)
) to the left of the dotted line) to the sub-operand code buffer 9
send to In addition, parts of the instruction code other than the above (see Figure 1 (a)
) to the right of the dotted line) is the sub-operation execution control unit 1
Send to 0.

The sub-operation execution control unit 10 increments the program counter 3 by 1 and performs execution control according to the sub-operation code of the fetched portion.

If the fetched instruction word includes a sub-operand code extension, that is, in the format shown in FIG. 1(b), the sub-operand decoder 8 sends the sub-operand code extension to the sub-operand code buffer 9.
Concatenates to the contents of the previous sub-operand code buffer. As long as the fetched instruction word contains the sub-operand code extension, the sub-operation decoder 8 repeats the above operations. When the instruction word including the sub-operation code is fetched again, the sub-operation decoder 8 instructs the sub-operation execution control unit 10 to execute the previous sub-operation. The sub-operation execution control unit 10 already has the sub-operation decoder 8
Based on the previous sub-operation code received from the block, the block sends control codes and timing signals to other blocks to execute the sub-operation. Further, the address and data generated by the execution of the sub-operation are written to the first-in first-out memory (FIFO) 12 through the FIFO write control 11.

Execution of the sub-operation occurs as described below. The sub-operation execution control unit 10 determines, according to the least significant bit of the sub-operand code inputted from the sub-operation decoder 8, whether the content of the sub-operation code is the instruction target itself or a value according to the number of sequences. If the least significant bit is O, the rest excluding this bit (this is the operation code,
memory addresses, constants, etc.) are output from the sub-operand code buffer 9 to the sub-operand bus 13.

If the least significant bit is 1, the remaining part excluding this bit is an address that specifies the address or data (data generated from a previously executed instruction code using the same operand code) stored in the FIFO 12. Therefore, when these are output from the sub-operand code buffer 9 to the sub-operand bus 13, they are supplied to the FIFO 12. At this time, the sub-operation execution control unit 10
By giving an instruction signal to the FO random read control unit 14, the address or data at the corresponding address is read from the PIFO 12 to the sub-operand bus 13.

PIFO12 has the most recently written address as 0, and the beginning (
The new address for writing and the storage address for data are numbered in such a way that the address becomes smaller, with the oldest address as the upper limit. Also, since the address and data generated by one instruction code are written to the FIFO in the order of address and data, the address and data are written at odd addresses in the FIFO.
Data is stored at even addresses. That is, the addresses and data generated by the execution of each instruction code are written into the PIFO 12 in a first-in, first-out manner in correspondence with the execution order of the instruction code series (that is, they are always written from address O of the FIFO). As described above, the part of the sub-operand code excluding the least significant bit corresponds to the FIFO address and at the same time corresponds to the value according to the number of sequences of instruction codes. This is the number of instruction codes from the current instruction code to previous instruction codes with the same sub-operand code (
number of series). Therefore, when executing the current instruction code, the address or data generated by the previous instruction code can be quickly used. In other words, P.I.
In the FO 12, addresses and data are sequentially written from address 0, going backwards from the previous instruction code.

Therefore, the value according to the number of sequences up to the past instruction code having the same operand code directly corresponds to the FIFO address where the necessary address and data are stored. (When reading according to the number of sequences, whether an address or data is required is instructed from the sub-operation execution control unit 10 to the FO 12 by the value of the second least significant bit of the sub-operand code.) , when the bit string excluding the least significant bit from the sub-operand code is output to the sub-operand bus, the sub-operation execution control unit 10 controls each block according to the four types of received sub-operation codes, as shown below. Output a signal. (Here, both cases where the least significant bit is 0.1 are applicable.) (2) Execution 2 If the above-mentioned PI column is the operation code itself, it is sent to the arithmetic unit 15 as is. If the bit string is a FIF○ address (corresponding value of the number of sequences), the FI
The corresponding operation code read from the FO 12 is sent to the calculation unit 15. Sub-operation execution control unit 1
0 instructs the calculation unit 15 to execute, and also sends the sent operation code to the FIFO write control unit 11.
Write to address 0 of IFO 12 (that is, generate it as an address). The arithmetic unit 15 interprets the received operation code, reads data to be used as an operand code from the FIFO via the sub-operand bus 13 as necessary, and performs an operation corresponding to the operation code. (This data is specified for each type of operation code, and if it is an addition, it is the first address of the FIFO.

The result of the operation thus obtained is written to address 0 of the PIFO 12 via the operand bus 13゜FIFO write control unit 11 (that is, it is generated as data. When the above address is written at address 1) a ■Reading: If the above bit string is the read address itself on the main memory 1, it is directly written to the address buffer 4.
．． It is sent to main memory 1 via address bus 5.

If the bit string is a FIFO address, the corresponding address read from the PIFO 12 is sent to the main memory 1. At the same time, the read address is written to address 0 of the PIFO 12 via the FIFO write control unit 11 (generated as an address). Next, data is read from the corresponding address in main memory 1.

The signal is sent to the arithmetic unit 15 via the data bus 6 and data buffer 7. At the same time, the data is written to address 0 of the PIFO 12 via the FIFO write control unit 11 (generated as data. At this time, the above address is written to address 1).

(2) Setting 2 If the above bit string is the data itself (constant, etc.), it is sent to the calculation unit 15 as is. Bit string is FIF
If the address is O, the data read from the PIFO 12 is sent to the calculation unit 15.

At this time, the value of the program counter 11 is written to address 0 of the FIFO 12 via the FIFO write control section 11 according to an instruction from the sub-operation execution control section 10 (generated as an address). Next, the data itself is FIFO
It is written to address 0 of 12 (generated as data).

At this time, the above address is written at address 1).

) Write: If the above bit string is the write address itself, it is directly written to address buffer 4. address bus 5
is sent to main memory 1 via.

If the bit string is a FIFO address, the corresponding address read from the PIFO 12 is sent to the main memory 1. At the same time, the read address is written to address 0 of the PIFO 12 via the FIFO write control unit 11 (generated as an address).

Next, the arithmetic unit 15 reads write data from the PIFO 12 (normally, data generated by the immediately previous instruction code is specified). This write data is written to the corresponding address of the main memory l via the data buffer 7 and the data bus 6. At the same time, the write data is
It is written to address 0 of the PIFO 12 via the IFO write control unit 11 (generated as data. At this time, the above address is written to address 1).

It should be noted that through these processes ω to (a), the contents of the sub-operand code buffer 9 are initialized every time the contents of the sub-operand code buffer 9 are output to the sub-operand bus 13. Then, the part of the next instruction code held in the sub-operation decoder 8, obtained by removing the least significant bit from the sub-operand code, is stored.

Next, we will quote an actual program example, and
The manner in which data is stored in the IFO will be explained in detail.

Now, consider a program that "squares the number stored at address 30fc178□6 in main memory and stores it again at address 30fc178.s" (Xl, where X is 1
(Hexadecimal number = 4 bits)

The multiplication instruction code (operation code) is 30□.

The program itself is stored in main memory 5d70C4□
It is assumed that the data is stored at address 6 or later. As a conventional example, FIG. 3(a) shows a program using only instruction codes in the format shown in the upper part of FIG. 1(a) and FIG. 1(b), and as the present invention, the upper part of FIG. An example of a program using the instruction code in the format shown below is shown in FIG. 3(b). These third
The meaning of each series (step) in the diagram is as follows.

■30fc1781. Read data from address.

Specify the same data as ■■ (read again).

Multiply the data in ■■ and the data in ■.

Write the result of ■■ to address 30fc178□6.

As is clear from comparing FIGS. 3(a) and 3(b), in the present application, a sub-operand code having a large number of digits (bits) can be replaced with a value according to the number of sequences having a small number of digits.

Here, a 4-byte instruction code can be expressed in 2 bytes in step ■■. FIF of the invention in this example
If the changes in the contents of O are shown step by step, the result will be as shown in FIG. (However, 30fc1781. address has 10 as data.
00. , is entered) Here, the data at address 0 in step ■ is written as data to address 0 in step ■ (that is, the data read in step ■ is reused). Furthermore, the address at address 5 in step (2) is written to address 1 in step (2) (that is, the read address in step (2) is reused as the write address).

As described above, in this embodiment, the number of bits for specifying a FIFO address (a value according to the number of series) is extremely smaller than the number of bits for directly specifying a main memory address or the number of data bits required for an operation. Therefore, for instruction codes in which the same sub-operand code appears from the second time onwards,
If you write using only the lower instruction code in figure (a),
The amount of code is significantly reduced compared to conventional programs. Furthermore, according to this method, as the amount of code is reduced, the instruction code fetch time and decoding time can also be reduced in proportion.

〔Effect of the invention〕

According to the present invention, for an instruction code in which the same sub-operand code appears for the second time or later, the sub-operand code is determined based on the number of sequences from the instruction code to the instruction code that previously used the same sub-operand code. All you have to do is store it. In other words, unlike conventional programming, there is no need to constantly check the current register number, which reduces the burden on the operator. Furthermore, the present invention includes a first-in, first-out memory that always stores addresses and data generated by each instruction code starting from address 0.

Therefore, unlike conventional programs, there is no need to write many extra register storage instructions in the program, and the amount of instruction code can be reduced, which has great practical advantages.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram showing an instruction code format of an embodiment of the present invention, FIG. 1(b) is a diagram showing an instruction code format consisting of a sub-operand code extension, and FIG. A block diagram of the built-in program computer according to the embodiment, Fig. 3 (a)
) is a diagram showing an example of conventional program description, FIG. 3(b) is a diagram showing an example of program description according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of FI associated with program execution according to an embodiment of the present invention.
FIG. 3 is a diagram showing how the contents of FO change. 1... Main memory, 2... CPU, 3...
Program counter, 4...address buffer, 5...address bus. 6...Data bus, 7...Data buffer,
8... Sub-operation decoder, 9... Sub-operand code buffer, 10... Sub-operation execution control unit, 11... FIFo write control unit, 12... First-in first-out memory (FIFO), 13...
・Sub-operand bus, 14...FIFO random read control unit, 15...Arithmetic unit representative Patent attorney Nori Chika Ken Yuiζ 005d70C4 005d70C8 005d 70CC 005d 70Ce 1D frame (hey missing) 30fc 1786 (4) 30fc 1786 030fc 178 030fc 178 oooo +oo. 005d 70C8 ■ 030fc 178 005d70C8 ■ 030fc 178 005d70C8 oooo+oo. Q30fc 178 ■ Figure

Claims (16)

[Claims] (1) Sequentially read an instruction code series consisting of a sub-operation code indicating the type of instruction and a sub-operand code indicating the target of the instruction from the storage unit by addressing;
In a computer with a built-in program that interprets and executes this read instruction code with a central processing unit, an instruction code that uses the same sub-operand code for the second time or later is an instruction that previously used the same sub-operand code from the instruction code. A first-in, first-out memory stores values according to the number of sequences up to the code as sub-operand codes, and sequentially stores generated data when each instruction code is executed in association with the execution order of the instruction code sequence, and A computer with a built-in program, characterized in that, when a value according to the number of series is stored as a sub-operand code, the generated data of an instruction code corresponding to the sub-operand code is read out from the first-in-first-out memory and used for execution. (2) The computer with built-in program according to claim 1, wherein the sub-operation code has four types: execution, storage, setting, and reading. (3) The computer with a built-in program according to claim 2, wherein the sub-operand code has an identification bit indicating whether the instruction target itself or a value according to the number of sequences is stored. (4) The generated data is divided into two types, address and data, as an index, and if the sub-operation code is execution, the operation code specified by the sub-operand code is the address of the index, and the execution result is If the sub-operation code is Store, the write address specified by the sub-operand code is the index address, and the write data is the index data. If the sub-operation code is Set, the instruction code is The address in the storage unit is the index address, the data corresponding to the sub-operand code is the index data, and when the sub-operand code is read, the read address specified by the sub-operand code is the index address, 4. A computer with a built-in program according to claim 3, wherein the read data is used as index data. (5) The first-in-first-out memory stores data sequentially such that the smallest memory address is 0, the first memory address is the upper limit, and the address where writing was slower and the memory address holding data become smaller. A computer with a built-in program as described in 4. (6) The first-in, first-out memory stores the data in memory addresses twice the number of series corresponding to the desired instruction code, and stores the data in memory addresses twice the number of series + 1 corresponding to the desired instruction code. Calculator with built-in program. (7) The computer with a built-in program according to claim 4, wherein the sub-operand code has an identification bit indicating whether a value according to the number of sequences is stored as data or an address. (8) When the sub-operation code of the read instruction code is execution and the sub-operand code stores a value according to the number of series, the means for providing the sub-operand code read from the first-in first-out memory according to this value. 8. The computer with built-in program according to claim 7, wherein the computer interprets and executes the sub-operation code as a sub-operation code. (9) The computer with a built-in program according to claim 8, wherein the providing means uses the read sub-operand code as an address and writes the execution result as data to the lowest address of the first-in, first-out memory. (10) When the sub-operand code of the read instruction code is stored and the sub-operand code stores a value according to the number of sequences, the providing means reads the sub-operand code from the first-in first-out memory according to this value. 8. A computer with a built-in program according to claim 7, wherein the data of the immediately preceding execution result is written by using the write address in the storage section. (11) The computer with built-in program according to claim 10, wherein the providing means uses the read sub-operand code as an address and writes the written data as data to the lowest address of the first-in, first-out memory. (12) When the sub-operation code of the read instruction code is set and the sub-operand code stores a value according to the number of series, the providing means reads the address or data from the first-in first-out memory according to this value. 8. The computer with built-in program according to claim 7, wherein the data to be processed is the data to be processed. (13) The computer with built-in program according to claim 12, wherein the providing means writes the data to be processed as data and the address of the instruction code on the storage unit as an address to the lowest address of the first-in, first-out memory. . (14) When the sub-operation code of the read instruction code is read and a value according to the number of series is stored in the sub-operand code, the providing means reads the sub-operand code from the first-in first-out memory according to this value. 8. The computer with a built-in program according to claim 7, wherein the corresponding data is read from the storage section by using the address as a read address of the storage section. (15) The computer with built-in program according to claim 14, wherein the providing means uses the read sub-operand code as an address and writes the read data as data to the lowest address of the first-in, first-out memory. (16) If there are multiple instruction codes that use the same sub-operand code before, the instruction code that uses the same sub-operand code from the second time onward will be different from the processing data corresponding to each instruction code. 2. A value according to the number of sequences from the instruction code to one instruction code using the same sub-operand code is stored as the sub-operand code depending on whether the instruction code is to be processed. Calculator with built-in program.