JPH0457298A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To read the possibility of reloading data before executing the reloading of each sector by reading whether the reloading is enabled or not, before executing reloading to each sector. CONSTITUTION:When erasing or writing is disabled for a certain sector, writing is executed to a non-volatile memory to store the reloading information of the sector. A column decoder selects the sector and a row decoder is completely set in a non-selective state by a signal A. A write circuit is operated by a signal C after applying a positive high voltage to the gate of the memory by a signal B, and writing is executed by applying a high voltage to a bit line. Thus, the output data of the memory to store the information of the sector disabling write becomes 0. When reading this memory, all the word lines in an array are made non-selective by the signal A, the signal B output a select signal due to a read power source and afterwards, it is enough only, to turn a sense amplifier to an operatable state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to an electrically rewritable semiconductor nonvolatile memory having a floating gate.

[Conventional technology]

FIG. 2(a) is a configuration diagram for explaining a conventional semiconductor memory device and a semiconductor memory device according to the present invention.

Flash EEPROM is one type of electrically rewritable semiconductor nonvolatile memory. This memory is of the batch erasing type (all bits are erased at the same time) and cannot be rewritten in byte units, but since one bit can be configured with one memory transistor, it can be used as an inexpensive semiconductor nonvolatile memory. Also, this flash EEPRO
M can also be erased in sector units, so if this were realized, it would attract a lot of attention as a memory that could replace floppy disks.

This flash i15 EEPROM is constructed as shown in FIG. 2(a). In the figure, (1) is a P-type substrate, (21, (3) are N+ diffusion layers, and indicate the drain and source, respectively. The drain (2) is connected to the bit line in the array, and the source (3) is ) is normally at ground potential. (4) is a gate for controlling the memory transistor, and is connected to the word line in the array. (5) is a floating gate that captures electrons by writing. , the state after writing is retained even when the power is turned off.And when erasing, electrons are emitted.(6
) is an insulating film between the floating gate (51 and the substrate (1)), which is formed of an oxide film and is usually about 100 mm thick, and is called a tunnel oxide film. During erasing, the floating gate is This is because the electrons in (5) are released to the drain (2) or source (3).
7) is an insulating film between the gate (4) and the floating gate (5), and is usually formed of an oxide film of 200 Å or more. In addition, the drain (2), source (3), gate (
4) the voltages applied to VD and ■8. (2) Let G be the current flowing through the drain (2) and ID be the current flowing through the drain (2).

Next, the operation will be explained. FIG. 2(b) is a characteristic diagram of Vo to ■D of the memory transistor. The threshold value of a memory in an erased state (hereinafter referred to as VTH) is generally low, and this state is referred to as VTHE. When writing to memory, a high positive voltage is applied to the drain (2) and gate (4), and the source (
3) Set it to ground potential. At this time, a channel is formed between the drain (2) and the source (3), current flows, and hot electrons are generated within the depletion layer of the drain (2). These hot electrons are attracted to the floating gate (5) and captured by the electric field generated by the positive voltage applied to the gate (4). Due to the electrons captured in the floating gate (5), the stop of the memory after writing is shifted to a higher side, resulting in the state of VTHP shown in FIG. 2(b).

When erasing memory, drain (2) or source (3
). Here, it is assumed that a positive high voltage is applied to the drain (2). At this time, when the gate (4) is placed at ground potential and the source (3) is placed in a floating state, the electrons captured by the floating gate (5) due to the electric field between the drain (2) and the floating gate (5) are transferred to the drain by a tunneling phenomenon. (2), and the value of the memory after erasing shifts to the lower side, and the VT of FIG. 2(b)
Return to HH state.

Figure 3 shows a flash EE as a conventional semiconductor memory device.
A block diagram of a PROM is shown. In the figure, 1M bit memories are arranged in an IKXIK (IK=1024) array, each having IK word lines and bit lines. Moreover, input/output data is 8-pit parallel (DO to D7).

There are 17 addresses, 10 of the addresses (A0 to A,)
A book is input to the row decoder through each address buffer, and only one word line is selected by the output of the row decoder. Seven addresses (A, .~A1g) are input to the column decoder through each address buffer, and each input/output (D0~D?) is input to the column decoder through each address buffer.
), one column gate becomes conductive, and the bit line corresponding to this column gate is selected.

At the time of writing, input data of 8 pits (DO to D?) is inputted to the writing circuit through the input buffer, and a selected memory is written according to the contents of the data. Desired data is written by setting the bit line of the memory to be written to a high voltage, and setting the bit line of the memory to which it is not desired to write to a low voltage, for example, a ground potential. At this time, the selected word line is at a high voltage, and the unselected word lines are at a ground potential. The input/output data is "1" before writing, that is, after erasing.
", and becomes "0" after writing.

During reading, as in writing, two word lines and one bit line are selected for each input/output data (DO to D?). The voltage of the selected word line is the read power supply ■.

. The voltage becomes the potential (usually SV), and the sense-up becomes operational. From FIG. 2(b), the word line is ■. . I'm
V o = V c. (vT of memory in erased state)
l is Vmt<Vc. Therefore, a drain current ID flows. Also, ■ of the memory in the write state is vTHP > V
ac, and the drain current ■D does not flow.

The sense amplifier detects whether this drain current ID flows or not, and outputs it from the output buffer.

There are two types of erasure: - In the case of batch erasing, all word lines are set to a non-selected state, that is, set to ground potential, and all column gates are set to a conductive state to set all bit lines to a selected state. Then, all bits can be erased at once by generating a high voltage using an erase circuit. Another type of erasure is sector erasure. Considering the structure of the device, it is most preferable to use one bit line as one sector, and therefore one sector is IK bytes. At this time, all word lines are set to the ground potential as in the case of batch erasing. Then, the column decoder outputs one input/output data (D0~
D? ), by making one column gate conductive and generating a high voltage from the erase circuit, it is possible to erase only one bit line, or one sector. After erasing this sector, data can be rewritten in units of sectors by writing to the same bit line.

In the above description, a control circuit for writing/continuation/erasing is required, but it is omitted here.

[Problem to be solved by the invention]

Since conventional semiconductor storage devices are configured as described above, flash EE, which is a type of conventional nonvolatile memory,
With PROM, it was possible to erase all bits at once and write new data, or to erase in units of sectors and write new data in that sector.
The number of times data can be rewritten in this nonvolatile memory is 104.
About once. Therefore, this nonvolatile memory has been used for applications where the number of rewrites is 104 times or less. In addition, when rewriting is enabled in sector units, the number of rewrites varies depending on the sector, and while most other sectors can be rewritten sufficiently, some sectors have already been rewritten many times and have exceeded 104 times. This may result in a case where the data cannot be rewritten. There is a problem in that the product life of the entire semiconductor memory device is considered to have ended when even one bit cannot be rewritten.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can read whether or not data can be rewritten before rewriting each sector.

[Means to solve the problem]

The semiconductor storage device according to the present invention has a built-in non-volatile memory for storing information as to whether data can be rewritten for each sector, and data can be rewritten before rewriting each sector. This allows you to read out whether the

[Effect]

The semiconductor storage device of the present invention is configured so that it is possible to read out whether or not each sector is rewritable before rewriting the sector, so if it is possible, the sector is rewritten, and if it is not possible, it is rewritten. It is possible to skip sectors and rewrite to other sectors.

〔Example( An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention. In the figure, explanations of the same parts as in the conventional example shown in FIG. 3 will be omitted. What is newly added in this invention is a non-volatile memory for storing rewriting information. In this embodiment, it is placed near the memory array. The nonvolatile memory for storing this rewritten information has the same structure as the nonvolatile memory in the array, with the drain of one memory connected to each bit line, and the source of the memory normally at ground potential. The gates of each memory are commonly connected to form one word line, which is controlled by a signal B output from a control circuit.

The above control circuit is a circuit for controlling writing/reading of information in a non-volatile memory for storing rewrite information, and the signal A selects a word line of the non-volatile memory for storing rewrite information. This signal is used to deselect all memory word lines in the array, and the signal C is used to operate the write circuit when writing information to a non-volatile memory for storing rewrite information. This is a signal to do so.

Next, the operation will be explained. Non-volatile memory for storing rewriting information [initial erased state (VTH=Vr+-
+E). When this memory is read, "1" should be output from each data output (D o to D?). After reading this information, it erases and writes to each sector, but if a certain sector cannot be erased or written, at that point the rewrite information for that sector is written to the nonvolatile memory that stores it. Do this.

At this time, the column decoder selects a non-rewritable bit line sector, and the row decoder is rendered unselected by signal A. Then, a high positive voltage is applied to the gate of the memory by signal B, and a write circuit is operated by signal C to apply a high voltage to the bit line to perform writing.

As a result of this operation, the output data of the memory that stores information on non-rewritable sectors becomes "0". When reading this memory, all the word lines in the array need to be unselected with symbol A, and the selection signal with symbol B needs to be outputted by the read power supply to put the sense amplifier into operation. Then, data may be rewritten in another sector, for example, the next sector, by skipping the sector that cannot be rewritten. When reading/rewriting each sector, first read the memory for storing the rewriting information, and if each data (Dll to D?) is "1", execute it.
If the data is "0", the operation method should be such that it is skipped. Additionally, if rewriting becomes impossible in another sector, "0" is written to the memory that stores the rewriting information for that sector in the same sequence.
All you have to do is write .

Further, the semiconductor memory device according to the present invention outputs the contents of other nonvolatile memories arranged corresponding to each sector by the same means as the means for outputting the contents of the nonvolatile memories arranged in an array to the outside. Even if output is enabled, the same effects as in the above embodiment can be expected.

Further, even if the other non-volatile memories arranged corresponding to each sector have the same structure as the non-volatile memories arranged in an array, the same effect as in the above embodiment can be expected.

Furthermore, the same effects as in the above embodiment can be expected even if the other nonvolatile memories arranged corresponding to each sector are of N-channel type.

〔Effect of the invention〕

As described above, according to the present invention, by incorporating a memory for storing rewrite information for each sector, even if a certain sector cannot be rewritten, the information can be known and skipped, and the number of rewrites can be increased. It is possible to extend the life of the device, which is limited by Further, it is expected that the application will be expanded to include applications that require rewriting more than 104 times.

In addition, it is desirable to configure a structure that does not increase the number of circuits as much as possible, and it is more efficient to use the same means as the means for reading the memory in the array for reading from the memory for storing rewrite information, as in this embodiment. It is true. By making the memory for storing rewrite information the same structure as the memory in the array, there is no need to increase the number of manufacturing steps, and there is an effect that writing/reading can be performed under the same conditions as the memory in the array.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 (, ) is a cross-sectional structure of a nonvolatile memory, and FIG. ID-V
FIG. 3 is a block diagram of a conventional semiconductor memory device. In the figure, 1 is a semiconductor substrate, 2 is a drain, 3 is a source, 4 is a gate, 5 is a floating gate, 6 is an insulating film between the floating gate and the substrate, and 7 is an insulating film between the gate and the floating gate. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] An insulated gate nonvolatile memory formed on a semiconductor substrate, having a floating gate in an insulating film between the gate and channel or on the side of the insulating film, erasable and writable in sector units, and arranged in an array. , place other non-volatile memory corresponding to each sector,
A semiconductor memory device, characterized in that whether or not each sector is erasable and writable is stored.