JPH0456378A - Electronic apparatus - Google Patents
Electronic apparatusInfo
- Publication number
- JPH0456378A JPH0456378A JP16770790A JP16770790A JPH0456378A JP H0456378 A JPH0456378 A JP H0456378A JP 16770790 A JP16770790 A JP 16770790A JP 16770790 A JP16770790 A JP 16770790A JP H0456378 A JPH0456378 A JP H0456378A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ground
- legs
- integrated circuit
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 238000005728 strengthening Methods 0.000 abstract description 3
- 230000010355 oscillation Effects 0.000 description 16
- 230000003321 amplification Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はたとえば高周波機器等に使用する、電子機器に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to electronic equipment used, for example, in high frequency equipment.
従来の技術
従来、この種の電子機器は、回路部品の接続は配線基板
のパターンを用いて電極とパターンを半田付により接続
し、さらにアース回路についてもアースパターンにより
各回路のアースを接続させた構成となっている。Conventional technology Conventionally, in this type of electronic equipment, circuit components were connected by soldering the electrodes and patterns using wiring board patterns, and the ground circuits were also connected to the ground of each circuit using the ground pattern. The structure is as follows.
発明が解決しようとする課題
しかしながら、このような構成では、近年特に盛んにな
ってきた電子機器における集積回路の多機能化や、サイ
ズの小型化により、配線基板に装着された集積回路およ
び周辺回路部品の接続パターンにより、アースパターン
が十分形成できず、高周波回路ではアースポイントの分
散による電力利得の低下等の特性劣化が発生するという
問題があった。Problems to be Solved by the Invention However, with such a configuration, the integrated circuits and peripheral circuits mounted on the wiring board have become increasingly multi-functional and smaller in size in electronic devices, which have become particularly popular in recent years. Due to the connection pattern of the components, a sufficient ground pattern cannot be formed, and in high frequency circuits, there is a problem in that characteristic deterioration such as a decrease in power gain due to the dispersion of the ground points occurs.
本発明は、このような問題点を解決するもので、電子機
器の小型化と高性能化を目的とするものである。The present invention is intended to solve these problems, and aims to reduce the size and improve the performance of electronic equipment.
課題を解決するための手段
上記の目的を達成するために本発明は、シールドケース
内に装着された配線基板と、この配線基板に装着された
複数の電極を有する集積回路と、この集積回路の装着面
の反対面に装着されたアース板と、を備え、前記アース
板には配線基板を貫通する脚部を複数個設け、この脚部
を前記配線基板の集積回路の装着面のアースパターンに
電気的接続させた構成とするものである。Means for Solving the Problems In order to achieve the above objects, the present invention provides a wiring board mounted in a shield case, an integrated circuit having a plurality of electrodes mounted on the wiring board, and a circuit board of the integrated circuit. a grounding plate attached to a surface opposite to the mounting surface, the grounding plate having a plurality of legs penetrating the wiring board, and the legs being connected to a grounding pattern on the mounting surface of the integrated circuit of the wiring board. The configuration is electrically connected.
作用
この構成によれば、集積回路の装着面の反対面に装着さ
れたアース板が、集積回路のアース用電極および周辺回
路のアースを電気的接続させるためアースが十分に強化
される。このため集積回路の装着面は集積回路および周
辺回路部品の実装とパターンの接続のみで良いことから
高密度実装が可能となり、電子機器の小型化とアース強
化による高性能化を図ることができる。According to this configuration, the grounding plate attached to the surface opposite to the mounting surface of the integrated circuit electrically connects the grounding electrode of the integrated circuit and the grounding of the peripheral circuit, so that the grounding is sufficiently strengthened. For this reason, the mounting surface of the integrated circuit only requires mounting the integrated circuit and peripheral circuit components and connecting the patterns, making it possible to implement high-density mounting, making it possible to miniaturize electronic equipment and improve its performance by strengthening the ground.
実施例
以下、本発明の一実施例について図面に基づいて説明す
る。第3図は本発明の一実施例による集積回路を用いた
テレビジョン受像機のチューナのブロック図である。EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings. FIG. 3 is a block diagram of a tuner for a television receiver using an integrated circuit according to an embodiment of the present invention.
第3図において、1は集積回路、2はアンテナ、3は入
力端子、4はVHF/UHF切換回路、5はVHF入力
同調回路、6はVHF高周波増幅回路、7はVHF段間
複同調回路、8はVHF混合回路、9はVHF局部発振
回路、9AはVHF発振同調回路、9BはVHF発振帰
還増幅回路、10はtJHF入力同調回路、11はUH
F高周波増幅回路、12はU HF段間複同調回路、1
3はUHF混合回路、14はUHF局部発振回路、14
AはUHF発振同調回路、J4BはUHF発振帰還増幅
回路、15は中間周波増幅回路、16は中間周波同調回
路、17はローパスフィルタ回路、18は出力端子であ
る。In FIG. 3, 1 is an integrated circuit, 2 is an antenna, 3 is an input terminal, 4 is a VHF/UHF switching circuit, 5 is a VHF input tuning circuit, 6 is a VHF high frequency amplifier circuit, 7 is a VHF interstage double tuning circuit, 8 is a VHF mixing circuit, 9 is a VHF local oscillation circuit, 9A is a VHF oscillation tuning circuit, 9B is a VHF oscillation feedback amplifier circuit, 10 is a tJHF input tuning circuit, 11 is a UH
F high frequency amplifier circuit, 12 is U HF interstage double tuning circuit, 1
3 is a UHF mixing circuit, 14 is a UHF local oscillation circuit, 14
A is a UHF oscillation tuning circuit, J4B is a UHF oscillation feedback amplifier circuit, 15 is an intermediate frequency amplifier circuit, 16 is an intermediate frequency tuning circuit, 17 is a low-pass filter circuit, and 18 is an output terminal.
つぎに、上記のような各構成要素よりなるテレビジョン
受像機のチューナの各構成要素相互の関係と動作につい
て説明する。Next, the mutual relationship and operation of each component of the tuner for a television receiver made up of the above-mentioned components will be explained.
第3図において、アンテナ2より入力端子3に入力され
たテレビジョン受像機のチャンネル信号は、VHF信号
を例にとると、V HF/U HF切換回路4によりV
HF回路に信号が供給され、■HF入力同調回路5で第
1の同調がなされ、つぎにVHF高周波増幅回路6で増
幅される。さらに、VHF段間複同調回路7で第2の同
調がなされ、VHF混合回路8に入力される。そして、
VHF局部発振回路9で発生させた局部発振信号もVH
F混合回路8に入力され、VHF混合回路8で中間周波
数に変換され、中間周波増幅回路15により中間周波増
幅され、ローパスフィルタ回路17を通過し出力端子1
8に出力される。In FIG. 3, taking a VHF signal as an example, the channel signal of the television receiver inputted from the antenna 2 to the input terminal 3 is changed to VHF by the VHF/U HF switching circuit 4.
A signal is supplied to the HF circuit, first tuned by the HF input tuning circuit 5, and then amplified by the VHF high frequency amplifier circuit 6. Furthermore, second tuning is performed in the VHF interstage double tuning circuit 7 and input to the VHF mixing circuit 8. and,
The local oscillation signal generated by the VHF local oscillation circuit 9 is also VH.
It is input to the F mixing circuit 8, converted to an intermediate frequency by the VHF mixing circuit 8, amplified by the intermediate frequency amplification circuit 15, passed through the low-pass filter circuit 17, and output to the output terminal 1.
8 is output.
UHF信号についても、UHF回路により同様に処理さ
れ出力される。The UHF signal is similarly processed and output by the UHF circuit.
ここで、集積回路工には、VHF混合回路8、UHF混
合回路13、VHF発振帰還増幅回路9B、UHF発振
帰還増幅回路14B、中間周波増幅回路15が含まれて
おり、集積回路lの内部のそれぞれの回路と周辺回路の
アースポイントを共通にし強化することが、特に高周波
帯域では安定した動作を得るため必要である。Here, the integrated circuit construction includes a VHF mixing circuit 8, a UHF mixing circuit 13, a VHF oscillation feedback amplification circuit 9B, a UHF oscillation feedback amplification circuit 14B, and an intermediate frequency amplification circuit 15. In order to obtain stable operation, especially in high frequency bands, it is necessary to strengthen the common grounding point between each circuit and the peripheral circuits.
つぎに、上記のように構成されたテレビジョン受像機の
チューナの回路ブロックの実際の配置について説明する
。Next, the actual arrangement of the circuit blocks of the tuner of the television receiver configured as described above will be explained.
第1図(a)は、第3図のブロック図に基づいた本発明
の一実施例によるブロック配置図、第1図(ロ)は本発
明の要部断面図、第2図(a)〜(C)は本発明のアー
ス板の一実施例である。FIG. 1(a) is a block layout diagram according to an embodiment of the present invention based on the block diagram of FIG. 3, FIG. 1(b) is a sectional view of essential parts of the present invention, and FIGS. (C) is an embodiment of the ground plate of the present invention.
第1図において、集積回路1は16ピンの構成となって
おり、1aは電源印加端子、1b・1cは中間周波同調
回路接続端子、1dはローパスフィルタ回路接続端子、
1eは混合回路アース用端子、If・1g・1hはVH
F発振同調回路接続端子、】iは発振帰還増幅回路アー
ス用端子、1j−1に−11はUHF発振同調回路接続
端子、IsはVHF段間複同調回路接続端子、inはV
HF段間複同調回路接続アース用端子、1oはUHF段
間複同調回路接続端子、1pはUHF段間複同調回路接
続アース用端子であり、それぞれ周辺回路とパターンに
より接続されている。In FIG. 1, the integrated circuit 1 has a 16-pin configuration, where 1a is a power supply terminal, 1b and 1c are intermediate frequency tuning circuit connection terminals, 1d is a low-pass filter circuit connection terminal,
1e is the mixed circuit ground terminal, If, 1g, and 1h are VH.
F oscillation tuned circuit connection terminal, ]i is the oscillation feedback amplifier circuit ground terminal, 1j-1 and -11 are UHF oscillation tuned circuit connection terminals, Is is the VHF interstage double tuned circuit connection terminal, in is V
HF inter-stage double-tuned circuit connection ground terminal, 1o is a UHF inter-stage double-tuned circuit connection terminal, and 1p is a UHF inter-stage double-tuned circuit connection ground terminal, each of which is connected to a peripheral circuit by a pattern.
また、19は配線基板で集積回路1および周辺回路部品
を実装しており、2oはアース板で集積回路lの反対面
に装着されており、21はシールドケースで配線基板1
9を装着している。In addition, 19 is a wiring board on which the integrated circuit 1 and peripheral circuit components are mounted, 2o is a grounding plate attached to the opposite side of the integrated circuit l, and 21 is a shield case on which the wiring board 1 is mounted.
I am wearing 9.
つぎに、アース板2oの動作について説明する。Next, the operation of the ground plate 2o will be explained.
集積回13の周辺のアースポイントは第1図(a)に示
すように、AはVHF段間複同調回路7のア−スポイン
ト、BはU)(F段間複同調回路12のアースポイント
、Cは集積回路1の内部の混合回路のアースポイント、
DはUHF発振同調回路14Aのアースポイント、Eは
VHF発振同調回路9Aのアースポイント、Fは集積回
路1の内部の発振帰還増幅回路のアースボイドであり、
それぞれ分散している。この分散したアースポイントを
強化するため配線基板19を貫通させた脚部20’を備
えた金属製のアース板20を集積回路1の反対面に装着
する。この脚部20゛の先端は、アースポイントのパタ
ーンと半田付されることからそれぞれ分散したアースポ
イントが高周波的に共通のアースポイントとなり、安定
した動作を得ることができ、電力利得の低下等の特性劣
化もなくなる。As shown in FIG. 1(a), the grounding points around the integrated circuit 13 are as shown in FIG. , C is the ground point of the mixed circuit inside the integrated circuit 1,
D is the earth point of the UHF oscillation tuning circuit 14A, E is the earth point of the VHF oscillation tuning circuit 9A, and F is the earth void of the oscillation feedback amplifier circuit inside the integrated circuit 1.
Each is dispersed. In order to strengthen the dispersed grounding points, a metal grounding plate 20 having legs 20' extending through the wiring board 19 is mounted on the opposite side of the integrated circuit 1. The tips of the legs 20゛ are soldered to the ground point pattern, so the dispersed ground points become a common ground point at high frequencies, allowing stable operation and reducing power gain. Deterioration of characteristics also disappears.
以上のように、本実施例によれば、配線基板I9を貫通
させた脚部20′を備えたアース板20を集積回路1の
反対面に装着し、この脚部20′の先端をアースポイン
トのパターンと半田付することにより、分散されたアー
スポイントを強化することができる。このため、配線基
板19の集積回路1の装着面のパターンはアースパター
ンを構成させる必要がないことから周辺部品の高密度実
装が可能となり、電子機器の小型化とアース強化による
高性能化を図ることができる。As described above, according to this embodiment, the grounding plate 20 having the legs 20' passing through the wiring board I9 is attached to the opposite surface of the integrated circuit 1, and the tip of this leg 20' is connected to the grounding point. Distributed earth points can be strengthened by soldering with the pattern. For this reason, the pattern on the mounting surface of the integrated circuit 1 of the wiring board 19 does not need to constitute a grounding pattern, which enables high-density mounting of peripheral components, thereby achieving miniaturization of electronic devices and higher performance by strengthening the grounding. be able to.
なお、アース板20の金属部分の面積を広くしておけば
、少くとも配線基板19のアース板20の側の部分につ
いては外部電界の影響を防ぐシールド効果を期待できる
。Note that if the area of the metal portion of the ground plate 20 is made large, a shielding effect can be expected for at least the portion of the wiring board 19 on the ground plate 20 side to prevent the influence of an external electric field.
なお、本発明のアース板20は従来の配線基板のアース
パターンと併用してもよ(、その場合、回路によってい
ずれかを使い分けることにより、共通アースによる他回
路への干渉や帰還を防ぐこともできる。また低周波回路
などでは、アース板20の形を工夫することによっであ
るアースポイントに至る複数回路の回路−アースポイン
ト間の共通インピーダンスによる干渉、帰還を防ぐこと
もできる。Note that the grounding plate 20 of the present invention may be used in combination with the grounding pattern of a conventional wiring board (in that case, by using one of them depending on the circuit, it is possible to prevent interference with other circuits or feedback caused by the common grounding). Furthermore, in low frequency circuits, interference and feedback due to common impedance between multiple circuits leading to a certain ground point and the ground point can be prevented by devising the shape of the ground plate 20.
発明の効果
以上の実施例の説明より明らかなように、本発明によれ
ばシールドケース内に装着された配線基板を貫通させた
脚部を備えたアース板を集積回路の装着面の反対面に装
着し、この脚部の先端をアースポイントのパターンと電
気的接続することにより、分散されたアースポイントを
強化することができ、この結果として配線基板の集積回
路の装着面のパターンはアースパターンを構成させる必
要がないことから周辺部品の高密度実装が可能となり、
電子機器の小型化とアース強化による高性能が図れると
いう効果が得られる。Effects of the Invention As is clear from the above description of the embodiments, according to the present invention, a grounding plate having legs that penetrate a wiring board mounted in a shield case is provided on the opposite side of the mounting surface of the integrated circuit. By attaching the legs and electrically connecting the ends of the legs to the pattern of the grounding points, the distributed grounding points can be strengthened, and as a result, the pattern on the mounting surface of the integrated circuit of the wiring board is connected to the grounding pattern. Since there is no need for configuration, high-density mounting of peripheral components is possible.
The effect is that electronic devices can be made smaller and have higher performance due to stronger grounding.
第1図(a)は本発明の一実施例によるブロック配置平
面図、第1図(b)は同じくその要部側断面図、第2図
(a)〜(C)は同じくアース板の一実施例を示す正面
図、平面図と側面図、第3図は、同しく集積回路を用い
たテレビジタン受像機のチューナのブロック図である。
1・・・集積回路、19・・・配線基板、20・・・ア
ース板、20゛・・・アース板20の脚部、21・・・
シールドケース、A〜F・・・アースポイント。
代理人の氏名 弁理士 粟野重孝 はか1名区
OJ
緘FIG. 1(a) is a plan view of a block arrangement according to an embodiment of the present invention, FIG. 1(b) is a side sectional view of the main part thereof, and FIGS. A front view, a plan view and a side view showing the embodiment, and FIG. 3 are block diagrams of a tuner for a television receiver using an integrated circuit. DESCRIPTION OF SYMBOLS 1... Integrated circuit, 19... Wiring board, 20... Earth plate, 20゛... Leg part of earth plate 20, 21...
Shield case, A to F...Earth point. Name of agent: Patent attorney Shigetaka Awano
Claims (2)
路と、この集積回路の装着面の反対面に装着されたアー
ス板とを備え、前記アース板には前記配線基板を貫通す
る脚部を複数個設け、この脚部を前記配線基板の集積回
路の装着面のアースパターンに電気的に接続させた電子
機器。(1) An integrated circuit having a plurality of electrodes attached to a wiring board, and a grounding plate attached to a surface opposite to the mounting surface of the integrated circuit, the grounding plate having legs that penetrate the wiring board. An electronic device comprising a plurality of legs, the legs of which are electrically connected to a ground pattern on a mounting surface of an integrated circuit of the wiring board.
記載の電子機器。(2) Claim 1 in which the wiring board is mounted inside the shield case
Electronic equipment listed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16770790A JPH0456378A (en) | 1990-06-26 | 1990-06-26 | Electronic apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16770790A JPH0456378A (en) | 1990-06-26 | 1990-06-26 | Electronic apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0456378A true JPH0456378A (en) | 1992-02-24 |
Family
ID=15854724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16770790A Pending JPH0456378A (en) | 1990-06-26 | 1990-06-26 | Electronic apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0456378A (en) |
-
1990
- 1990-06-26 JP JP16770790A patent/JPH0456378A/en active Pending
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