JPH0455826U - - Google Patents
Info
- Publication number
- JPH0455826U JPH0455826U JP9741190U JP9741190U JPH0455826U JP H0455826 U JPH0455826 U JP H0455826U JP 9741190 U JP9741190 U JP 9741190U JP 9741190 U JP9741190 U JP 9741190U JP H0455826 U JPH0455826 U JP H0455826U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- output
- voltage
- bias
- avalanche photodiode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Optical Communication System (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図はこの考案によるＡＰＤ１のバイアス回
路の構成図、第２図は従来技術による光受信回路
の構成図、第３図はＡＰＤ１のブレーク・ダウン
電圧説明図である。
１……ＡＰＤ（アバランシエ・フオトダイオー
ド）、２Ａ……前置増幅器、２Ｂ……可変利得増
幅器、３……検波回路、４Ａ……利得制御回路、
４Ｂ……バイアス制御回路、５……可変バイアス
電源、６……比較器、７Ａ〜７Ｄ……抵抗、７Ｅ
……ＺＤ（ツエナー・ダイオード）、７Ｆ……抵
抗、８……電源Ｖｃｃ供給端子、１１……光入力
信号。
FIG. 1 is a block diagram of the bias circuit of the APD 1 according to this invention, FIG. 2 is a block diagram of the optical receiver circuit according to the prior art, and FIG. 3 is a diagram illustrating the breakdown voltage of the APD 1. 1...APD (avalanche photodiode), 2A...preamplifier, 2B...variable gain amplifier, 3...detection circuit, 4A...gain control circuit,
4B...Bias control circuit, 5...Variable bias power supply, 6...Comparator, 7A to 7D...Resistor, 7E
...ZD (Zener diode), 7F...Resistor, 8...Power supply Vcc supply terminal, 11...Optical input signal.
Claims (1)
シエ・フオトダイオード１と、 アバランシエ・フオトダイオード１の出力信号
を増幅する前置増幅器２Ａと、 前置増幅器２Ａの出力を増幅する可変利得増幅
器２Ｂと、 可変利得増幅器２Ｂの出力を検波する検波回路
３と、 検波回路３の出力を入力とし、可変利得増幅器
２Ｂの利得を制御する利得制御回路４Ａと、 アバランシエ・フオトダイオード１に逆バイア
ス電圧を供給する可変バイアス電源５と、 検波回路３の出力を入力とし、可変バイアス電
源５を制御するバイアス制御回路４Ｂと、 逆バイアス電圧を分圧する第１の抵抗７Ａと第
２の抵抗７Ｂと、 アバランシエ・フオトダイオード１と同方向の
温度係数をもつツエナー・ダイオード７Ｅと、 ツエナー・ダイオード７Ｅに流す電流を制限す
る第３の抵抗７Ｆと、 ツエナー・ダイオード７Ｅの電圧を分圧する第
４の抵抗７Ｃと第５の抵抗７Ｄと、 第１の抵抗７Ａと第２の抵抗７Ｂによる第１の
分圧と第４の抵抗７Ｃと第５の抵抗７Ｄによる第
２の分圧を入力とする比較器６とを備え、 検波回路３の出力により受光パワーに対応した
逆バイアス電圧を可変バイアス電源５に設定し、
比較器６の出力によりブレーク・ダウン電圧以上
にならないようにバイアス制御回路４Ｂを制御す
ることを特徴とする光受信回路のバイアス回路。[Claims for Utility Model Registration] An avalanche photodiode 1 that converts an optical input signal 11 into an electrical signal, a preamplifier 2A that amplifies the output signal of the avalanche photodiode 1, and amplifies the output of the preamplifier 2A. a detection circuit 3 that detects the output of the variable gain amplifier 2B; a gain control circuit 4A that receives the output of the detection circuit 3 as an input and controls the gain of the variable gain amplifier 2B; and an avalanche photodiode 1. a bias control circuit 4B that receives the output of the detection circuit 3 and controls the variable bias power supply 5, and a first resistor 7A and a second resistor that divides the reverse bias voltage. A resistor 7B, a Zener diode 7E having a temperature coefficient in the same direction as the avalanche photodiode 1, a third resistor 7F that limits the current flowing through the Zener diode 7E, and a third resistor that divides the voltage of the Zener diode 7E. 4 resistor 7C and fifth resistor 7D, a first divided voltage by first resistor 7A and second resistor 7B, and a second divided voltage by fourth resistor 7C and fifth resistor 7D. a comparator 6 for setting the variable bias power supply 5 to a reverse bias voltage corresponding to the received light power by the output of the detection circuit 3;
A bias circuit for an optical receiving circuit characterized in that the output of a comparator 6 controls a bias control circuit 4B so that the voltage does not exceed a breakdown voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9741190U JPH0455826U (en) | 1990-09-17 | 1990-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9741190U JPH0455826U (en) | 1990-09-17 | 1990-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0455826U true JPH0455826U (en) | 1992-05-13 |
Family
ID=31837758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9741190U Pending JPH0455826U (en) | 1990-09-17 | 1990-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0455826U (en) |
-
1990
- 1990-09-17 JP JP9741190U patent/JPH0455826U/ja active Pending
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