JPH0454730A - Encoder - Google Patents

Encoder

Info

Publication number
JPH0454730A
JPH0454730A JP2164704A JP16470490A JPH0454730A JP H0454730 A JPH0454730 A JP H0454730A JP 2164704 A JP2164704 A JP 2164704A JP 16470490 A JP16470490 A JP 16470490A JP H0454730 A JPH0454730 A JP H0454730A
Authority
JP
Japan
Prior art keywords
signal
multiplier
encoding
code amount
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2164704A
Other languages
Japanese (ja)
Inventor
Shinya Sumino
眞也 角野
Tatsuro Shigesato
達郎 重里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2164704A priority Critical patent/JPH0454730A/en
Publication of JPH0454730A publication Critical patent/JPH0454730A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To save a data quantity at an area not imparting much effect onto picture quality by using an absolute value processor and an accumulator so as to control a multiplier. CONSTITUTION:An input signal 1 is subjected to orthogonal transformation by an orthogonal transformer 2, the result is fed to an absolute value processor 4 and an accumulator 6, from which a signal 7 being the accumulated signal of an absolute value is calculated. The accumulation is implemented in the unit of a block of orthogonal transformation. The signal 7 is given to a multiplier generator 8, in which the signal is mapped to one of some multipliers and a selected multiplier is outputted as a multiplier 9. The multiplier 9 is multiplied with a signal retarding the signal 3 by a multiplier 12 and the product signal is given to a coder 14, in which the signal is coded. The multiplier 9 is coded simultaneously as the signal 13 and the result is used for correct decoding at a decoder.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、通信コストの削減や記録時間の延長を図るた
めに、画像信号を伝送したり記憶したりするのに必要な
データ量を削減する手段である符号化装置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a means for reducing the amount of data required to transmit and store image signals in order to reduce communication costs and extend recording time. The present invention relates to an encoding device.

従来の技術 従来の符号化装置のブロック図を第6図に示す。Conventional technology A block diagram of a conventional encoding device is shown in FIG.

同図において、lは入力信号、2は入力信号1を直交変
換する直交変換器、3は直交変換器2で直交変換された
信号、14は信号3を符号化する符号化器、15は符号
化器4で符号化された出力信号である。
In the figure, l is an input signal, 2 is an orthogonal transformer that orthogonally transforms input signal 1, 3 is a signal that has been orthogonally transformed by orthogonal transformer 2, 14 is an encoder that encodes signal 3, and 15 is a code This is the output signal encoded by encoder 4.

以上の様に構成された従来の符号化装置においては、入
力信号lが直交変換器2で直交変換される。この直交変
換として適当な関数を選べば、ある変換成分を他の成分
よりも小さくすることが可能となり、情報理論で証明さ
れているように画像信号などのように相関の強い信号は
、大幅なデータ量削減を行なうことができる。更に、直
交変換としてDcT(I散コサイン変換)等を用いると
、高周波成分に対する歪は低周波成分に対する歪よりも
視覚的に日立ちにくい特徴があり、これを用いて殆ど画
質を損なわずに更にデータ量を削減することができる。
In the conventional encoding device configured as described above, the input signal l is orthogonally transformed by the orthogonal transformer 2. By choosing an appropriate function for this orthogonal transformation, it is possible to make certain transformation components smaller than other components, and as proven in information theory, signals with strong correlations such as image signals can be significantly reduced. Data amount can be reduced. Furthermore, when using DcT (I-scattered cosine transform) as an orthogonal transformation, the distortion for high-frequency components is visually less noticeable than the distortion for low-frequency components. The amount of data can be reduced.

発明が解決しようとする課題 しかしながら、以上の様な構成では、画像の局所的な分
布(周波数が高い領域と周波数が低い領域が空間的に集
中している)の性質が全く使われておらず、まだデータ
量削減の余地がある。
Problems to be Solved by the Invention However, in the above configuration, the characteristics of the local distribution of the image (high frequency areas and low frequency areas are spatially concentrated) are not used at all. , there is still room to reduce the amount of data.

本発明はかかる点に鑑み、画質を殆ど損なうことな〈従
来の符号化装置のデータ量を更に削減する符号化装置を
提供することを目的とする。
In view of this, an object of the present invention is to provide an encoding device that further reduces the amount of data compared to conventional encoding devices without substantially degrading image quality.

課題を解決するための手段 本発明は入力信号を直交変換する直交変換手段と、前記
直交変換手段出力信号の絶対値を計算する絶対値計算手
段と、前記絶対値計算手段出力信号を前記直交変換毎に
累積加算する累積加算手段と、前記直交変換出力信号を
前記累積加算手段出力の関数で乗算する乗算手段と、前
記乗算器の乗数と前記乗算手段出力を符号化する符号化
手段を備えたことを特徴とする符号化装置である。また
入力信号を直交変換する直交変換手段と、前記直交変換
手段出力信号を符号化した場合の符号量推定値を計算す
る符号量予測手段と、前記直交変換出力信号を前記符号
量予測手段出力の関数で乗算する乗算手段と、前記乗算
器の乗数と前記乗算手段出力を符号化する符号化手段を
備えたことを特徴とする符号化装置である。さらに、入
力信号を直交変換する直交変換手段と、前記直交変換手
段出力信号の絶対値を計算する絶対値計算手段と、前記
絶対値計算手段出力信号を前記直交変換毎に累積加算す
る累積加算手段と、前記直交変換出力信号を符号化する
圧縮率を前記累積加算手段出力によって制御してその制
御情報も同時に符号化する符号化手段を備えたことを特
徴とする符号化装置である。そして、入力信号を直交変
換する直交変換手段と、前記直交変換手段出力信号を符
号化した場合の符号量推定値を計算する符号量予測手段
と、前記直交変換出力信号を符号化する圧縮率を前記符
号量予測手段出力によって制御してその制御情報も同時
に符号化する符号化手段を備えたことを特徴とする符号
化装置である。
Means for Solving the Problems The present invention provides orthogonal transformation means for orthogonally transforming an input signal, absolute value calculation means for calculating the absolute value of an output signal of the orthogonal transformation means, and orthogonal transformation of the output signal of the absolute value calculation means. a cumulative addition means for cumulatively adding each time, a multiplication means for multiplying the output signal of the orthogonal transform by a function of the output of the cumulative addition means, and an encoding means for encoding the multiplier of the multiplier and the output of the multiplication means. This is an encoding device characterized by the following. Further, an orthogonal transform means for orthogonally transforming an input signal, a code amount prediction means for calculating a code amount estimate value when the output signal of the orthogonal transform means is encoded, and a code amount prediction means for calculating an estimated code amount when the output signal of the orthogonal transform means is encoded; The encoding device is characterized by comprising a multiplication means for multiplying by a function, and an encoding means for encoding the multiplier of the multiplier and the output of the multiplication means. Furthermore, orthogonal transformation means for orthogonally transforming the input signal, absolute value calculation means for calculating the absolute value of the output signal of the orthogonal transformation means, and cumulative addition means for cumulatively adding the output signal of the absolute value calculation means for each orthogonal transformation. and encoding means for controlling the compression rate for encoding the orthogonal transform output signal by the output of the cumulative addition means and encoding the control information at the same time. and an orthogonal transform means for orthogonally transforming an input signal, a code amount prediction means for calculating an estimated code amount when the orthogonal transform means output signal is encoded, and a compression rate for encoding the orthogonal transform output signal. The encoding device is characterized in that it includes encoding means that performs control based on the output of the code amount prediction means and encodes the control information at the same time.

作用 本発明は前記した構成により、直交変換された成分をあ
る基準をもとにして乗算器の乗数を変化させたり圧縮率
を変化させてデータ量を削減するものである。人間の視
覚は、特定の周波数の絶対値が大きい場合には符号化歪
がわかりにくく、また周波数成分の変動が大きい場合に
も歪がわかりにくい特徴がある。そこで、歪がわかりに
くい場合に従来よりもデータ量を削減することによって
、殆ど画質を損なうことなく平均データ量を削減するこ
とが可能となる。これを実視する手段とじて第1の発明
は絶対値の累積和、第2の発明は符号量推定値(一般に
成分の絶対値と符号量は連動している)の値で乗算手段
の乗数を制御している。
Operation The present invention reduces the amount of data by changing the multiplier of the multiplier or changing the compression ratio based on a certain criterion for the orthogonally transformed components using the above-described configuration. Human vision has the characteristic that encoding distortion is difficult to detect when the absolute value of a specific frequency is large, and distortion is difficult to detect when fluctuations in frequency components are large. Therefore, by reducing the amount of data compared to the conventional method when the distortion is difficult to understand, it becomes possible to reduce the average amount of data with almost no loss in image quality. The first invention is a cumulative sum of absolute values, and the second invention is a multiplier for multiplying by the estimated code amount value (generally, the absolute value of a component and the code amount are linked). is under control.

また、第3の発明は絶対値の累積和、第4の発明は符号
量推定値の値で符号化手段の圧縮率を制御している。
Further, the third invention controls the compression ratio of the encoding means using the cumulative sum of absolute values, and the fourth invention controls the compression ratio of the encoding means using the value of the estimated code amount.

実施例 第1図は第1の発明の実施例における符号化装置のブロ
ック図である。同図においてlは入力信号、2は入力信
号1を直交変換して直交変換信号3を出力する直交変換
器、4は信号3の絶対値を計算して絶対値信号5を出力
する絶対値化器、6は信号5を累積加算して累積和信号
7を出力する累積加算器、8は信号7から乗数9に変換
する乗数生成器、lOは信号3を絶対値化器4、累積加
算器6および乗数生成器8の処理時間だけ遅延させた信
号11を出力する遅延器、12は信号11を乗数9で乗
算して積信号13を出力する乗算器、14は乗数9と信
号13を符号化して出力信号15を出力する符号化器で
ある。
Embodiment FIG. 1 is a block diagram of an encoding device in an embodiment of the first invention. In the figure, l is an input signal, 2 is an orthogonal transformer that orthogonally transforms input signal 1 and outputs orthogonally transformed signal 3, and 4 is an absolute value converter that calculates the absolute value of signal 3 and outputs absolute value signal 5. 6 is a cumulative adder that cumulatively adds signal 5 and outputs cumulative sum signal 7; 8 is a multiplier generator that converts signal 7 to multiplier 9; lO is an absolute value converter 4 for signal 3, and cumulative adder 6 and a delay device that outputs a signal 11 delayed by the processing time of the multiplier generator 8; 12 a multiplier that multiplies the signal 11 by a multiplier 9 and outputs a product signal 13; and 14 a signal that encodes the multiplier 9 and the signal 13. This encoder outputs an output signal 15.

以上のように構成された本実施例の符号化装置について
、以下その動作を説明する。人力信号lは直交変換器2
で直交変換された後、絶対値化器4と累積加算器6で絶
対値の累積加算信号である信号7が計算される。この累
積加算は直交変換のブロックの単位で行なう。信号7は
乗数生成器8でいくつかの乗数の1つに写像され、選ば
れた乗数が乗数9となる。乗算器12で遅延された信号
3に乗数9が乗算されて、符号化器14で符号化される
。乗数9も信号13と同時に符号化されて、復号化装置
で正しく復号化するために用いられる。第2図は本実施
例の符号化装置で符号化された信号を復号化する復号化
装置のブロック図であり、15は入力信号、16は入力
信号15を復号化して信号17(信号13と同じ)と除
数18(乗数9と同じ)を生成する復号化器、19は信
号17を除数18で除算した商信号20を出力する除算
器、21は直交変換器2の逆変換を行なって出力信号2
2を出力する直交変換器である。この復号化装置の動作
は自明なので省略するが、この復号化装置を用いれば本
実施例の符号化装置で符号化した信号は容易に復号化す
ることができる。
The operation of the encoding device of this embodiment configured as described above will be described below. Human power signal l is orthogonal transformer 2
After the signal is orthogonally transformed, an absolute value converter 4 and a cumulative adder 6 calculate a signal 7 which is a cumulative addition signal of absolute values. This cumulative addition is performed in units of orthogonal transform blocks. Signal 7 is mapped to one of several multipliers in multiplier generator 8, with the selected multiplier being multiplier 9. The signal 3 delayed by the multiplier 12 is multiplied by a multiplier 9 and encoded by the encoder 14. The multiplier 9 is also encoded simultaneously with the signal 13 and is used by the decoding device for correct decoding. FIG. 2 is a block diagram of a decoding device that decodes a signal encoded by the encoding device of this embodiment, where 15 is an input signal, and 16 is a signal 17 (signal 13) obtained by decoding the input signal 15. 19 is a divider that outputs a quotient signal 20 obtained by dividing the signal 17 by the divisor 18, and 21 performs the inverse transformation of the orthogonal transformer 2 and outputs it. signal 2
This is an orthogonal transformer that outputs 2. The operation of this decoding device is self-explanatory and will therefore be omitted, but if this decoding device is used, the signal encoded by the encoding device of this embodiment can be easily decoded.

以上のように本実施例によれば、絶対値化器4と累積加
算器6で乗数を制御することにより、画質に影響の少な
い領域のデータ量を削減することができる。
As described above, according to this embodiment, by controlling the multiplier using the absolute value converter 4 and the cumulative adder 6, it is possible to reduce the amount of data in areas that have little influence on image quality.

第3図は第2の発明の実施例における符号化装置のブロ
ック図である。同図においてlは入力信号、2は入力信
号lを直交変換して直交変換信号3を出力する直交変換
器、23は信号3を符号化した場合の符号量推測値を計
算して推測値信号24を出力する符号量予測器、8は信
号24から乗数9に変換する乗数生成器、10は信号3
を符号量予測器23および乗数生成器8の処理時間だけ
遅延させた信号11を出力する遅延器、12は信号11
を乗数9で乗算して積信号13を出力する乗算器、14
は乗数9と信号13を符号化して出力信号15を出力す
る符号化器である。
FIG. 3 is a block diagram of an encoding device in an embodiment of the second invention. In the figure, l is an input signal, 2 is an orthogonal transformer that orthogonally transforms the input signal l and outputs an orthogonal transformed signal 3, and 23 is an estimated value signal that calculates an estimated code amount when signal 3 is encoded. 8 is a multiplier generator that converts signal 24 into multiplier 9; 10 is signal 3;
12 is a delay device that outputs a signal 11 that is delayed by the processing time of the code amount predictor 23 and the multiplier generator 8;
a multiplier 14 that multiplies by a multiplier 9 and outputs a product signal 13;
is an encoder that encodes the multiplier 9 and the signal 13 and outputs the output signal 15.

以上のように構成された本実施例の符号化装置について
、以下その動作を説明する。入力信号1は直交変換器2
で直交変換された後、符号量予測器23で信号3を符号
化した場合の符号量推測値である信号7が計算される。
The operation of the encoding device of this embodiment configured as described above will be described below. Input signal 1 is orthogonal transformer 2
After orthogonal transformation, the code amount predictor 23 calculates signal 7, which is the estimated code amount when signal 3 is encoded.

この符号量推測値は直交変換のブロックの単位で行なう
。信号24は乗数生成器8でいくつかの乗数の1つに写
像され、選ばれた乗数が乗数9となる。乗算器12で遅
延された信号3に乗数9が乗算されて、符号化器14で
符号化される。乗数9も信号13と同時に符号化されて
、復号化装置で正しく復号化するために用いられる。復
号化装置は第1の実施例と同じものが使用できる。符号
量推測値は画質の直接的な関数ではないので、画質を帯
域的に一定に保つ意味では第1の実施例が優れているが
、符号量の変動が少なく、ある一定の範囲での固定長化
の制御は本実施例の方が優れている。なお、符号量推測
値は必ずしも正確に符号量を計算する必要はなく、符号
量を近似できるような関数をもちいてもよい。
This code amount estimation value is performed in units of orthogonal transform blocks. Signal 24 is mapped to one of several multipliers in multiplier generator 8, with the selected multiplier being multiplier 9. The signal 3 delayed by the multiplier 12 is multiplied by a multiplier 9 and encoded by the encoder 14. The multiplier 9 is also encoded simultaneously with the signal 13 and is used by the decoding device for correct decoding. The same decoding device as in the first embodiment can be used. Since the code amount estimate value is not a direct function of image quality, the first embodiment is better in the sense of keeping the image quality constant across the band, but it is better to keep the code amount constant within a certain range. This embodiment has better control over lengthening. Note that the estimated code amount does not necessarily need to be calculated accurately, and a function that can approximate the code amount may be used.

以上のように本実施例によれば、符号量予測器で乗数を
制御することにより、画質に影響の少ない領域のデータ
量を削減することができる。
As described above, according to this embodiment, by controlling the multiplier using the code amount predictor, it is possible to reduce the amount of data in areas that have little effect on image quality.

第4図は第3の発明の実施例における符号化装置のブロ
ック図である。同図においてlは入力信号、2は入力信
号1を直交変換して直交変換信号3を出力する直交変換
器、4は信号3の絶対値を計算して絶対値信号5を出力
する絶対値化器、6は信号5を累積加算して累積和信号
7を出力する累積加算器、25は符号化器を制御する圧
縮パラメータ26を生成する圧縮制御器、10は信号3
を絶対値化器4、累積加算器6および圧縮制御器25の
処理時間だけ遅延させた信号11を出力する遅延器、1
4は信号11を圧縮パラメータ26で符号化して出力信
号15を出力する符号化器である。
FIG. 4 is a block diagram of an encoding device in an embodiment of the third invention. In the figure, l is an input signal, 2 is an orthogonal transformer that orthogonally transforms input signal 1 and outputs orthogonally transformed signal 3, and 4 is an absolute value converter that calculates the absolute value of signal 3 and outputs absolute value signal 5. 6 is a cumulative adder that cumulatively adds signals 5 and outputs a cumulative sum signal 7; 25 is a compression controller that generates compression parameters 26 for controlling the encoder; 10 is a signal 3;
a delay device 1 that outputs a signal 11 that is delayed by the processing time of the absolute value converter 4, the cumulative adder 6, and the compression controller 25;
4 is an encoder that encodes the signal 11 using compression parameters 26 and outputs an output signal 15.

以上の欅に構成された本実施例の符号化装置について、
以下その動作を説明する。直交変換器2、絶対値化器4
、累積加算器6は第1図に示す実施例と同じ動作をする
ので説明は省略する。累積和が大きい場合には圧縮率を
少し大きくして符号化歪が増加しても視覚的に検知しに
くい。そこで、圧縮制御器25を制御して圧縮率が増加
するように圧縮パラメータ26を制御し、データ量を減
少させることができる。出力信号15は圧縮制御器25
に人力されて、圧縮ffI御器25は平均符号量が一定
になるように圧縮パラメータを制御する。即ち、信号7
が大きいか平均データ量が大きい場合に圧縮率を大きく
し、平均データ量が小さい場合には圧縮率を小さくする
。平均データ量が一定になるように圧縮率を制御する場
合には、信号7で直接圧縮率を変えることにより、第1
の実施例の乗算器や乗数の符号化手段が不要となり、構
成が容易となる。
Regarding the encoding device of this embodiment configured in the above keyaki,
The operation will be explained below. Orthogonal transformer 2, absolute value converter 4
, the accumulative adder 6 operates in the same manner as in the embodiment shown in FIG. 1, so a description thereof will be omitted. When the cumulative sum is large, it is difficult to visually detect even if the compression ratio is slightly increased and the encoding distortion increases. Therefore, by controlling the compression controller 25, the compression parameter 26 can be controlled to increase the compression ratio, thereby reducing the amount of data. The output signal 15 is the compression controller 25
The compression ffI controller 25 controls the compression parameters so that the average code amount becomes constant. That is, signal 7
The compression ratio is increased when the average amount of data is large or the average amount of data is large, and the compression ratio is decreased when the average amount of data is small. When controlling the compression rate so that the average data amount is constant, the first
The multiplier and multiplier encoding means of the embodiment are not required, and the configuration is simplified.

以上のように本実施例によれば、絶対値化器と累積加算
器と圧縮制御器を用いて圧縮率を累積和と平均データ量
で制御することにより、殆ど画質を劣化させることなく
容易にデータ量を減少させることができる。
As described above, according to this embodiment, by controlling the compression rate using the cumulative sum and average data amount using the absolute value converter, cumulative adder, and compression controller, the compression ratio can be easily achieved without deteriorating the image quality. The amount of data can be reduced.

第5図は第4の発明の実施例における符号化装置のブロ
ック図である。同図において1は入力信号、2は入力信
号1を直交変換して直交変換信号3を出力する直交変換
器、23は信号3を符号化した場合の符号量推測値を計
算して推測値信号24を出力する符号量予測器、25は
符号化器を制御する圧縮パラメータ26を生成する圧縮
制御器、10は信号3を符号量予測器23および圧縮制
御器25の処理時間だけ遅延させた信号llを出力する
遅延器、14は信号11を圧縮パラメータ26で符号化
して出力信号15を出力する符号化器である。
FIG. 5 is a block diagram of an encoding device in an embodiment of the fourth invention. In the figure, 1 is an input signal, 2 is an orthogonal transformer that orthogonally transforms input signal 1 and outputs orthogonal transformed signal 3, and 23 is an estimated value signal that calculates the estimated code amount when signal 3 is encoded. 25 is a compression controller that generates a compression parameter 26 for controlling the encoder; 10 is a signal obtained by delaying signal 3 by the processing time of the code amount predictor 23 and compression controller 25; 14 is an encoder that encodes the signal 11 using the compression parameter 26 and outputs the output signal 15.

以上の様に構成された本実施例の符号化装置について、
以下その動作を説明する。直交変換器2および符号量予
測器23は第3図に示す実施例と同じ動作をするので説
明は省略する。符号量推測値が大きい場合には圧縮率を
少し大きくして符号化歪が増加しても視覚的に検知しに
くい。そこで、圧縮制御器25を制御して圧縮率が増加
するように圧縮パラメータ26を制御し、データ量を減
少させることができる。出力信号15は圧縮制御器25
に入力されて、圧縮制御器25は平均符号量が一定にな
るように圧縮パラメータを制御する。即ち、信号24が
大きいか平均データ量が大きい場合に圧縮率を大きくし
、平均データ量が小さい場合には圧縮率を小さくする。
Regarding the encoding device of this embodiment configured as described above,
The operation will be explained below. Since the orthogonal transformer 2 and the code amount predictor 23 operate in the same manner as in the embodiment shown in FIG. 3, their explanation will be omitted. When the code amount estimate is large, it is difficult to visually detect even if the compression ratio is slightly increased and the encoding distortion increases. Therefore, by controlling the compression controller 25, the compression parameter 26 can be controlled to increase the compression ratio, thereby reducing the amount of data. The output signal 15 is the compression controller 25
The compression controller 25 controls the compression parameters so that the average code amount is constant. That is, when the signal 24 is large or the average amount of data is large, the compression ratio is increased, and when the average amount of data is small, the compression ratio is decreased.

平均データ量が一定になるように圧縮率を制御する場合
には、信号24で直接圧縮率を変えることにより、第2
の実施例の乗算器や乗数の符号化手段が不要となり、構
成が容易となる。
When controlling the compression rate so that the average data amount is constant, the second
The multiplier and multiplier encoding means of the embodiment are not required, and the configuration is simplified.

以上のように本実施例によれば、符号量予測器と圧縮制
御器を用いて圧縮率を符号量推測値と平均データ量で制
御することにより、殆ど画質を劣化させることなく容易
にデータ量を減少させることができる。
As described above, according to this embodiment, by controlling the compression rate using the code amount estimate and the average data amount using the code amount predictor and compression controller, the data amount can be easily controlled without deteriorating the image quality. can be reduced.

なお、本発明の実施例において、直交変換の代わりに直
交変換と類伯の係数をもつ変換を使ってもよい。また、
第1の実施例および第3の実施例において絶対値の累積
和による制御を直交変換のブロック単位の整数倍にして
もよく、第2の実施例および第4の実施例において符号
量推定値による制御を複数の符号化単位の符号量推定値
の和で制御してもよい。更に、第1の実施例と第2の実
施例および第3の実施例と第4の実施例を併用して実施
効果を上げてもよい。
In the embodiments of the present invention, a transform having coefficients similar to the orthogonal transform may be used instead of the orthogonal transform. Also,
In the first embodiment and the third embodiment, the control based on the cumulative sum of absolute values may be made an integral multiple of the block unit of the orthogonal transform, and in the second embodiment and the fourth embodiment, the control based on the code amount estimation value may be used. Control may be performed using the sum of code amount estimates of a plurality of coding units. Furthermore, the first embodiment and the second embodiment, and the third embodiment and the fourth embodiment may be used together to increase the implementation effect.

発明の効果 以上説明したように、本発明によれば、殆ど画質を損な
うことなく、データ量を削減することが出来、その実用
的効果は大きい。
Effects of the Invention As explained above, according to the present invention, it is possible to reduce the amount of data with almost no loss in image quality, and its practical effects are great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は第1の発明における符号化装置の実施例のブロ
ック図、第2図は同実施例の復号化装置のブロック図、
第3図は第2の発明の符号化装置のブロック図、第4図
は第3の発明の符号化装置のブロック図、第5図は第4
の発明の符号化装置のプロ・ンク図、第6図は従来の符
号化装置のブロック図である。 4・・・・・・絶対値化器、6・・・・・・累積加算器
、8・・・・・・乗数生成器、14・・・・・・符号化
器、23・・・・・・符号量予測器、25・・・・・・
圧縮制御器。 代理人の氏名 弁理士 粟野重孝 はか1名菓 図 第 図
FIG. 1 is a block diagram of an embodiment of the encoding device in the first invention, FIG. 2 is a block diagram of the decoding device of the same embodiment,
3 is a block diagram of the encoding device of the second invention, FIG. 4 is a block diagram of the encoding device of the third invention, and FIG. 5 is the block diagram of the encoding device of the third invention.
FIG. 6 is a block diagram of a conventional encoding device. 4... Absolute value converter, 6... Cumulative adder, 8... Multiplier generator, 14... Encoder, 23... ...Code amount predictor, 25...
Compression controller. Name of agent: Patent attorney Shigetaka Awano

Claims (8)

【特許請求の範囲】[Claims] (1)入力信号を直交変換する直交変換手段と、前記直
交変換手段出力信号の絶対値を計算する絶対値計算手段
と、前記絶対値計算手段出力信号を前記直交変換毎に累
積加算する累積加算手段と、前記直交変換出力信号を前
記累積加算手段出力の関数で乗算する乗算手段と、前記
乗算器の乗数と前記乗算手段出力を符号化する符号化手
段を備えたことを特徴とする符号化装置。
(1) Orthogonal transformation means for orthogonally transforming an input signal, absolute value calculation means for calculating the absolute value of the output signal of the orthogonal transformation means, and cumulative addition for cumulatively adding the output signal of the absolute value calculation means for each orthogonal transformation. a multiplication means for multiplying the orthogonal transform output signal by a function of the output of the cumulative addition means; and an encoding means for encoding the multiplier of the multiplier and the output of the multiplication means. Device.
(2)累積加算出力が大きい場合に乗数を小さくし、累
積加算出力が小さい場合に乗数を大きくした請求項(1
)記載の符号化装置。
(2) Claim (1) where the multiplier is made smaller when the cumulative addition output is large and the multiplier is made larger when the cumulative addition output is small.
) described encoding device.
(3)入力信号を直交変換する直交変換手段と、前記直
交変換手段出力信号を符号化した場合の符号量推定値を
計算する符号量予測手段と、前記直交変換出力信号を前
記符号量予測手段出力の関数で乗算する乗算手段と、前
記乗算器の乗数と前記乗算手段出力を符号化する符号化
手段を備えたことを特徴とする符号化装置。
(3) orthogonal transform means for orthogonally transforming an input signal; code amount predicting means for calculating a code amount estimate when the output signal of the orthogonal transform means is encoded; and code amount predicting means for orthogonally transforming the orthogonal transform output signal. An encoding device comprising: a multiplier for multiplying by a function of an output; and an encoding means for encoding the multiplier of the multiplier and the output of the multiplier.
(4)符号量推定値が大きい場合に乗数を小さくし、符
号量推定値が小さい場合に乗数を大きくした請求項(3
)記載の符号化装置。
(4) Claim (3) where the multiplier is made small when the code amount estimate is large and the multiplier is made large when the code amount estimate is small.
) described encoding device.
(5)入力信号を直交変換する直交変換手段と、前記直
交変換手段出力信号の絶対値を計算する絶対値計算手段
と、前記絶対値計算手段出力信号を前記直交変換毎に累
積加算する累積加算手段と、前記直交変換出力信号を符
号化する圧縮率を前記累積加算手段出力によって制御し
てその制御情報も同時に符号化する符号化手段を備えた
ことを特徴とする符号化装置。
(5) orthogonal transformation means for orthogonally transforming an input signal; absolute value calculation means for calculating the absolute value of the output signal of the orthogonal transformation means; and cumulative addition for cumulatively adding the output signal of the absolute value calculation means for each orthogonal transformation. and encoding means for controlling the compression ratio for encoding the orthogonal transform output signal by the output of the cumulative addition means and encoding the control information at the same time.
(6)累積加算出力が大きい場合に圧縮率を大きく、累
積加算出力が小さい場合に圧縮率を小さくした請求項(
5)記載の符号化装置。
(6) Claim in which the compression ratio is increased when the cumulative addition output is large and the compression ratio is decreased when the cumulative addition output is small (
5) The encoding device described.
(7)入力信号を直交変換する直交変換手段と、前記直
交変換手段出力信号を符号化した場合の符号量推定値を
計算する符号量予測手段と、前記直交変換出力信号を符
号化する圧縮率を前記符号量予測手段出力によって制御
してその制御情報も同時に符号化する符号化手段を備え
たことを特徴とする符号化装置。
(7) Orthogonal transform means for orthogonally transforming an input signal, code amount prediction means for calculating a code amount estimate when the output signal of the orthogonal transform means is encoded, and a compression ratio for encoding the orthogonal transform output signal. An encoding device characterized by comprising encoding means for controlling the output of the code amount predicting means and encoding the control information at the same time.
(8)符号量推定値が大きい場合に圧縮率を大きく、符
号量推定値が小さい場合に圧縮率を小さくした請求項(
7)記載の符号化装置。
(8) Claim in which the compression rate is increased when the code amount estimate is large and the compression rate is decreased when the code amount estimate is small (
7) The encoding device described.
JP2164704A 1990-06-22 1990-06-22 Encoder Pending JPH0454730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2164704A JPH0454730A (en) 1990-06-22 1990-06-22 Encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2164704A JPH0454730A (en) 1990-06-22 1990-06-22 Encoder

Publications (1)

Publication Number Publication Date
JPH0454730A true JPH0454730A (en) 1992-02-21

Family

ID=15798293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2164704A Pending JPH0454730A (en) 1990-06-22 1990-06-22 Encoder

Country Status (1)

Country Link
JP (1) JPH0454730A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0276385A (en) * 1988-09-12 1990-03-15 Toshiba Corp Picture data compressor
JPH02105792A (en) * 1988-10-14 1990-04-18 Nippon Telegr & Teleph Corp <Ntt> Orthogonal transform coefficient quantization circuit
JPH02222386A (en) * 1989-02-23 1990-09-05 Toshiba Corp Picture data compressor
JPH03295377A (en) * 1990-04-13 1991-12-26 Fujitsu Ltd Moving picture encoding control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0276385A (en) * 1988-09-12 1990-03-15 Toshiba Corp Picture data compressor
JPH02105792A (en) * 1988-10-14 1990-04-18 Nippon Telegr & Teleph Corp <Ntt> Orthogonal transform coefficient quantization circuit
JPH02222386A (en) * 1989-02-23 1990-09-05 Toshiba Corp Picture data compressor
JPH03295377A (en) * 1990-04-13 1991-12-26 Fujitsu Ltd Moving picture encoding control system

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