JPH04543A - Input/output processing control system - Google Patents

Abstract

PURPOSE:To remove the generation of an event disabling the processing of a specific I/O processing request for a long period by controlling an I/O processing request so as to continuously stored it in a position having a high starting priority order in a queue when the using condition of an I/O device is a route using condition. CONSTITUTION:When the start of I/O processing is impossible and a using condition for holding a certain processing request in a queue is detected as the result of a trial to the I/O processing request by a hardware connected to a CPU as a slave and the using condition is a using condition for the I/O device, the I/O processing request is moved to a position whose starting priority order in the queue is lower than the I/O processing request of another I/O device used in the same route. When the using condition is a route using condition, the I/O processing request is controlled so as to be continuously held on a position whose starting priority order in the queue is high.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art and Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems (Figures 1 and 2) Effects of the Invention [Overview] Hardware (input/output processor (IOP)) under the central processing unit (CPU) manages the path status of input/output processing and the status of input/output devices as a management information block (SCH), and When the Fukuro fi (CPU) executes an input/output command, it converts the input/output control parameters specified by the input/output command, sets it in the management information block (SCH), and inputs it into a queue of input/output processing requests. (SCH queue) management and route selection for the input/output processing using an input/output processing control method in which the above hardware executes the management, and
In the hardware, at least the logical queue (
SCH queue) and each queue (SCH queue)
Regarding the input/output processing control method in a computer system that attempts to start up for the input/output processing request with the highest priority among the central processing unit (CPU) / input/output processor (IOP)
) side's processing speed and the input/output controller (IOC) side's busy release timing have been synchronized, the problem of specific input/output processing requests being kept waiting for a long time has been resolved on the input/output processor (IOP) side. As a result of an attempt for a certain input/output processing request, a busy condition is detected that makes it impossible to start the input/output processing request and keeps the input/output processing request in the above queue (SCH queue). If the input/output device is in use, the input/output processing request is activated in the queue (SCH queue) faster than the input/output processing requests of other input/output devices using the same path. If the in-use condition is a path-in-use condition, the I/O processing request is moved to a position with a lower priority in the queue (SCH queue), and continues to be moved to a position with a higher activation priority in the queue (SCH queue). Manage to retain. Alternatively, when attempting to start an I/O process, if the elapsed time since the I/O process request was issued does not exceed a certain value, the I/O process requests from other I/O devices will If the queue is moved to a low priority position and a certain period of time is exceeded, management is configured to maintain the priority position in the queue at a high priority position.

[Industrial Field of Application] The present invention manages queues of input/output processing requests and selects available input/output paths for each input/output processing request by processing them under a central processing unit (CPU). It relates to the input/output processing control method in computer systems performed by input/output processors (IOPs), especially the processing speed on the central processing unit (CPU)/input/output processor (IOP) side and the busyness on the input/output control unit (IOC) side. The present invention relates to an input/output processing control method that solves the problem of a specific input/output processing request being made to wait for a long time due to synchronization with the release timing.

Due to the diversification of data processing by recent computer systems, input/output devices (Ilo
) is also increasing, and the format of input/output instructions issued by the central processing unit (CPU) is also changing from the conventional start input/output (SI
O) As in the instruction, the central processing unit (CPU) recognizes the operating state of the channel device (CH) and input/output device (Ilo) indicated by the operand of the start input/output (SIO) instruction, and A start input/output (SIO) command is issued, and the channel device (CH) issues a channel control word (CCW).
In the method of reading out the , the overhead on the central processing unit (CPU) increases. Conventionally, a start subchannel (SSCH) command with an operand of
) transfers the selection of the path leading to the input/output device f (Ilo) to the input/output processor (IOP), and the central processing unit (CPU) selects the above-mentioned start sub from the input/output processor (IOP). As soon as the channel (SSCH) command receives a response that the command has been transmitted normally, the next command is executed. When the busy release timing on the device (IOC) side is synchronized, there is a problem in that a specific input/output processing request is kept waiting for a long period of time.

In this case, in the conventional input processing control method described above, the issue timing of the relevant input/output command is shifted in the input/output processing routine etc. in the operating system (O3). In order to reduce the overhead related to input/output processing in a central processing unit (CPU), an input/output processor (IOP) is introduced, and route selection related to input/output processing is performed by the input/output processor (IOP).
In the input/output processing control method performed in P), the operating system (O8) cannot recognize the occurrence of the synchronization state, so it is necessary to deal with it on the input/output processor (IOP) side. It's starting to look like this.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram explaining a conventional input/output processing control method, and (a
) shows an example of a system configuration, (b) shows an example of a subchannel format, (c) shows an example of a format of a subchannel queue control block (SQCB), and (d) shows an example of a format of a subchannel queue control block (SQCB).
l) shows an example of subchannel enqueue processing, and (d2
) shows an example of startup logic for an input/output processor (IOP),
(e) schematically shows the synchronization problem.

In the figure (a), an input/output processor (IOP) 2 manages the state of all input/output devices 51 to 53 and input/output commands (SSCH) issued by a central processing unit (CPU) 1.
In order to manage input/output processing requests/processing based on the
CH) Management information blocks called 201 to 203 are stored in an internal memory (not shown).

An example of the conventional format of the subchannels (SCH) 201 to 203 is shown in FIG.

The subchannels (SCH) 201 to 203 hold information for managing the status of the corresponding input/output devices 51 to 53, and also perform input/output processing requested by software executed by the central processing unit (CPU) 1. hold the request,
Until the activation of the input/output devices 51 to 53 is completed, the input/output processor (subchannel queue) related to the activation of the input/output processing request is placed in a queue (subchannel queue) 20 (described later).
IOP) Waits for process 2 (IOP process).

The above software operates on the central processing unit (CPU) 1. The software internally receives input/output requests (I1) requested from the upper application program.
0 requests) are managed in the form of a queue for each input/output device 51 to 53.

That is, when the input/output processor Cl0P) 2 notifies that the input/output operation of a certain input/output device 51 to 53 has been completed by an input/output interrupt (110 interrupt), the software It is checked whether the next input/output request of 53 does not exist in the above queue, and if it exists, the input/output command (the above-mentioned 5SCH command) is executed.
transmits an input/output processing request to the input/output processor (IOP) 2.

At this time, as mentioned above, the input/output control parameters specified by the operand of the input/output instruction are set by the input/output processor (
IOP) 2 is converted into a format that is easy to process and set in the management information blocks (SCI() 201 to 2o3).

In the figure (a), 111, 112, etc. shown in the central processing unit (CPU 1) are a group of input/output requests corresponding to the input/output device 51, and constitute a queue.Similarly, , 12L122.~, 131, 132.~ are a group of input/output requests corresponding to the input/output devices 52.53.These input/output requests are sequentially transmitted to the input/output processor (IOP) 2 by the software. .

Next, according to figure (b), the above subchannel (SC) I)
The schematic configuration of 201 to 203 will be explained.

As mentioned above, the sub-channels C3CH) 201-2
3 is provided in the internal memory of the input/output processor (IOP) 2 corresponding to each of the above-mentioned input/output devices 51 to 53, and is provided in the internal memory of the input/output processor (IOP) 2. The input/output control parameters indicated by the operands are converted, and the input/output control parameters specified by the operands are converted to 5C)lN
Subchannel (SCH) 201 ~ at the position indicated by α
It is set to 203.

In the figure (b), the [input/output device state descriptor] is for managing the state of the input/output devices 51 to 53, and indicates whether an input/output request exists within the subchannels (SCH) 201 to 203. or whether the input/output process is currently being executed, and if so, whether it is actively transferring data, or if the input/output process is currently being executed.
Do not use the interface with the input/output device 51.
Information such as whether input/output processing preparation/cleanup processing is being performed only on the ~53 side is described. For example, if the most significant bit (indicated by diagonal lines) in this "I/O device status descriptor" is "1', it indicates that the device exists in the queue (subchannel queue) 20, which will be described later. ing.

In addition, this subchannel (ScH) 201 to 2o3
A queue forward pointer and a queue backward pointer are provided, and each subchannel (SCH
) This is a queue pointer for managing 201 to 203 as a queue 2o, and is an identifier for the forward and backward subchannels (SCH) 201 to 203 in the queue.

When the subchannels (SCH) 201 to 203 are located at the head or end of the queue, the identifiers of the subchannels (SCH) 201 to 203 are stored in their respective forward pointers or backward pointers. It is composed of

The "number of connection channels" indicates how many routes there are to reach the input/output devices 51 to 53, for example, an unsigned 8-bit binary value is written.

(b) In the example shown in the figure, there are a maximum of eight routes. Normally, input/output devices 51-53 are addressed by a single unit address (UA), so selecting one route means selecting one channel 100-.

In other words, with respect to a certain input/output device 51 to 53, there are N paths, which means that there are N different channels 100 to 53.
This means that it is connected to.

The identifiers of the connection channels 100 to 100 are written in "connection channel 0" to "connection channel 7."

The input/output processor (IOP) 2 is a subchannel (S
When attempting to start a subchannel (SC
H) When 201 to 203 are acquired from the queue (subchannel queue) 20, the subchannel (SCH)
Among the channels described in 201 to 203, one that is currently available is selected, and for that channel 100 to 100, the subchannel (SCH) is selected.
The channels 100 to 100 transmitting the information described inside the channels 201 to 203 and receiving the transmitted information perform bus arbitration of the input/output interface using the unit address (UA) in the information. , and activates the corresponding input/output device 51.

Generally, the number of queues (subchannel queues) 20 for input/output processing requests created in the input/output processor (IOP) 2 is not one.

If there is only one subchannel, even if channels 100 to 100 unrelated to the first subchannel are usable, they cannot be linked to the queue processing, resulting in poor efficiency. On the other hand, if the number is too large, management becomes complicated, and since mutual queues are selected by a round-tropin method or the like, the average waiting time may actually increase significantly.

For reasons like 2, in many current computer systems, the input/output devices 51 to 53 are shared between the input/output control devices 10, that is, the paths to the input/output devices 51 to 53 are connected to the input/output control devices. Focusing on the fact that the queue (
A subchannel queue) 20 is created.

Subchannel (SCH) 201 shown in figure (b) above
The "queue identification information (SQCB number)" in ~203 can be considered to be the serial number within the system of the input/output control device 10~ to which the input/output devices 51 to 53 are connected.

A numerical value that uniquely specifies this input/output control device 10~ within the system is assigned to the corresponding subchannel (SCH) 201~203.
By setting it in the above-mentioned "queue identification information (SQCB number)" area, for example, at the time of power-on reset, etc., the corresponding subchannel (SC) 201 to 20
When performing queue processing for 3, the subchannel (
SCH) 201 to 203 and the queue (subchannel queue) 20 can be easily established.

The management of the queue (subchannel queue) 20 is also carried out in the internal memory of the input/output processor (IOP) 2.
This is performed by a subchannel queue management block (SQCB) 21 acquired corresponding to the input/output control device 10.

(C) The diagram shows the subchannel queue management block (SQC).
B) 21 format examples are shown.

In this figure, the "input/output controller status descriptor" is information for the input/output processor (IOP) 2 to manage the status of the input/output controller 10 corresponding to this subchannel queue management block (SQCB) 21. area. Here, physical protocol information supported by this input/output control device 10, supported function information, and whether or not there is a condition in which the input/output control device 10 is currently in use are described.

Next, the "number of subchannels in queue" is the number of subchannels (SCH) 201 to 203 enqueued in the queue (subchannel queue) 20 managed by the subchannel queue management block (SQCB) 21. is described.

The next “head subchannel identifier” and “last subchannel identifier” are the head of the queue 20.

Identifiers describing the last subchannels (SCH) 201 to 203 are entered.

"Front 5QCB pointer" [Backward 5QCB pointer J
connects the subchapter queue management blocks (SQCB) 21 provided corresponding to the input/output control device 10 whose length (the number of queued subchannels) is not 0゛. This is a forward/backward pointer for the 5QCB list structure.
21 identifiers are entered.

This is because the structure of the subchannel queue is a two-dimensional structure using the round-robin method (see input/output processor (IOP) 2 in Figure (a)), and valid input/output processing requests cannot be processed. Subchannel to hold (SCH)
Only one subchannel queue management block (SQCB) 21 to which one or more of 201 to 203 are connected is combined into a list and scanned by the input/output processor (IOP) 2, thereby creating the subchannel queue management block (SQCB). The first subchannel (SCH) 201~ of the subchannel queue 20 managed by one of the subchannels 201 and 21.
203 will be taken out and activated.

Next, the central processing unit (CPU) 1 issues an input/output instruction (SS
At the time of issuing the CH), the input/output processor (LOP)
2 enqueues the subchannels (SCH) 201 to 203 requested by the central processing unit (CPU) 1 into the queue (subchannel queue) 20.
subchannel (SCH) from the queue.
The process of extracting (dequeuing) and attempting to start up 201 to 203 will be explained with reference to FIGS. (di) and (d2).

First, in the (dl) diagram, the central processing unit (CPU)
1 issues the above-mentioned input/output command (SSCH), the subchannel number (
), the corresponding subchannel (SC
H) For 201 to 203, the input/output command (SSC
The input/output control parameters indicated by the operand of H) are
The input/output processor (IOP) 2 converts it into an easy-to-use format and sets the corresponding subchannel (SCH) 20.
1 to 203, the previously set r 5QC
B number'' is recognized and enqueued to the subchannel queue 20 indicated by the r5IICB number.

Then, the subchannel queue management block (SQCB)
) 21 are connected to the 5QCB list structure, the input/output processor (IOP) 2 will eventually scan the subchannel (SCH) 20 in the corresponding subchannel queue management block (SQCB) 21.
1 to 203 are missing and are not connected in the 5QCB list structure, the subchannel queue management block (SQCB) 21 is incorporated at the end of the 5QCB list structure and the subchannel enqueue is Finish the process.

Next, as shown in the figure (d2), the input/output processor (IOP) 2 scans the list structure in which the valid subchannel queue management blocks (SQCB) 21 are chained and ) 201 to 203, but by the 5QCB pointer (not shown), the subchannel queue management block (SQCB) 21 pointed to by the current pointer is fetched, and the subchannel queue management block (SQCB) 21 in the subchannel queue management block (SQCB) 21 is fetched. , if the above-mentioned "number of queue subchannels" is 0', then
Since there are no input/output devices 51~ that are under the corresponding input/output control device IO and are requesting input/output processing, the subchannel queue management block ( SQCB) 21
fetch.

(Refer to processing steps 300 to 302 and 310) 5Q above
The beginning/end of the CB list connection is input/output processor <l
0P) It is pointed to by the subchannel queue management block-list control block (SQLCB) 22 in the internal memory of 2, and when the 5QCB pointer is moved to the next subchannel queue management block (SQCB) 21 in the above process. , if the backward pointer of the subchannel queue management block (SQCB) 21 is the 5QCB itself, the head identifier of the 5QLCB 22 is fetched as a new pointer.

The interrelationship between the above-mentioned 5QLCB 22, 5QCB 21, and subchannels (SCH) 201 is conceptually illustrated by the input/output processor (IOP) 2 in the figure (a).
It is a two-dimensional structural diagram of the inside.

Subchannel Queue Management Block (SQCB) 2 above
1, if the "queue subchannel number" is not 0', it means that there are subchannels (SCH) 201 to 203 requesting input/output processing in the subchannel queue 20, so the subchannel Subchannels managed by queue management block (SQCB) 21 Head subchannels (SCH) 201 to 20 of subchannel queue 20
Fetch 3.

The aforementioned channels 100-. Looking at the corresponding input/output devices 51 to 53, if the device is busy or there is no usable path, that is, channels 100 to 100, move the subchannels (SCH) 201 to 203 to the end of the subchannel queue. . (Processing steps 303-30
(Refer to 5) In the above, if there is a device-free and usable route, that is, channel 100~, that channel 10
0 to 20, the subchannels (SCH) 201 to 20
Transmit the information in step 3 and start it up.

If the activation fails (i.e. subchannel (SC8)
Even if it is possible to start up with the information in 201~, the actual input/output device 51~ may still be in a busy state or may be accessed from another input/output control device 10). Subchannel (SCH) 201-2
03 to the end of the subchannel queue 20, but
If activation is successful, the corresponding subchannel (SCH) 201
203 from the subchannel queue 20.

(See processing steps 304, 306 to 310) As mentioned above, in the conventional input/output processing control method,
Since the subchannel queue 20 is managed in a round-robin manner, it is generally a first-in, first-out FIFO)
It is a natural consequence that the above is not satisfied, but FIFO in the subchannel queue 20 under the subchannel queue management block (SQCB) 21 is also not achieved.

That is, in the flow of the IOP activation logic shown in figure (d2) above, in steps 305 and 308 marked (hatched) in the lower right corner, 8 subchannel queues 20 under the subchannel queue management block (SQCB) 21 Then, the first subchannel (SCH) 201
~ is moved to the end, not necessarily the first subchannel (
SCH) 201~ are not executed first.

For this reason, the following events may occur.

In FIG. 3(a), a plurality of input/output requests 111-, 121-, 131- are sent to the input/output devices 51-53 in the main storage (not shown) of the central processing unit (CPU) 1. When present, an input/output request to the input/output device 51 (e.g., 111 as shown) is sent to the subchannel (SCH
) 201 to the input/output device 51 and is activated.

As a result of this input/output processing, when the input/output control device 10 becomes busy, an input/output request (for example, 121) to the input/output device 52 is sent to the input/output processor (IOP) via the subchannel (SCH) 202. 2, the input/output control device 10 is in use, so the subchannel (SCH) 202 is fetched from the subchannel control block (SQ) corresponding to the input/output control device 10.
CB) 21 is moved to the end of the subchannel queue 20. (Step 305 of the flow in the diagram (d2) above)
(See) After this, the processing of the request 111 to the input/output device 51 is completed, and the software executed by the central processing unit (CPU) 1 immediately processes the next input/output request 112 to the input/output device 51 as input/output. command (SSCH), and the information of the input/output request 112 is subchannel (SC) I).
201 and enqueued at the end of the subchannel queue 20.

In general, the conditions during use of the input/output control device 10 may not be canceled for a while even after the input/output processing is completed, depending on the conditions on the input/output control device IO side. When the subchannel (SCH) 202 corresponding to the input/output request 121 for the device 52 meets the busy condition again, the subchannel (SCH) 202 in which the input/output request 121 is stored is moved to the end again. ,
Above, the subchannel (SCH
) 201 becomes higher in priority, and the original priority relationship is repeated.

If the processing speed of the central processing unit (CPU) 1/input/output processor (IOP) 2 side and the busy cancellation timing of the input/output control unit 10 side are synchronized due to the above relationship, the sub The activation of the channel (SCH) 201 is successful again, and the processing of the input/output device 51 corresponding to the input/output request 112 is started. This relationship is schematically shown in Fig. 3(e). Here, the number in parentheses indicates the number of the input/output request.

When the synchronization phenomenon occurs, the above subchannel queue 2
The priority relationship between the subchannel (SCH) 201 and the subchannel (SCH) 202 at 0 is always the same (that is, the priority relationship is that the subchannel (SCH) 201 has a higher priority), and the above input/output request 121 is supported. The input/output device 52 will be unable to operate for a long time.

The above example occurs due to conditions during use of the input/output control device 10, but for example, if three or more input/output devices 51 to 53 as shown in FIG. 3(a) In the case where the channels 100 and 101 are connected, it is easy to imagine that the conditions that the channels 100 to 101 are in use will also occur.

Recently, this phenomenon has been occurring in input/output processors (
When IOP) 2 becomes highly functional and is controlled by a microprogram, one subchannel (SCH)
201 is processed and the next subchannel 202 is fetched, or the processing speed of the central processing unit (CPU) 1 is slower than the processing speed of the input/output processor (IOP) 2. As the speed increases, the same input/output device 5 that the central processing unit (CPU) 1 has
New input/output requests 111, 112 for 1 are transmitted to the input/output processor (IOP) 2, and the chances of inputting them to the subchannel (SCH) 201 increase, increasing the number of synchronization phenomena described above. Become.

In the computer system of the generation in which input/output control was managed in the operating system (O3) executed by the central processing unit (CPU) 1, the above-mentioned
Synchronization issues can arise, for example, from operating systems (O
3) In the above, when an unprocessed input/output processing request was detected in the synchronized state, the issue timing of the input/output command for the input/output processing request was shifted. Like a computer system, the central processing unit (
In order to reduce the overhead on CPU) 1, most of the input/output processing is performed by input/output processor (IOP) 2.
In this case, the input/output processing is an event that is invisible to the operating system (O8), so countermeasures must be taken on the input/output processor (IOP) 2 side.

In view of the above-mentioned drawbacks of the conventional art, the present invention implements the management of queues for input/output processing requests and the process of selecting usable input/output paths for input/output processing requests using hardware, such as an input/output processor (IOP). ), in a computer system that uses
Central processing unit (CPU) / input/output processor (IOP)
) side's processing speed and the input/output controller (IOC) side's busy release timing are synchronized, the problem of specific input/output processing requests being kept waiting for a long time has been resolved on the input/output processor (IOP) side. The purpose of this invention is to provide an input/output processing control method that can perform the following tasks.

[Means to solve the problem]

The above problems are solved by the input/output processing control method configured as follows.

(1) The hardware under the central processing unit (CPU) manages the path status of input/output processing and the status of input/output devices as a management information block (SCH), and the central processing unit (CPU) issues input/output commands. When executing, converting the input/output control parameters specified by the input/output instruction, and managing a queue (SCH queue) of input/output processing requests set and submitted to the management information block (SCH); Using an input/output processing control method in which the hardware executes the input/output processing route selection, and in the hardware,
configuring at least the logical queue (SCH queue) for a group of input/output devices that use the same route;
In a computer system that attempts to start an input/output processing request with the highest priority in each queue (SCH queue), as a result of an attempt for a certain input/output processing request, the startup of the input/output processing fails. If possible, and a busy condition is detected that keeps the input/output processing request in the queue (SCH queue), if the input/output device is busy, the input/output processing request is routed along the same route. Move to a position in the queue (SCH queue) where the startup priority is lower than the input/output processing requests of other input/output devices to be used, and if the busy condition is a route busy condition, , manages the input/output processing request so that it continues to be held at a higher activation priority position in the queue (SCH queue) than the input/output processing requests of other input/output devices using the same path. do.

(2) In the computer system, the time at which the input/output processing request was issued by the central processing unit (CPU) is set in the management information block (SCH) for managing the input/output processing request in the hardware. Means (A).

means (B) for calculating the elapsed time since the input/output processing request was issued by comparing the time information set by the means (A) in the management information block (SCH) with the current time; .

A means (C) for comparing the magnitude of the value calculated by the means (B) and a value given in advance is provided, so that the elapsed time exceeds a certain value when attempting to start the input/output processing. If not, the I/O processing request is moved to a position with a lower priority in the queue (SCH queue) than the I/O processing requests of other I/O devices using the same route, and the If the time exceeds a certain value,
The input/output request is managed so as to be held at a higher priority in the queue (SCH queue) than the input/output processing requests of other input/output devices using the same route.

(Operation) That is, according to the present invention, the queue (subchannel queue) management of input/output processing requests and the process of selecting an input/output path that can be used by the input/output processing requesters are performed by hardware, for example, In a computer system that runs on an input/output processor (IOP), the processing speed of the central processing unit (CPU)/input/output processor (IOP) side and the input/output control unit (
By synchronizing the busy release timing on the IOC) side, the problem of specific input/output processing requests being kept waiting for a long time can be solved on the input/output processor (IOP) side.
Focusing on the fact that the synchronization problem is caused by the fact that first-in, first-out (FIFO) control is not completely performed in the subchannel queue, we , in the case of an input/output device in use condition, it is necessary to allow another input/output device to use the path, so as in the conventional method, the end of the subchannel queue under the relevant subchannel queue control block (SQCB) However, in case of a busy condition on a path such as a channel/I/O controller, the subchannel queue control block (S
QCB) In most cases, all input/output devices under
Since the same route as the one that is currently allowed to be used is used, there is little point in moving the subchannel (SCH) to the end of the subchannel queue. This is left at the beginning of the channel queue.

As a result, the priority order between each subchannel (SCH) in the subchannel queue can be partially fixed without increasing the hardware, for example, by simply changing a part of the microprogram inside the input/output processor (IOP). This has the effect of reducing the number of orders for events in which a specific subchannel (SCH) is not processed for a long time.

In addition, as a means to bring control in the subchannel queue as close as possible to first-in, first-out (FIFO) control, the subchannel (SC) that has remained in the subchannel queue for a certain period of time is
H) into the corresponding subchannel queue control block (SQC
B) It is kept at the head of the subordinate subchannel queue.

Therefore, the timer for time monitoring is set to the input/output processor (I).
Each subchannel (SCH) in the subchannel queue can be
) is partially fixed, which has the effect of reducing the occurrence of events such as a particular subchannel (SCH) not being processed for a long time. Furthermore, if this method is adopted, the residence time inside the subchannel queue is averaged, so disturbance to system performance due to competition between jobs is reduced, and system performance is improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing another embodiment of the present invention, (al),
(a2) shows the change processing step, and (b) shows the "current time entry area" added to the subchannels (SCH) 201~, and in the subchannel queue 20 in the input/output processor (IOP) 2, the subchannel ( SCH)20
In the process of enqueuing and dequeuing 1~.

A means for controlling the data in a first-in, first-out (FIFO) manner as far as possible is a necessary means for carrying out the present invention.

Note that the same reference numerals refer to the same objects throughout the plan.

Below, an example of the configuration of the computer system shown in FIG. 3(a), (di
), FIG. 1 with reference to the processing flow of (d2).

The input/output processing control method of the present invention will be explained with reference to FIG.

Even if the present invention is implemented, the input/output processor (IOP) 2 manages the input/output processing request queue (subchannel queue) 20 and selects an available input/output path for each input/output processing request. The basic operation of input/output processing will not be changed, so it will be omitted here. The explanation will focus on means for avoiding the problem that a specific input/output processing request is not processed for a long time due to timing synchronization, that is, the problem that it is stuck in the subchannel queue 20.

First, one means of the present invention is to add a mark (diagonal line mark) to a part of the microprogram of the input/output processor (IOP) startup logic explained in FIG. 3 (d2), that is, in the lower right corner of FIG. This step replaces step 3o 5308 of "Move subchannel to the end of queue" with the attached flowchart shown in FIG.

That is, fetched subchannels (SCH) 201~
If the input/output device is in use (busy) condition for the input/output processing request condition of At the end of the subchannel queue 2o under the control block (SQCB) 21, the subchannel (
SCH) 201~, but in the case of a busy condition regarding the path of a channel/input/output control device, most of the input/output devices 51~53 under the subchannel queue control block (SQCB) 21 are moved. In this case, the same route as the one currently allowed to be used will be used.
Focusing on the fact that there is little point in moving the subchannel to the end of the subchannel queue 20, the subchannel (SCH) is
201~ are left at the head of the subchannel queue 20.

By doing so, the control in the subchannel queue 20 can be brought as close as possible to first-in, first-out (FIFO) control, and the occurrence of the above-mentioned synchronization problem can be reduced.

Next, another embodiment will be described with reference to FIG.

First, in the subchannel enqueue processing flow shown in FIG. "Enqueue" step is replaced with the flow shown in FIG. 2 (al).

That is, a timer (not shown) is provided in the input/output processor (IOP) 2, and when an input/output command (SSCH) is issued by the central processing unit (CPU) 1, it is enqueued into the subchannel queue 20. At that time, the value of the above-mentioned timer at that time is set to the subchannel (SC) I) 201~
"Current time entry area" added to (see Figure 2 (b))
Record it in

Then, the "move to the end of the subchannel queue" steps 305 and 308 (steps marked with diagonal lines at the lower right) explained in FIG. 3(d2) are replaced with the flow shown in FIG. 2(a2).

That is, when attempting to start the corresponding sub-channel (SCH) 201-, the above-mentioned sub-channel (SCH) 201-
The enqueue time recorded in the "current time entry area" of the subchannel queue 20 is compared with the current time, and the subchannel queue 20 is
If the residence time of the relevant subchannel (SCH) 201~ exceeds a certain value, the movement to the end of the subchannel queue 2o under the relevant subchannel queue control block (SQCB) 21 is not performed, Try to keep it at the beginning.

If the residence time is less than a certain value, the subchannels (SCH) 201 to 201 are moved to the end of the subchannel queue 20 as before.

By doing so, the control in the subchannel queue 20 can be brought as close as possible to first-in, first-out (FIFO) control, and the occurrence of the above-mentioned synchronization problem can be reduced.

As described above, the present invention happens to utilize the central processing unit (CPU) because enqueue and dequeue processing in subchannel queues is based on the round-robin method, and first-in, first-out (FIFO) control is not achieved.
) / Due to the mutual relationship that the processing speed of the input/output processor (IOP) side and the busy cancellation timing of the input/output control device side are synchronized, a specific subchannel (5CH)
Focusing on the fact that the subchannel (SCH) may remain in the subchannel queue for a long time, if the busy condition is an input/output route in use condition, the subchannel (SCH) is moved to the end. Alternatively, monitor the amount of time the subchannel is staying in the subchannel queue, and if the amount of time the subchannel stays exceeds a certain time, prevent the subchannel (SCH) from being moved to the end. In this way,
The feature is that it is made as close as possible to first-in, first-out (CFIFO) control.

(Effects of the Invention) As explained above in detail, the input/output processing control method of the present invention allows the hardware (input/output processor (IOP)) under the central processing unit (CPU) to The status and the status of the input/output device are stored in the management information block (S
When the central processing unit (CPU) executes an input/output command (SSCH), it converts the input/output control parameters specified by the input/output command and sets them in the management information block (SCH). Using an input/output processing control method in which the hardware executes the management of a queue (SCH queue) of input/output processing requests submitted by the user and the route selection of the input/output processing, and in the hardware, For a group of input/output devices that use the same route, at least an input/output processing request that constitutes the above logical queue (SCH queue) and has the highest priority in each queue (SCH queue) In an input/output process in a computer system that attempts to start a certain input/output process request, it is found that the input/output process cannot be started, and the input/output process request is placed in the above queue (SCH queue). ) is detected, and if the busy condition is the busy condition of an input/output device, the input/output processing request is transferred to another input/output device using the same path. The input/output processing request is moved to a position with a lower activation priority in the queue (SCI (queue)) than the input/output processing request, and if the in-use condition is the route-in-use condition, the input/output processing request is ,
The activation is managed so as to continue to be held at a high priority position in the queue (SCH queue). Or
When attempting to start an I/O process, if the elapsed time since the I/O process request is issued does not exceed a certain value, the I/O process request is prioritized in the queue over the I/O process requests of other I/O devices. If the queue moves to a lower position and exceeds a certain period of time, the priority within the queue is maintained at a higher position. For example, by only partially changing the microprogram inside the input/output processor (IOP), the priority order among each subchannel (SCH) in the subchannel queue can be partially fixed, and a specific subchannel (SCH) can be This has the effect of reducing the occurrence of events that are not processed for a long time.

In addition, in the latter case, by adding some hardware such as installing a timer in the input/output processor (IOP) for time monitoring, the priority order between each subchannel (SCH) in the subchannel queue can be partially changed. This has the effect of reducing the occurrence of an event in which a specific subchannel (SCH) is fixed and not processed for a long time. Furthermore, if this method is adopted, the residence time inside the subchannel queue is averaged, so disturbance to system performance due to competition between jobs is reduced, and system performance is improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing another embodiment of the present invention. FIG. 3 is a diagram illustrating a conventional input/output processing control method. In the drawings, 1 is a central processing unit (CPU). 11L112. ~． 121, 122. ~ is an input/output request. 2 is an input/output processor (IOP). 20 is a queue (SCH queue), or subchannel queue 21 is a subchannel queue control block (SQCB)
. 22 is a subchannel queue control block-list control block (SQLCB). 201 to 203 are subchannels (SCH). 10 is an input/output control device, 51. ~53 is an input/output device. 100.101 is the channel. 300 to 310 are processing steps. are shown respectively. Figure (Part 2) (Part 1) Figure (Part 2) Figure (Part 3) Move input/output command (SSCH) at the end (e) Diagram explaining the conventional input/output processing control method Figure 3 (
Part 5)

Claims (2)

[Claims] (1) The hardware (2) under the central processing unit (CPU) (1) uses the management information block (SCH) (20
When the central processing unit (CPU) (1) executes an input/output command, it converts the input/output control parameters specified by the input/output command and stores the management information block (S
The above hardware (2) manages the queue (SCH queue) (20) of input/output processing requests set and submitted to CH) (201~) and selects the route for the input/output processing. Input/output devices (5) that use the output processing control method and that use the same route in the hardware (2)
1 to ), at least the logical queue (SCH queue) (20) is constructed, and each queue (SC
H queue) (20) In a computer system that attempts to start an input/output processing request with the highest priority, as a result of an attempt for a certain input/output processing request, it is impossible to start the input/output processing. When a busy condition for keeping the input/output processing request in the queue (SCH queue) (20) is detected, if the input/output device (51~) is in use, the input/output processing request is stopped in the queue (SCH queue) (20). Move the request to a position where the activation priority is lower in the queue (SCH queue) (20) than the input/output processing requests of other input/output devices (51~) using the same route, and If the in-use condition is a route in-use condition, the input/output processing request is sent to another input/output device (5
1. An input/output processing control method characterized in that management is performed so that activation is maintained at a higher priority position in the queue (SCH queue) (20) than the input/output processing requests of (1 to 1). (2) The hardware (2) under the central processing unit (CPU) (1) uses the management information block (SCH) (20
When the central processing unit (CPU) (1) executes an input/output command, it converts the input/output control parameters specified by the input/output command and stores the management information block (
The above hardware (2) manages the queue (SCH queue) (20) of input/output processing requests set and submitted to SCH) (201~) and selects the route for the input/output processing. For a group of input/output devices (51~) that uses the output processing control method and uses the same path in the hardware (2), at least:
A computer system that configures the above-mentioned logical queue (SCH queue) (20) and attempts to activate an input/output processing request with the highest priority in each queue (SCH queue) (20). In the hardware (2), the time when the input/output processing request was issued by the central processing unit (CPU) (1) is stored in the management information block (SCH) that manages the input/output processing request.
The means (A) set in (201~), the time information set by the means (A) in the management information block (SCH) (201~), and the current time are compared, and the input/output processing A means (B) for calculating the elapsed time since the request was issued, and a means (C) for comparing the value calculated by the means (B) with a value given in advance. , If the elapsed time does not exceed a certain value when attempting to start the input/output processing, the input/output processing request is forwarded from the input/output processing requests of other input/output devices (51~) using the same path. too,
The input/output request is moved to a lower priority position in the queue (SCH queue) (20), and if the elapsed time exceeds a certain value, the input/output request is transferred to another input/output request using the same route. The above queue (SCH queue) (
20) An input/output processing control method characterized in that the priority level in 20) is managed so as to be maintained at a high position.