JPH0453470B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a digital receiver, and in particular to demodulation by removing interference waves from a quadrature amplitude modulation signal in which transmission signals based on other modulation methods coexist as interference waves. The present invention relates to a digital receiving device capable of performing operations.

(Prior Art) As is well known, in digital wireless communication, 16QAM (Quadrature Amplifier) is used for the purpose of highly efficient transmission.
Although the development and practical use of multilevel quadrature amplitude modulation methods such as 64QAM, 64QAM, and 256QAM are progressing, transmission signals based on such multilevel quadrature amplitude modulation methods are inferior to transmission signals based on other existing modulation methods. The interference removal method has become a problem.

As a conventional interference cancellation method, for example, JP-A-58
The one described in Publication No.-131853 is known. This conventional interference wave removal device uses a narrow band filter to extract an interference wave signal from an input signal in which interference waves coexist, controls the amplitude and phase of the extracted interference wave signal, and removes the interference wave thus controlled. By subtracting the signal from the input signal and orthogonally multiplying the subtracted signal and the previously extracted interference wave signal, the in-phase component and quadrature component are used as the amplitude control and phase control signals. The subtraction output is a signal from which interference waves have been removed from the input signal.

(Problems to be solved by the invention) By the way, in the conventional interference wave removal method,
A narrowband filter is used from the viewpoint that the interference wave is buried in the band of the input signal, but in order to improve the C/N (carrier-to-noise power ratio) of the extracted interference wave signal, a narrowband filter is used. It is necessary to make the passband width of the device sufficiently narrow. In this case, only the frequency components of the interference wave signal that pass through the narrowband filter can be removed.

Therefore, in a receiving device equipped with a conventional interference wave removal device, it is possible to sufficiently eliminate the influence of interference waves in which the carrier component is dominant, such as narrowband FM (frequency modulation) waves, and perform signal regeneration. For example, interference waves with non-negligible frequency components over a wide bandwidth, such as FM waves with sidebands, FSK (frequency shift keying) waves, and PSK (phase shift keying) waves, are signals whose effects can be removed. There is an essential problem in that it interferes with playback.

Furthermore, conventional receiving apparatuses are configured to be able to remove intersymbol interference and cross-polarization interference, and in many cases this is usually processed in the IF band, and the circuit elements are analog circuits. When adding the above-mentioned interference cancellation function to such a receiving device, it is convenient for the additional device to be a separate device from the receiving device, considering the convenience of adjusting the circuit elements. Therefore, the above-mentioned interference wave canceling device was proposed for the sole purpose of removing interference waves, but since both devices make extensive use of analog circuits, the addition of this interference wave canceling device made it possible to eliminate interference waves. Conventional receiving devices have a problem in that the size of the device increases.

The present invention was made in view of these problems, and its purpose is to eliminate inter-symbol interference and cross-polarization interference, as well as eliminate other modulations that have non-negligible frequency components over a wide bandwidth. It is an object of the present invention to provide a digital receiving device that can eliminate interference waves based on a method without increasing the scale of the device.

(Means for Solving the Problems) In order to achieve the above object, the digital receiving apparatus of the present invention has the following configuration.

That is, the digital receiving device of the present invention demodulates a digitally modulated signal in an intermediate frequency band in which intersymbol interference exists and a transmission signal based on another modulation method exists as an interference signal, and generates a first demodulated signal in the baseband. a demodulation circuit that forms a multi-column digital signal; an inter-symbol interference compensation circuit that performs inter-symbol interference compensation processing on the first multi-column digital signal by digital processing to form a second multi-column digital signal; Compensation processing for the interference signal is performed on the second multi-column digital signal by digital processing to form a main data signal, and the interference signal is extracted from the second multi-column digital signal by filtering processing. and forms an interference cancellation signal according to the magnitude of the extracted interference signal, and removes the interference signal using the interference cancellation signal thus formed from a second multi-column digital signal delayed appropriately. It is characterized by comprising a circuit and;

(Function) Next, the function of the digital receiving apparatus of the present invention configured as described above will be explained.

The demodulation circuit demodulates an intermediate frequency band digital modulation signal in which there is intersymbol interference and a transmission signal based on another modulation method exists as an interference signal, and forms a first multi-column digital signal that is a baseband demodulation signal. do.

The intersymbol interference compensation circuit digitally performs intersymbol interference compensation processing on the first multi-column digital signal to form a second multi-column digital signal.

The other-system interference compensation circuit extracts an interference signal from the second multi-column digital signal by filtering processing through digital processing, and forms an interference cancellation signal according to the magnitude of the extracted interference signal. Then, the interference signal is canceled by the interference cancellation signal thus formed from the appropriately delayed second multi-column digital signal, and the main data signal is formed.

It can be set appropriately depending on the extraction bandwidth filtering characteristics.

As is well known, in wireless communication, two mutually orthogonal polarized waves are sometimes used from the standpoint of effective frequency utilization, and the receiving side receives these waves using a single antenna. In this case, each of the two polarized waves is received and processed independently, but cross-polarized interference becomes a new problem in this receiving process. Therefore, when applied to a wireless communication system that uses two mutually orthogonal polarized waves, the digitally modulated signal in the intermediate frequency band includes interference signals from different polarized waves. A cross-polarization interference compensation circuit that performs interference signal compensation processing by digital processing is provided in parallel or in series with the inter-symbol interference compensation circuit between the demodulation circuit and the other type interference compensation circuit.

As explained above, according to the digital receiving device of the present invention, instead of being used as a separate device with different functions like the conventional interference wave canceling device, in addition to removing interference signals based on other modulation methods, the digital receiving device A multi-system interference compensation circuit is provided which can realize some of the functions of the receiving device, and the compensation method is performed by digital processing in the same way as inter-symbol interference compensation and cross-polarization compensation. , the equipment scale will not increase. In other-type interference compensation circuits, the predetermined bandwidth to be extracted can be set according to the bandwidth of the interference signal, and the delay time necessary for removing the interference signal can be set appropriately, so that interference signals with a wide band can be detected. But it can be removed. Further, since the delay processing in the other-system interference compensation circuit is performed by a digital circuit, there are advantages such as that deterioration of the main data signal can be reduced compared to analog delay processing.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a digital receiving apparatus according to an embodiment of the present invention. The wireless communication system in this embodiment uses two polarized waves that are orthogonal to each other. Figure 1 shows the receiving system for one polarized wave (hereinafter referred to as "self-polarized wave"), and the receiving system for the other polarized wave. The receiving system for waves (hereinafter referred to as "differently polarized waves") has the same configuration and is therefore not shown.

In FIG. 1, 1 is a demodulation circuit, 2 is an inter-symbol interference compensation circuit, 3 is a cross-polarization interference compensation circuit, 4 is an other-system interference compensation circuit, and the cross-polarization interference compensation circuit 3 is an inter-symbol interference compensation circuit. A case where it is provided in parallel with circuit 2 is shown.

The input signal is a digitally modulated signal in an intermediate frequency band that includes intersymbol interference, interference signals from different polarizations, and interference signals based on other modulation methods such as FM signals, such as a 16QAM (quadrature amplitude modulation) signal. The input signal is first input to the demodulation circuit 1.

The demodulation circuit 1 basically includes a quadrature detector 5, an A/D converter 6, and an A/D converter 7. The quadrature detector 5 performs phase detection on the input signal and detects the phase of the input signal.
form baseband signals P and Q of values.

A/D converters 6 and 7 perform multi-value identification on the four-value baseband signal and convert it into 6-bit binary data signals (P ₁ -P ₆ ) and 6-bit binary data signals (Q ₁ -Q ₆ ).

These 6-bit binary data signals (P ₁ to P ₆ ) and the same signals (Q ₁ to Q ₆ ) are given to the intersymbol interference compensation circuit 2, and are also subjected to cross-polarization interference via this intersymbol interference compensation circuit 2. The signals are given to the compensation circuit 3 as binary data signals (P ₁ to _{P 6} , Q ₁ to _{Q 6} ) from the self-polarized waves.

Note that among the binary data signals (P ₁ to P ₆ , Q ₁ to _{Q 6} ), the binary data signals from the most significant bit to the second bit (P ₁ , P ₂ and Q ₁ , Q ₂ ) are the main data. As is well known, it corresponds to a signal.

The intersymbol interference compensation circuit 2 receives binary data signals (P ₁ to _{P 6} , Q ₁ to _{Q 6} ) and compensates for linear distortion caused by device imperfections, multipath fading, etc. occurring in the propagation path. The intersymbol interference generated and contained in the input signal is compensated for by digital processing. The compensation operation is as described in the document ``Configuration and characteristics of digitized transversal equalizer'' (1986 Institute of Electronics and Communication Engineers National Conference of Communications Division No. 41).

The cross-polarization interference compensation circuit 3 outputs the binary data signals (P ₁ to P ₆ , Q ₁ to Q ₆ ) from the self-polarized waves and the demodulation circuit output of the different polarization input signals, that is, the binary data signals from the different polarizations. Receives data signals (P ₁ to P ₆ , Q ₁ to _{Q 6} ) and removes different polarization interference with the same amplitude characteristics and opposite phase as the different polarization interference signal contained in the self-polarized input signal. A signal is formed by digital processing and is applied to the intersymbol interference compensation circuit 2. The operation of this cross-polarization interference compensation circuit 3 is detailed in the document ``Characteristics of Shift Bit Select Controlled Polarization Interference Compensator'' (1985 IEICE General Conference No. 2301). The explanation will be omitted.

The intersymbol interference compensation circuit 2 digitally adds the different polarization interference cancellation signal to the binary data signal that has undergone intersymbol interference compensation processing, and as a result, the binary data from which intersymbol interference and different polarization interference have been removed is generated. The signals (P ₁ ′ to P ₆ ′) and the signals (Q ₁ ′ to _{Q 6} ′) are applied to the other system interference compensation circuit 4.

The system interference compensation circuit 4 receives a binary data signal (P ₁ '~
a first other-system interference compensation circuit 8 for P ₆ ′);
and a second other-system interference compensation circuit 9 for value data signals (Q ₁ ′ to _{Q 6} ′), both of which have the same configuration, and which eliminate interference signals based on other modulation methods as described later. forming data signals (P ₁ ″~P ₆ ″) and data signals (Q ₁ ″~ _{Q 6} ″).

FIG. 2 shows a first other-system interference compensation circuit 8,
This will be explained below with reference to the same figure. The other type interference compensation circuit includes an interference wave extraction circuit 10, a delay circuit 14,
It basically includes an adder 15, a digital multiplier 16, and a digital correlator 17.

Among the binary data signals P _{1 ′} to P ₆ ′, which are input signals, the data signals from the most significant bit (MSB) to the second bit (P ₁ ′, P ₂ ′) correspond to the main data signal, The data signal from the 3rd bit to the 6th bit (P ₃ ′ to R ₆ ′) indicates how much the 4-level baseband signal P deviates from its original level, and includes interference. Contains signals. Therefore, the binary data signal (P ₁ ′ to _{P 6} ′) is sent to the delay circuit 1.
4, and a binary data signal (P ₃ ' to P ₆ '), which is a part thereof, is supplied to the interference wave extraction circuit 10.

In this embodiment, the interference wave extraction circuit 10 is a D/A
It is composed of a converter 11, a bandpass filter 12, and an A/D converter 13. The D/A converter 11 converts the binary data signal (P ₃ ′ to P ₆ ′) into an analog signal and supplies it to the bandpass filter 12 . The bandpass filter 12 suppresses various noises included in the output of the D/A converter 11, extracts interference signal components, and converts it into an A/A converter.
It is given to the D converter 13. Note that the bandpass filter 12
The pass center frequency and pass band are set variously depending on the interference signal, but if the band of the interference signal is narrow, a tracking filter using a phase synchronization circuit can be used. Finally, A/
The D converter 13 converts the extracted interference signal into 2
Convert to value signal. The required number of bits for this binary signal is at least 3 bits, and in this embodiment, a 3-bit data signal (U1 to U3) is formed and is applied to a digital multiplier 16 and a digital correlator 17.

Here, regarding the configuration method of the interference wave extraction circuit 10, basically the D/A converter 11 can be omitted, and in this case, the first one of the binary data signals (P ₃ ′ to _{P 6} ′) The signal P ₃ ' in the first column may be input directly to the bandpass filter 12. In this method, the S/
Although the N value is slightly degraded, the circuit scale can be reduced.

Note that the interference wave extraction circuit 10 can be replaced with a digital filter, but when the frequency component of the interference signal is near a low frequency, the bandpass filter 12 in the interference wave extraction circuit 10 can be replaced with a low-pass filter. can. When the frequency component of the interference signal is near a low frequency, the interference wave extraction circuit 10 can be replaced by a circuit that calculates the integral value (average value) for a predetermined number of time slots. At this time, the number of time slots for integration is determined by the band of the interference signal, but if the band of the interference signal is narrow, the number of time slots can be increased, and the S/N of the extracted interference signal can be improved. can.

The delay circuit 14 is composed of, for example, a shift register, and receives the same binary data signals (P ₁ ′, P ₂ ′) (P ₃ ′ to _{P 6} ′).
For this, delay processing is performed to compensate for the time delay (bit shift) in the signal path from the interference wave extraction circuit 10 via the digital multiplier 16, and the delayed signal is provided to the adder 15.

The adder 15 adds this delayed signal and the interference cancellation signal outputted by the digital multiplier 16 as described later, and sends the main data signals (P ₁ ″, P ₂ ″) outside the diagram as reproduced data. On the other hand, a binary data signal (P ₃ ″ to P ₆ ″) is applied to the digital correlator 17 .

The digital correlator 17 receives a binary data signal (U
1 to U3) and the binary data signals (P ₃ '' to _{P 6} '') to form a multi-bit control signal, which is applied to the digital multiplier 16 .

The digital multiplier 16 generates binary data signals (U1 to U3) in response to the multi-bit control signal.
is weighted and given to the adder 15 as the interference cancellation signal. That is, the multiplier output (interference cancellation signal) is controlled by the control signal so that it becomes a signal having the same amplitude level and opposite polarity as the interference signal included in the delayed signal.

As a result, the adder 15 generates the main data signals (P ₁ ″, P ₂ ″) from which the interference signal included in the delayed signal has been removed.
and binary data signals (P ₃ ″ to P ₆ ″) are output.

Note that the digital correlator 17 uses two signals called error signals in the binary data signals (P ₃ ″ to P ₆ ″).
Only the value data signal P ₃ ″ may be used.

Next, the delay circuit 14 exhibits a particularly remarkable effect when the interference signal has a relatively wide band. For example, one time slot is
Assuming that the bit shift is 40ns, the bit shift is 2 time slots, and the band of the interference wave signal is ±1MHz, the signal is input to the adder 1 via the interference wave extraction circuit 10 and the digital multiplier 16.
The interference signal input to 5 has a phase shift of 360° x 40 x 10 ^-9 x 2 x 1 x 10 ⁶ = 28.8° at the band edge (that is, the edge 1 MHz apart from the band center). Therefore, if the delay circuit 14 does not exist, even if the multiplier output (interference cancellation signal) is added at the same level as the interference signal and with opposite polarity, there will be a phase shift of 28.8 degrees at the band edge of the interference signal. The polarity is not completely reversed. In other words, the interference signal cannot be completely removed, and the interference signal remains. The time to compensate for the delay can be quite large, and compensating for this in an analog manner degrades the characteristics of the main data signal.However, in the present invention, digital circuits such as shift registers are used, so the main data Not only does it not degrade the signal characteristics, but it also allows you to easily set any delay time.

By the way, in order for the interference wave extraction circuit 10 in the other-system interference wave compensation circuit 4 to extract an interference signal with a good S/N, a binary data signal (P ₃ '~
P ₆ ′, Q ₃ ′ to Q ₆ ′) must not include interference signals other than the interference signal to be extracted, that is, interference signals based on intersymbol interference or cross-polarization interference of the main data signal. It is. Therefore, in the present invention, the intersymbol interference compensation circuit 2 and the cross-polarization interference compensation circuit 3 are provided in advance. By configuring in this way, the multi-symbol interference compensation circuit 2, the cross-polarization interference compensation circuit 3, and the other-system interference compensation circuit 4, which are interference compensation circuits using digital processing, are individually required. Value discriminators (A/D converters 6 and 7) can be shared with each other, reducing the equipment scale.
Furthermore, interference signals based on other modulation methods can be efficiently compensated for without degrading the main data signal.

In the embodiment described above, the cross-polarization interference compensation circuit 3 is provided in parallel with the inter-symbol interference compensation circuit 2. They may be arranged in series, such as in the example shown in FIG.

In addition, the digital modulation signal that is the input signal is
The method is not limited to the QAM method, but may be based on the polyphase PSK method. Furthermore, the interference signal by another modulation method may be an analog signal or a digital signal.

(Effects of the Invention) As explained above, according to the digital receiving device of the present invention, it is not used as a separate device with separate functions like the conventional interference wave canceling device, but is used to cancel interference signals based on other modulation methods. In addition, a multi-system interference compensation circuit that can form the main data signal and realize some functions of the receiving device is provided, and its compensation method is based on digital processing similar to intersymbol interference compensation and cross-polarization compensation. Since this is done, the scale of the device does not increase. With other type interference compensation circuits, the predetermined bandwidth to be extracted can be set according to the bandwidth of the interference signal, and the delay time necessary for removing the interference signal can be set appropriately, so even interference signals with a wide band can be set. Can be removed. Furthermore, since the delay processing in the other-system interference compensation circuit is performed by a digital circuit, there are advantages such as that deterioration of the main data signal can be reduced compared to analog delay processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a digital receiver according to an embodiment of the present invention, and FIG. 2 is a block diagram of the configuration of an interference compensation circuit for other systems. DESCRIPTION OF SYMBOLS 1... Demodulation circuit, 2... Digital type intersymbol interference compensation circuit, 3... Digital type cross polarization interference compensation circuit, 4... Other system interference compensation circuit, 5... Quadrature detector, 6, 7... A/D conversion device, 8...first other-system interference compensation circuit, 9...second other-system interference compensation circuit, 1
0...Interference wave extraction circuit, 11...D/A converter, 12
...bandpass filter, 13...A/D converter, 14...delay circuit, 15...adder, 16...digital multiplier,
17...Digital correlator.

Claims (1)

[Claims] 1. A first multi-column digital signal which is a baseband demodulated signal obtained by demodulating an intermediate frequency band digital modulated signal in which intersymbol interference exists and a transmission signal based on another modulation method exists as an interference signal. a demodulation circuit that forms a signal; an intersymbol interference compensation circuit that performs intersymbol interference compensation processing on the first multi-column digital signal by digital processing to form a second multi-column digital signal; Compensation processing for the interference signal is performed on the second multi-column digital signal by digital processing to form a main data signal, and the interference signal is extracted from the second multi-column digital signal by filtering processing, A multi-system interference compensation circuit that forms an interference cancellation signal according to the magnitude of the extracted interference signal and removes the interference signal from the appropriately delayed second multi-column digital signal using the interference cancellation signal thus formed. A digital receiving device characterized by comprising; 2. The digitally modulated signal in the intermediate frequency band includes an interference signal from a different polarization, and a cross-polarization interference compensation circuit that performs a compensation process for the interference signal from the different polarization by digital processing is combined with the demodulation circuit. 2. The digital receiving apparatus according to claim 1, wherein said intersymbol interference compensation circuit is provided in parallel or in series with said intersymbol interference compensation circuit between other types of interference compensation circuits.