JPH0453301A - Delay line and microwave phase shifter - Google Patents

Delay line and microwave phase shifter

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Publication number
JPH0453301A
JPH0453301A JP16121190A JP16121190A JPH0453301A JP H0453301 A JPH0453301 A JP H0453301A JP 16121190 A JP16121190 A JP 16121190A JP 16121190 A JP16121190 A JP 16121190A JP H0453301 A JPH0453301 A JP H0453301A
Authority
JP
Japan
Prior art keywords
conductor
line
delay
microstrip line
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16121190A
Other languages
Japanese (ja)
Other versions
JP3076354B2 (en
Inventor
Susumu Uehashi
上橋 進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP02161211A priority Critical patent/JP3076354B2/en
Publication of JPH0453301A publication Critical patent/JPH0453301A/en
Application granted granted Critical
Publication of JP3076354B2 publication Critical patent/JP3076354B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a large delay with a small sized line by arranging striplike conductor on a strip conductor via a dielectric body. CONSTITUTION:A microstrip line is made up of a semiconductor GaAs substrate 11, a strip conductor 12 and a ground conductor 13 to form a delay line, a striplike conductor 15 is arranged opposite to the microstrip line with a dielectric body 14 inbetween periodically in a direction intersecting the microstrip line. Then a FET 18 having a gate width periodically along the strip conductor 12 is formed on an operating layer 31 on the GaAs substrate 11. The FET 18 uses the strip conductor 12 as one of a source and a drain electrode 19 and the other of a drain and a source electrode 20 is connected to the ground conductor 13 through a throughhole 22. Thus, a large delay is obtained regardless of a small sized line.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、電子走査アンテナ等に使用し、信号の位相を
制御する遅延線路及びマイロり波移相器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a delay line and a microwave phase shifter used in an electronic scanning antenna or the like to control the phase of a signal.

(従来の技術) マイクロ波信号の位相を制御する回路として、電気長が
異る二つの伝送線路を半導体素子で構成したスイッチで
切替えて、伝送線路を伝送する信号の位相差から所望の
位相量を得る、線路切替形移相器が広く用いられている
(Prior art) As a circuit for controlling the phase of a microwave signal, two transmission lines with different electrical lengths are switched using a switch made of semiconductor elements, and a desired phase amount is determined from the phase difference of the signals transmitted through the transmission lines. Line-switching phase shifters are widely used.

この線路切替形移相器の一実施例を第4図に示す。ここ
で入出力端子1a、lbには、スイッチ用半導体素子で
構成したスイッチが接続されている。このスイッチの動
作により基準側伝送線路4と、通過位相量が所望な移相
量だけ大きな遅延側伝送線路5を切替える。ここでは−
例として、直列及び並列に接続したFET2a〜2d、
3a〜3dによりスイッチを構成している。ここでFE
T2a、2d、3a、3dのゲート電極にOVを印加し
、FET2b、2c、3b、3cのゲート電極に一5V
を印加すると、二つのスイッチは基準側伝送線路4側に
信号を伝送する状態になり、遅延側伝送線路5に接続し
た経路を遮断する状態になる。従って入出力端子1aが
ら入力したマイクロ波信号は基準側伝送線路4の移相量
に相当する位相遅れで1bに出力する。1bから入力し
た場合は同様にして1aから出力する。
An embodiment of this line switching type phase shifter is shown in FIG. Here, a switch constituted by a switching semiconductor element is connected to the input/output terminals 1a and lb. The operation of this switch switches between the reference side transmission line 4 and the delay side transmission line 5 whose passing phase amount is larger by a desired phase shift amount. Here -
As an example, FETs 2a to 2d connected in series and in parallel,
3a to 3d constitute a switch. FE here
Apply OV to the gate electrodes of T2a, 2d, 3a, and 3d, and apply -5V to the gate electrodes of FET2b, 2c, 3b, and 3c.
When this is applied, the two switches enter a state in which signals are transmitted to the reference side transmission line 4 side, and a state in which the path connected to the delay side transmission line 5 is cut off. Therefore, the microwave signal inputted through the input/output terminal 1a is outputted to 1b with a phase delay corresponding to the amount of phase shift of the reference side transmission line 4. If the input is from 1b, it is output from 1a in the same way.

また、各FETのゲート電極に上記と逆の関係になるよ
うにバイアス電圧を印加すると、入力したマイクロ波信
号は遅延側伝送線路5の移相量に相当する位相遅れて出
力する。従って、FET2a〜2d、3a〜3dのゲー
トバイアス電圧を上記のように切換えることによって、
基準側伝送線路4と遅延側伝送線路5の位相差に相当す
る移相量が得られる。この移相量は第5図に示すように
、周波数に対して線形で変化する。従って、この移相器
では広い周波数帯域にわたり、遅延時間が一定な、等遅
延形移1n器となる。
Further, when a bias voltage is applied to the gate electrode of each FET so as to have a relationship opposite to the above, the input microwave signal is output with a phase delay corresponding to the phase shift amount of the delay side transmission line 5. Therefore, by switching the gate bias voltages of FETs 2a to 2d and 3a to 3d as described above,
A phase shift amount corresponding to the phase difference between the reference side transmission line 4 and the delay side transmission line 5 is obtained. As shown in FIG. 5, this amount of phase shift varies linearly with frequency. Therefore, this phase shifter becomes an equal delay type shifter in which the delay time is constant over a wide frequency band.

しかし、この線路切替形移相器で180°以上の大きな
移相量を得る場合には、次のような欠点がある。
However, when obtaining a large phase shift amount of 180° or more with this line switching type phase shifter, there are the following drawbacks.

■遅延側伝送線路が長くなり、移相器の形状が大きくな
る。
■The delay side transmission line becomes longer and the shape of the phase shifter becomes larger.

■信号が基準側伝送線路4を通過する状態において、遅
延側伝送線路5の長さが1/2波長になる周波数で共振
が生し、通過損失の劣化や通過位相の直線性の劣化が生
じる。
■When a signal passes through the reference transmission line 4, resonance occurs at a frequency where the length of the delay transmission line 5 becomes 1/2 wavelength, resulting in deterioration of the transmission loss and deterioration of the linearity of the transmission phase. .

(発明が解決しようとする課題) 以上述べたように従来の線路切替形マイクロ波移相器で
は、大きな移相量を得ようとすると、遅延側伝送線路の
形状が大きくなることや、周波数特性に共振が発生する
などの欠点がある。
(Problems to be Solved by the Invention) As described above, in conventional line-switching microwave phase shifters, when trying to obtain a large amount of phase shift, the shape of the delay-side transmission line becomes large, and the frequency characteristics It has disadvantages such as resonance.

そこで本発明は、上記の欠点を除去すべくなされたもの
で、小形で大きな遅延量を得ることができる遅延線路と
、この遅延線路を用いた線路切替形のマイクロ波移相器
とを提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks, and provides a delay line capable of obtaining a large amount of delay with a small size, and a line switching type microwave phase shifter using this delay line. The purpose is to

[発明の構成] (課題を解決するための手段) 上記目的を達成するために、本発明では、半絶縁性Ga
As基板上にマイクロストリップ線路を形成して、遅延
線路を構成する。このマイクロストリップ線路導体に誘
電体層を挾んで対向し、かつ前記マイクロストリップ線
路導体を横切る方向に周期的に短冊状導体を配置する。
[Structure of the invention] (Means for solving the problem) In order to achieve the above object, the present invention uses a semi-insulating Ga
A microstrip line is formed on an As substrate to constitute a delay line. Strip-shaped conductors are arranged opposite to this microstrip line conductor with a dielectric layer interposed therebetween and periodically in a direction crossing the microstrip line conductor.

この短冊状導体は連結導体で連結され、スルーホールで
接地導体に接続される。そして、ストリップ導体に沿っ
て周期的にある長さのゲート幅を持っFETを前記半絶
縁性GaAs基板上の動作層に形成する。
The strip-shaped conductors are connected by a connecting conductor and connected to a ground conductor by a through hole. Then, FETs having a gate width of a certain length are periodically formed along the strip conductor in the active layer on the semi-insulating GaAs substrate.

このFETは、上記のストリップ導体をソース又はトレ
イン電極の一方としており、ドレイン又はソース電極の
他方はスルーホールにより接地導体に接続されている。
In this FET, the strip conductor is used as either a source or a train electrode, and the other drain or source electrode is connected to a ground conductor through a through hole.

この構造により構成した遅延側伝送線路を、入出力側に
設けたスイッチで切替えることによりマイクロ波移相器
とする。
A microwave phase shifter is formed by switching the delay-side transmission line configured with this structure with a switch provided on the input/output side.

(作用) 本発明の線路切替形マイクロ波移相器では、スイッチに
より遅延側伝送線路を通過状態にした時に、遅延側伝送
線路のストリップ導体に接続したFETのゲーI・電極
に、−5v程度の負電圧を印加する。この状態では、ス
トリップ導体の上方に短冊状導体のある区間は、短冊状
導体とストリップ導体間の容量のため低インピーダンス
の区間となる。また、ストリップ導体の上方に短冊状導
体のない区間は、短冊状導体の容量がないため、マイク
ロストリップ線路だけの高インピーダンス区間となる。
(Function) In the line switching type microwave phase shifter of the present invention, when the delay side transmission line is put into the passing state by the switch, about -5V is applied to the gate I electrode of the FET connected to the strip conductor of the delay side transmission line. Apply a negative voltage of In this state, the section where the strip conductor is above the strip conductor becomes a section of low impedance due to the capacitance between the strip conductor and the strip conductor. In addition, a section where there is no strip-shaped conductor above the strip conductor becomes a high-impedance section of only the microstrip line because the strip-shaped conductor has no capacity.

そして、この低インピーダンス区間と高インピーダンス
区間の境界は、OFF状態のFETによりストリップ導
体が接地導体に接続されている。
At the boundary between the low impedance section and the high impedance section, the strip conductor is connected to the ground conductor by an OFF-state FET.

従って、遅延側伝送線路は低インピーダンスと高インピ
ーダンスとの周期構造を持つ伝送線路となり、大きな遅
延量(通過位相量)を得ることができる。
Therefore, the delay-side transmission line becomes a transmission line with a periodic structure of low impedance and high impedance, and a large amount of delay (passing phase amount) can be obtained.

また、この遅延線路を用いて構成した線路切替形移相器
において、スイッチにより遅延側伝送線路が遮断状態に
なるときには、前記FETのゲト電極をO■にする。こ
の状態では、FETは微小抵抗とみなすことができ、遅
延側伝送線路は短い間隔で小抵抗により、接地されるた
め共振は発生しない。
Further, in the line switching type phase shifter constructed using this delay line, when the delay side transmission line is cut off by the switch, the gate electrode of the FET is set to O■. In this state, the FET can be regarded as a minute resistance, and the delay-side transmission line is grounded through a small resistance at short intervals, so resonance does not occur.

(実施例) 以下、本発明のマイクロ波移相器の一実施例を第1図に
示す。ここで第4図の従来例と同じ構成要素には共通の
番号をつけである。本発明に係る遅延側伝送線路10の
詳細図を第2図に示す。
(Embodiment) An embodiment of the microwave phase shifter of the present invention is shown in FIG. 1 below. Here, the same components as in the conventional example shown in FIG. 4 are given common numbers. A detailed diagram of the delay-side transmission line 10 according to the present invention is shown in FIG.

芽2図において半絶縁性GaAs基板11.ストリップ
導体12.接地導体13によりマイクロスしリプ線路を
構成している。動作層21はストリップ導体の12の両
側に沿って形成し、ストリップ導体12の下部には両側
端かられずかに入り込んでいる。
In Figure 2, semi-insulating GaAs substrate 11. Strip conductor 12. The ground conductor 13 constitutes a microslip line. The active layer 21 is formed along both sides of the strip conductor 12, and slightly enters the lower part of the strip conductor 12 from both ends.

このストリップ導体12の上には、SiO2などで形成
した誘電体14が覆っている。さらに誘電体14の上に
は、電磁波の伝播方向に周期的に配列した短冊状導体1
5が配置され、短冊状導体相互は連結導体16により接
続され、スルーホル17により゛1′絶縁性GaAs基
板下部の接地導体13に接続されている。F E T 
1.8は第2図(b)のB部拡大図に示すようにソース
電極又はドレイン電極の一方例えばソース電極19がス
トリップ導体12に接続され、ソース電極他又はドレイ
ン電極の他方例えばドレイン電極20はスルホール22
により短冊状導体15に接続されている。遅延側伝送線
路はこの構造を多数個連続している。
This strip conductor 12 is covered with a dielectric 14 made of SiO2 or the like. Further, on the dielectric material 14, strip-shaped conductors 1 are arranged periodically in the propagation direction of electromagnetic waves.
5 are arranged, and the strip-shaped conductors are connected to each other by a connecting conductor 16, and are connected to a ground conductor 13 at the bottom of the insulating GaAs substrate 1' by a through hole 17. FET
1.8, as shown in the enlarged view of part B in FIG. 2(b), one of the source electrode or the drain electrode, for example, the source electrode 19, is connected to the strip conductor 12, and the other source electrode or the other drain electrode, for example, the drain electrode 20, is connected to the strip conductor 12. is through hole 22
It is connected to the strip-shaped conductor 15 by. The delay-side transmission line has a large number of consecutive structures.

この構造の等価回路を第3図(a)示す。ここでストリ
ップ導体の上方に短冊状導体15がない区間1aは、高
い特性インピーダンスZa、位相定数βaの伝送線路で
示すことができる。一方、ストリップ導体12の上方に
短冊状導体15がある区間1bは短冊状導体とストリッ
プ導体との容量があるため、低い特性インピーダンスZ
b1位相定数βbの伝送線路で表すことができる。また
、高い特性インピーダンスの区間と低い特性インピーダ
ンスの区間の境界ではFET18により接地されている
An equivalent circuit of this structure is shown in FIG. 3(a). Here, the section 1a where there is no strip conductor 15 above the strip conductor can be represented by a transmission line having a high characteristic impedance Za and a phase constant βa. On the other hand, in the section 1b where the strip conductor 15 is located above the strip conductor 12, there is a capacitance between the strip conductor and the strip conductor, so the characteristic impedance Z is low.
b1 It can be represented by a transmission line with a phase constant βb. Further, the boundary between the high characteristic impedance section and the low characteristic impedance section is grounded by the FET 18.

従って、FET1gのゲート電極21に一5V程度の負
電圧を印加してFET18をOFFにした状態では第3
図(b)の等価回路で示すことができる。ここでFET
のOFF時の容量C81,は小さく、無視できるのでス
トリップ導体の上方に短冊状導体15のない区間である
高い特性インピーダンス区間と、ストリップ導体の上方
に短冊状導体15のある区間である低い特性インピーダ
ンス区間とか周期構造をなしている。
Therefore, when a negative voltage of about -5 V is applied to the gate electrode 21 of FET 1g and FET 18 is turned off, the third
This can be shown by the equivalent circuit shown in Figure (b). Here FET
Since the capacitance C81 when OFF is small and can be ignored, there is a high characteristic impedance section where there is no strip conductor 15 above the strip conductor, and a low characteristic impedance section where the strip conductor 15 is above the strip conductor. It has an interval or periodic structure.

このような周期構造は一般によく知られているように遅
波回路となり、この周期構造を有する線路の遅波率σは
Floquetの定理を用いて、次式で与えられる。
As is generally well known, such a periodic structure becomes a slow wave circuit, and the slow wave factor σ of a line having this periodic structure is given by the following equation using Floquet's theorem.

σ2− (β/β0)2−[(βala−βbib)/
/3 o 1 ] 2+ (f玉+1/−rK) 2β
ala βblb/(βOl)2 ここでβ〇−自由空間の位相定数 β −周期構造伝送線路の位相定数 に−Za/Zb、    1−1a+1b上式において
、βala−βblb、Za−200Ω、Zb−20Ω
とすると、 a2−10X  (βa/βo)X  (Ia  Φ 
lb)  2/(la+Ib)2となり、通常のマイク
ロストリップ線路の3倍近い遅波率が得られる。
σ2- (β/β0)2-[(βala-βbib)/
/3 o 1] 2+ (f ball +1/-rK) 2β
ala βblb/(βOl)2 Here, β〇 - phase constant of free space β - phase constant of periodic structure transmission line -Za/Zb, 1-1a+1b In the above equation, βala-βblb, Za-200Ω, Zb-20Ω
Then, a2-10X (βa/βo)X (Ia Φ
lb)2/(la+Ib)2, and a slow wave factor nearly three times that of a normal microstrip line can be obtained.

従って、第1図のスイッチを構成するFET2a〜2d
、3a〜3dのゲートバイアス電圧を、遅延側伝送線路
10か通過状態になるよううに設定し、遅延側伝送線路
10に接続されたFET18のゲートバイアスを負電圧
にバイアスすると、大きな通過位相量を得ることができ
る。
Therefore, FETs 2a to 2d constituting the switch in FIG.
, 3a to 3d are set so that the delay-side transmission line 10 is in a passing state, and the gate bias of the FET 18 connected to the delay-side transmission line 10 is biased to a negative voltage. Obtainable.

また、第1図の切替スイッチを構成するFET2a〜2
d、3a〜3dのゲートバイアス電圧を遅延側伝送線路
10が遮断状態になるように設定し、遅延側伝送線路1
0に接続したFET18のゲートバイアス電圧をOvに
すると、F E T ]、 8は微小抵抗R8Nとみな
すことができる。これは第3図(C)の等価回路で表わ
すことできる。この状態では、遅延側伝送線路10は短
い間隔で、微小抵抗RONにより接地されるため、共振
することはない。
In addition, FET2a to 2 constituting the changeover switch in FIG.
d, the gate bias voltages of 3a to 3d are set so that the delay side transmission line 10 is cut off, and the delay side transmission line 1
When the gate bias voltage of the FET 18 connected to 0 is set to Ov, F ET ], 8 can be regarded as a minute resistance R8N. This can be expressed by the equivalent circuit shown in FIG. 3(C). In this state, the delay-side transmission line 10 is grounded by the minute resistance RON at short intervals, and therefore does not resonate.

本発明の特徴は、スI・リップ導体上に誘電体を介して
短冊状導体を配置しているため、ストリップ導体と短冊
状導体間のキャパシタンスが高く、このため、この部分
のインピーダンスzbが低くなり、K=Za/Zbを大
にすることができる。
The feature of the present invention is that the strip-shaped conductor is placed on the slip I/slip conductor via the dielectric, so the capacitance between the strip conductor and the strip-shaped conductor is high, and therefore the impedance zb of this part is low. Therefore, K=Za/Zb can be increased.

これにより小面積で高い遅波率のσを得ることができる
。また、FETの製作が容易な点である。
This makes it possible to obtain a high slow wave rate σ with a small area. Another advantage is that the FET is easy to manufacture.

本発明で使用するFETはゲート幅が比較的小さく、単
純な直線状ゲートでよいため、製作容品である。
The FET used in the present invention has a relatively small gate width and requires only a simple straight gate, so it is easy to manufacture.

本実施例ではストリップ導体の中心直下には動作層を設
けず、ストリップ導体と対向するソース又はトレイン電
極の下までの範囲にたけけ動作層を設けた。しかし動作
層の範囲はこれに限られるものではなく、半絶縁性半導
体基板の一方の面金域に設けてもよい。
In this embodiment, the active layer was not provided directly under the center of the strip conductor, but the active layer was provided in the range below the source or train electrode facing the strip conductor. However, the range of the active layer is not limited to this, and it may be provided on one metal surface area of the semi-insulating semiconductor substrate.

また、本実施例ではストリップ導体の側面の両側に沿っ
てF E T 18を形成したが、両側ではなく、片側
たけFETを形成してもよい。さらに片側ずつ交互に設
けてもよい。本実施例では隣接する短冊状導体15相互
の間隔をla、短冊状導体15の幅をIbとした例で説
明したが、これらの寸法は一定値に限られるものではな
い。また、短冊状導体15相互を連結する連結導体は、
本実施例では両側としたが、片側でもよい。
Further, in this embodiment, the FETs 18 are formed along both sides of the strip conductor, but the FETs may be formed only on one side instead of on both sides. Furthermore, they may be provided alternately on each side. In this embodiment, an example has been described in which the distance between adjacent strip-shaped conductors 15 is la and the width of the strip-shaped conductors 15 is Ib, but these dimensions are not limited to fixed values. In addition, the connecting conductor that connects the strip-shaped conductors 15 is
In this embodiment, both sides are used, but one side may be used.

[発明の効果] 本発明によれば、小さな寸法で大きな移相量が得られる
遅延線路と、大きな移相量が得られ、共振が発生しない
線路切替形マイクロ波移相器を実現できる。
[Effects of the Invention] According to the present invention, it is possible to realize a delay line that can obtain a large amount of phase shift with small dimensions, and a line switching type microwave phase shifter that can obtain a large amount of phase shift and does not generate resonance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路構成図第2図は本
発明の一実施例の遅延側伝送線路の構造を示す平面図及
び断面図、第3図は本発明の遅延側伝送回路の等価回路
図、第4図は従来の線路切替形移相器の回路構成図の一
例、第5図は従来の線路切替形移相器の移相量の周波数
特性図である。 1に半絶縁性GaAs基板 12ニストリップ導体  13:接地導体14:誘電体
   15:短冊状導体 16:連結導体  17:スルーホール18:FET 
   1.9:ソース又はドレイン20ニドレイン又は
ソース 21:ゲート   22ニスルーホール31:動作層
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. FIG. 2 is a plan view and cross-sectional view showing the structure of a delay-side transmission line according to an embodiment of the present invention. FIG. 3 is a delay-side transmission line according to an embodiment of the present invention. An equivalent circuit diagram of the circuit, FIG. 4 is an example of a circuit configuration diagram of a conventional line switching type phase shifter, and FIG. 5 is a frequency characteristic diagram of the amount of phase shift of the conventional line switching type phase shifter. 1: semi-insulating GaAs substrate 12 strip conductor 13: ground conductor 14: dielectric 15: strip-shaped conductor 16: connection conductor 17: through hole 18: FET
1.9: Source or drain 20 Drain or source 21: Gate 22 Ni through hole 31: Operating layer

Claims (2)

【特許請求の範囲】[Claims] (1)半絶縁性半導体基板の一方の面に形成されたマイ
クロストリップ線路導体と、前記半絶縁性半導体基板の
他方の面に形成された接地導体と、前記マイクロストリ
ップ線路導体を含む、半絶縁性半導体基板面を覆う誘電
体層と、前記マイクロストリップ線路導体に誘電体層を
挾んで対向し、かつ前記マイクロストリップ線路導体を
横切る方向に周期的に配置された短冊状導体と、前記短
冊状導体を連結する連絡導体と、前記連結導体を接地す
る手段と、前記マイクロストリップ線路導体に沿って前
記半絶縁性半導体基板の所定領域に形成された動作層と
、この動作層内で前記マイクロストリップ線路導体に沿
って所定間隔で形成された複数個のゲートと、前記動作
層内で、前記ゲートを挾んで前記マイクロストリップ線
路導体の反対側に形成され、かつ、前記接地導体に接続
された複数の電極を具備し、この複数の電極をソース又
はドレインの一方とし、前記マイクロストリップ線路導
体をソース又はドレインの他方とし、前記ゲートと共に
電界効果トランジスタの機能を持たせたことを特徴とす
る遅延線路。
(1) A semi-insulating device including a microstrip line conductor formed on one surface of a semi-insulating semiconductor substrate, a ground conductor formed on the other surface of the semi-insulating semiconductor substrate, and the microstrip line conductor. a dielectric layer covering a surface of the semiconductor substrate; a strip-shaped conductor facing the microstrip line conductor with the dielectric layer sandwiched therebetween and periodically arranged in a direction transverse to the microstrip line conductor; a connecting conductor for connecting the conductors; a means for grounding the connecting conductor; an active layer formed in a predetermined area of the semi-insulating semiconductor substrate along the microstrip line conductor; a plurality of gates formed at predetermined intervals along the line conductor; and a plurality of gates formed in the active layer on the opposite side of the microstrip line conductor with the gates sandwiched therebetween, and connected to the ground conductor. A delay line characterized in that the plurality of electrodes serve as either a source or a drain, the microstrip line conductor serves as the other of the source or drain, and the gate functions as a field effect transistor. .
(2)請求項第(1)項の遅延線路と、前記遅延線路と
マイクロ波半導体素子で構成された切替スイッチを介し
て並列に接続された基準側伝送線路とより成り、前記遅
延線路と前記基準側伝送線路とを切替えることを特徴と
するマイクロ波移相器。
(2) The delay line according to claim (1), and a reference side transmission line connected in parallel to the delay line via a changeover switch constituted by a microwave semiconductor element; A microwave phase shifter characterized by switching between a reference side transmission line and a reference side transmission line.
JP02161211A 1990-06-21 1990-06-21 Delay line and microwave phase shifter Expired - Fee Related JP3076354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02161211A JP3076354B2 (en) 1990-06-21 1990-06-21 Delay line and microwave phase shifter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02161211A JP3076354B2 (en) 1990-06-21 1990-06-21 Delay line and microwave phase shifter

Publications (2)

Publication Number Publication Date
JPH0453301A true JPH0453301A (en) 1992-02-20
JP3076354B2 JP3076354B2 (en) 2000-08-14

Family

ID=15730720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02161211A Expired - Fee Related JP3076354B2 (en) 1990-06-21 1990-06-21 Delay line and microwave phase shifter

Country Status (1)

Country Link
JP (1) JP3076354B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017103646A (en) * 2015-12-02 2017-06-08 日本電信電話株式会社 Optical transmitter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017103646A (en) * 2015-12-02 2017-06-08 日本電信電話株式会社 Optical transmitter

Also Published As

Publication number Publication date
JP3076354B2 (en) 2000-08-14

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