JPH0452578A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To achieve an efficient acceleration test by inputting a control signal and generating a signal which is equivalent to a signal which is input externally in normal operation using a test circuit. CONSTITUTION:In acceleration test, control signal is input to a terminal Ta for activating a timing control part 16A. Also, a clock is input to the terminal Ta. Then, a binary counter 18A counts it. On the other hand, the control part 16A sends switching signal to a multiplexer 14 and output of the counter 18A is applied to an internal bus. Further, the control part 16A generates gate signal in synchronization with the clock to enable signal on this internal bus to be taken into a register 12A and it is input to a G terminal of the register 12A. By processing in this manner, a value which is stored in the register is changed, thus enabling an acceleration test to be performed under conditions which are similar to normal operation state.

Description

[Detailed Description of the Invention] [Summary of the Invention] When performing accelerated testing of LSIs on semiconductor integrated circuits such as microprocessors and logic ICs, effective testing is possible by changing the internal state more frequently. The purpose of providing a semiconductor integrated circuit is to include a test circuit in a semiconductor substrate that outputs a signal corresponding to a signal input from the outside during normal operation of the semiconductor integrated circuit, and any of the external input signal and the test circuit output signal. The configuration includes a multiplexer that selects and outputs one of the following, and a control circuit that instructs the startup of the test circuit and switching of the multiplexer during testing.

[Industrial application field]

The present invention relates to semiconductor integrated circuits such as microprocessors and logic ICs.

With the development of semiconductor manufacturing technology, elements are becoming increasingly finer, and migration is becoming more likely to occur. Therefore, in order to avoid deterioration in reliability due to element miniaturization, it is necessary to perform appropriate tests.

Among these tests, there are tests in which LSIs are operated at high temperatures in order to accelerate latent initial defects into defects, expose them, and remove them.There is a need for methods and equipment to effectively perform this accelerated test. It is.

[Conventional technology]

Conventionally, accelerated testing involves applying a constant voltage to the terminals of an LSI.
Alternatively, this can be done by applying a pulse with a constant frequency.

[Problem to be solved by the invention]

However, with this method, the internal state of the LSI is difficult to change, voltage is only applied to a part of the circuit, or only a small part of the circuit is operating, making it difficult to perform an effective accelerated test. The problem is that this is not done.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can be tested effectively by changing the internal state more frequently when performing an accelerated test of an LSI.

[Means to solve the problem]

As shown in FIG. 1, according to the present invention, an accelerated test circuit is built into a semiconductor substrate IO that constitutes a semiconductor integrated circuit.

This includes a test circuit 18 that generates test signals, a multiplexer 14 that switches between input signals (commands and data) during normal operation of LSI input terminals -1 to T7 and test signals from the test circuit 18, and a control circuit 16. Be prepared.

During the acceleration test, a control signal for instructing this is inputted to the control circuit 16 from the acceleration test selection terminal.

[Effect]

Accelerated tests are usually carried out by attaching a large number of LSIs to a board, connecting power wiring, but not signal wiring, and placing the board in a high temperature chamber for a predetermined period of time. Unless a signal is input, each element of the LSI will not operate, and voltage will only be applied to a portion of the circuit, such as the power supply side. If voltage is only applied to a portion of the circuit, it is not possible to fully achieve the purpose of accelerated testing, which is to actively destroy any weak parts in the circuit and eliminate defective products.

In the present invention, in this accelerated test, the power supply voltage is applied and the terminal T
, input the control signal from . The test circuit 18 then operates, and the test circuit 18 generates a signal corresponding to a signal input from the outside during operation of the LSI. The multiplexer 14 replaces the signal outputted by the test circuit 18 with the signal inputted from the terminals T, -Ti during normal operation, and connects the signal to the internal circuit 12.
etc. by manpower. Of course, the test circuit 18 cannot output exactly the same signal as the external signal input to the terminal T fi during normal operation, but a signal similar to the external signal can be generated, and this In response, the LSI internal circuit performs a certain kind of operation, although it is functionally meaningless, and can avoid being in a dormant state.

Since the present invention performs the acceleration test under such conditions, it is more effective in accelerating and removing defects.

〔Example〕

FIG. 2 shows an embodiment of the present invention. In this example, the LSI is a 4-bit logic circuit with an input data terminal T.

There are four T4 lines and four internal bus signal lines.

The test circuit is a 4-bit binary counter, and the multiplexer 14 connects the 4-bit output of the counter to terminals T, ~T.
, and connect it to the 4-bit internal bus. In addition, the control circuit is the timing control section 16A in this example, and the internal circuit is the 4-bit register 12A.
It is A.

During the acceleration test, a control signal is input to the terminal T to activate the timing control section 16A, and a clock is input to the terminal T. The counter 18A counts this, and the timing controller 16A sends a switching signal to the multiplexer 14 to apply the output of the counter 18A to the internal bus. Furthermore, in order to cause the register 12A to take in the signal on the internal bus, a gate signal is generated in synchronization with the clock and is input to the G terminal of the register 12A. Such processing changes the value stored in the register, thus changing the LS
Accelerated tests can be performed under conditions close to the normal operating conditions of I.

FIG. 3 shows a more detailed embodiment of the present invention. In this example, the multiplexer 14 is composed of ant gates G, , C, 2 and an OR gate G3, and the gates c, , c2 are connected to the control signal TE.
It can be switched with ST. Internal bus BUS and data terminal T,
Buffers B, , B are provided between T7 and T7.

is inserted, and the buffer B1 is turned off (inactive) during writing and testing by the read/write control signal R/W.

Figure 4 shows a signal time chart. As shown in the figure, in this example, three clocks constitute one bus cycle, and reading/writing is switched in units of one bus cycle. counter 18
A counts the clock CLK and sets the count value to 1.2, 3.
I'm going to change it to...

When the control signal TEST is at H level, GI is off and G2 is on, and the output of the counter 18A is input to the data terminal of the latch DFF. And R/W is H, data strobe D
When S is H, the output of the Nant gate G4 becomes L, and the DFF takes in data at this fall. Therefore, the counter outputs taken into the DFF are 3, 9, 12, etc. in this example.・・・・・・
It is...

During normal operation, the control signal TEST is at L level, gate C is open, and gate G2 is closed. Therefore, when writing, terminal T1
~T7 data is 82. Latch DFF via G,,G3
and is taken into the latch by the strobe DS.

BUS IN in FIG. 4 indicates this input data. At the time of reading, R/W=is set, the buffer B1 becomes valid, and the internal lotus data is output to the terminals T1 to T7. BUS OUT in FIG. 4 indicates this data output.

If the signals (commands and data) input from terminals T and -T during normal operation are 8 bits, 16 bits, etc., the test circuit (counter) will also be 8 bits, 16 bits, etc.
......, but this means 4 bits twice, four times,
. . . The test circuit can be reduced to a small number of bits by a method such as repeated use.

The clock for operating the counter may be output from a built-in oscillator instead of being input externally.

〔Effect of the invention〕

As explained above, according to the present invention, during an accelerated test of an LSI, it is possible to bring the LSI into an operating state close to that in actual use under high temperatures, and to enable an effective accelerated test. This greatly contributes to improving the credibility of

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention. Fig. 2 is a block diagram showing an embodiment of the invention. Fig. 3 is a block diagram showing a detailed embodiment of the invention. Fig. 4 is for explaining the operation of Fig. 3. This is a time chart. In FIG. 1, 10 is a semiconductor substrate, 12 is an internal circuit, 14 is a multiplexer, 16 is a control circuit, 18 is a test circuit, T,
-T,,T, are terminals. Figure 1: Principle diagram of the present invention

Claims (1)

[Claims] 1. A test circuit (18) within the semiconductor substrate (10) that outputs a signal corresponding to a signal input from the outside during normal operation of the semiconductor integrated circuit, and the external input signal and the test circuit output. A semiconductor integrated circuit comprising: a multiplexer (14) for selecting and outputting one of the signals; and a control circuit (16) for instructing activation of a test circuit and switching of the multiplexer during testing. 2. The semiconductor integrated circuit according to claim 1, wherein the test circuit is a counter.