JPH0452224U - - Google Patents
Info
- Publication number
- JPH0452224U JPH0452224U JP9375890U JP9375890U JPH0452224U JP H0452224 U JPH0452224 U JP H0452224U JP 9375890 U JP9375890 U JP 9375890U JP 9375890 U JP9375890 U JP 9375890U JP H0452224 U JPH0452224 U JP H0452224U
- Authority
- JP
- Japan
- Prior art keywords
- reset signal
- bus
- signal line
- slave
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の一実施例の構成図、第２図は
第１図の要部構成図、第３図は第１図のシステム
の動作説明図、第４図はスイツチとリセツト信号
線の接続を概念的に示した図、第５図は従来にお
けるシステムのリセツト回路の構成例を示した図
である。
Ａ……マスタ側、Ｂ１〜Ｂｎ……マスタ側、Ｍ
，Ｓ……バスリピータカード、２……マスタ側バ
ス、４……スレーブ側バス、５……接続ケーブル
、８……リセツト信号線、９……スイツチ回路、
１０……電源ライン。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of the main parts of Fig. 1, Fig. 3 is an explanatory diagram of the operation of the system in Fig. 1, and Fig. 4 is a switch and reset signal line. FIG. 5 is a diagram conceptually illustrating the connections of , and FIG. 5 is a diagram illustrating an example of the configuration of a reset circuit in a conventional system. A... Master side, B 1 ~ Bn... Master side, M
, S... Bus repeater card, 2... Master side bus, 4... Slave side bus, 5... Connection cable, 8... Reset signal line, 9... Switch circuit,
10...Power line.
Claims (1)
したマスタ側に、バスリピータカードを介して、
スレーブネストのカード間をスレーブ側バスで接
続したスレーブ側を任意の数だけ追加接続し、前
記マスタ側バスのスロツト不足を補うシステムに
おいて、 各スレーブ側に設けられたバスリピータカード
に接続されていて、リセツト信号を伝送するリセ
ツト信号線と、 各スレーブ側ごとに設けられていて、対応する
バスリピータカードに電源電圧が供給されていな
い場合は、スイツチを閉じて前記リセツト信号線
をローレベル電位点に接続するスイツチ回路を具
備し、 全てのスレーブ側に電源電圧が供給されたとこ
ろで、全てのスイツチ回路はリセツト信号線をロ
ーレベル電位点から切離してリセツト信号をハイ
レベルに立上げることを特徴とするシステムのリ
セツト回路。[Scope of claim for utility model registration] On the master side, which connects the cards of the master nest with the master side bus, via a bus repeater card,
In a system in which a slave nest card is connected to a slave side bus and an arbitrary number of slaves are additionally connected to compensate for the lack of slots on the master side bus, each slave side is connected to a bus repeater card provided on each slave side. , a reset signal line for transmitting the reset signal, and a reset signal line for each slave side.If the power supply voltage is not supplied to the corresponding bus repeater card, close the switch and connect the reset signal line to the low level potential point. When the power supply voltage is supplied to all slaves, all the switch circuits disconnect the reset signal line from the low level potential point and raise the reset signal to high level. system reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9375890U JPH0452224U (en) | 1990-09-06 | 1990-09-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9375890U JPH0452224U (en) | 1990-09-06 | 1990-09-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0452224U true JPH0452224U (en) | 1992-05-01 |
Family
ID=31831208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9375890U Pending JPH0452224U (en) | 1990-09-06 | 1990-09-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0452224U (en) |
-
1990
- 1990-09-06 JP JP9375890U patent/JPH0452224U/ja active Pending
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