JPH0451612A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce the glitch of output without using an integrator and the like and to improve response speed and conversion precision by adding a pulse current (or voltage) generated by means of a pulse signal generator to the digital input or analog output of a D/A converter. CONSTITUTION:The pulse signal generation means 40 generating a prescribed pulse signal in synchronizing with the rise or fall of the digital input of the digital/analog(D/A) converter 30 and an addition means 50 adding the pulse signal generated by the means 40 to the output signal of the D/A converter 30 are provided. Then, glitch generated at the rise or fall of the output signal of the D/A converter 30 is cancelled. Thus, the glitch of the output of the D/A converter 30 is reduced without using the integrator for smoothing glitch is reduced and response speed and conversion precision improve.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a digital signal converter for converting a digital signal into an analog signal.
The present invention relates to an A converter, and particularly relates to a D/A converter equipped with a deglitch circuit for canceling glitches.

(Prior Art) In recent years, digital f. A D/A converter (hereinafter abbreviated as DAC) is used to convert the signal ' into an analog signal C3. Although there are various DAC methods, the ladder net type is the mainstream as a high-precision DAC. For example, in a ladder net type N-bit DAC, N bits from the 1st bit [1 to 2 N bits each] are input to the N-bit digital input.
It is attached to the current with a weight of -1 power, and outputs a gummy flow proportional to the digital input.

By the way, DACs have a problem with noise (glitches) due to data propagation variations. The main cause of glitches in ladder net type DACs is that the digital inputs are weighted by 2 to the N-1 power. glitches due to differences in current source characteristics (characteristics of rise, fall, delay, transient waveform, etc. of pulse current) and glitches due to differences in current source characteristics (characteristics of pulse current rise, fall, delay, transient waveform, etc.). This occurs due to leakage.

Conventionally, in order to reduce this glitch, it is passed through an integrator,
Glitches were smoothed out. However, by passing the signal through an integrator, the high speed and high accuracy of the DAC is lost. There is also a method of removing glitches using sample and hold, but in this case glitches in the sample and hold itself and fluctuations in the pedestal e level pose problems.

(Problems to be Solved by the Invention) Conventionally, in ladder net type D/Ai converters, the dynamic characteristics between digital inputs do not match, and the weighting corresponding to the digital inputs is difficult due to the characteristics of the current source. There is a problem that glitches occur due to differences in the numbers. Also, if you use an integrator to reduce this glitch,
There was a problem that the high speed and high precision of the D/A converter were lost.

The present invention has been made in consideration of the above circumstances, and its purpose is to reduce glitches in the output of a D/A converter without using an integrator or the like to smooth out glitches. It is an object of the present invention to provide a highly reliable D/A converter that is capable of providing high response speed and conversion accuracy.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to add a pulse current (or voltage) generated by a pulse signal generator to the digital input or analog output of a D/A converter. The purpose is to cancel out the glitch caused by the above-mentioned item (■).

That is, the present invention connects the 1st bit to the Nth bit of an N-bit digital input to a current source that outputs a current corresponding to a weight of 2 to the N-1 power, and outputs an analog current proportional to the digital input. D with an N-bit D/A converter
/A3 converter includes a pulse signal generating means for generating a predetermined pulse signal in synchronization with rising and falling edges of a digital input of a D/A converter, and a pulse signal generated by the means for converting the pulse signal into the D/A converter. The D/A converter output signal is added to the output signal of the D/A converter to cancel glitches that occur at the rise and fall of the output signal of the D/A converter.

Furthermore, the present invention connects the 1st bit to the Nth bit of an N-bit digital input to a current source that outputs a current corresponding to a weight of 2 to the N-1 power, and outputs an analog signal proportional to the digital input. D with an N-bit D/A converter
/A☆ Conversion device replacement - Pulse signal generation means that generates a predetermined pulse signal in synchronization with the rise and fall of the digital input of the D/A converter, and the pulse signal generated by this means are converted into a D/A converter. An addition means for adding to the digital input of the A converter is provided to cancel glitches that occur at the rise and fall of the output current of the D/A converter.

(Function) According to the present invention, from the information of the input data of the D/A converter, the pulse polarity and pulse width corresponding to the glitch occurring at the rising edge and falling edge of the output signal of the D/A converter,
Generate a pulse signal with an amplitude by a pulse signal generator,
By applying this pulse to the analog output or digital input of the D/A converter, glitches can be canceled. Therefore, a high-speed and highly accurate D/^ conversion output can be obtained. That is, individual weighting of the D/A converters makes it possible to eliminate glitches by making the rise and fall characteristics of the current source ideal by the pulse signal generator.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a block diagram showing a schematic configuration of a D/^ conversion device according to a first embodiment of the present invention.

In this embodiment, a 3-bit D/A converter is used to simplify the explanation, but the number of digital input bits is of course not limited to this.

In the figure, 10 is a delay circuit that delays the ENB signal, 20 is a latch that temporarily stores digital input data, and 30 is a weighted current source 31, 32, . '33 D/A converter (DA
C), 40 is a pulse current generation circuit that generates a pulse corresponding to the current to be corrected based on input data, and 50 is D
An adder is shown that adds the AC output current and the correction current.

ENB is delayed by Ta time by the delay circuit 10 and is input to the clock input terminal of the latch 20.

The latch 20 receives input data 1 to 1 in response to the above clock.
3 is temporarily stored. The output of latch 20 is provided to DAC 30, which drives the corresponding current source 31.33.

The current sources 31 to 33 are each given a weight of 2 to the N-1 power.

The ratio between current source 32 and current source 31 is two, and the ratio between current source 33 and current source 32 is four.

When the output of the latch 2 [ ] corresponding to the first bit of data 1 is "H", the transistor inside the current source 31 is turned on and the current source 31 is activated. When the output of the latch corresponding to data 1 is "L", the transistor inside the current source 31 is turned off, making the current source 31 inactive. Current sources 32 corresponding to the second and third bits.
Similarly, for 33, active and inactive states are created. and activation of current sources 31-33.

The inactive combination controls the output current of the DAC 30.

FIG. 2 is a time chart for explaining the operation of this device. In this figure, current sources 3] to 33, the DAC output current without correction, the correction current of current sources 31 to 33, and the DAC output current without correction.
A time chart of the Th1i positive current and the DAC output current after pressure compensation is shown. Further, it is assumed that the rise and fall characteristics (slew rates) of the current sources 31 to 33 have the same slope.

At time T1 in FIG. 2, the current sources 31 to 33 are active (ON) and the output current of the DAC is at its maximum.

At time T2, the current source 31 is inactive (OFF), and the current source 32
．． 33 is active (ON), the output current of the DAC is current source 3.
It decreases by the magnitude of 1. Similarly, time T3 to T8
Also, the output current of the DAC monotonically decreases.

The correction current of the current source 31, the correction current of the current source 32, and the correction current of the current source 33 in FIG.
represents the error from the ideal value. The correction current of the DAC is the sum of the correction currents of the current sources 31 to 33 described above.

By adding this correction current to the DAC output current,
Obtain the corrected DAC output current. The pulse current generating circuit 40 is for generating a correction current for the DAC shown in FIG.

FIG. 3 is a block diagram showing a specific configuration of the pulse current generating circuit 40. As shown in FIG. In the figure, 41 is a free knob flop (hereinafter abbreviated as FF), 42 is an oscillator, 43 is a counter, 44 is a memory for storing correction data, 45, 46.4
7 is a rising/falling detection circuit (hereinafter abbreviated as RFH path), 49 is a correction DAC, 481 is a delay circuit,
482 is a delay control circuit, 483 is a latch, and 484 is a differential circuit.

ENB turns on the FF 41 and inputs the pulse of the oscillator 42 to the counter 43. The output of the counter 43 is connected to the 3 bits on the LSB side of the memory 44 (the outputs C1 to C3 of the counter 43 are connected to the address ADD of the memory 44, respectively).
I~^DD3), and the L address of the memory 44
Change the 3 bits on the SB side. Furthermore, R due to ENB
Data 1-3 are taken into FM paths 45-47.

FIG. 4 shows details of the RF circuits 45-47.

The data taken in by ENB is taken into FF451. FF451 data before being imported is FF4
Shift to 52. Based on the currently captured data and the previously captured data, the combination of (A, B) in Figure 5 causes the data to rise (1, 1), fall (0, 1), and remain unchanged at 0.0. or 1.0). Returning to FIG. 3, the output terminals AI, Bl, A2 . B2. A3 and B3 are connected to addresses ADD4 to ADD9 of the memory 44, respectively.

FIG. 6 shows details of the correction current from time T4 to T5 in FIG. 2. Using ENB, the RF circuits 45 and 46 in FIG. 3 detect rising edges, and the RF circuit 47 detects falling edges. At this time, addresses ADD1 to ADD3 of the memory 44 are zero, AD
D4.5 is both 1, ADD6.7 is both 1, and ADD
8 is 0. ADD9 is 1. Eight pulses of the internal clock are generated simultaneously with ENB.

In FIG. 3, the counter 43 is operated by the internal clock shown in FIG.
Supply to 3. The correction current data from time T4 to T5 in FIG. By doing so, the data of the correction current from T4 to T5 is sequentially output to the outputs D101 to D4 of the memory 44.

Here, if the rising and falling states of data 1 to 3 are different, the addresses of the memory 44 (ADD9 to 1)
The contents of the memory 44 will change, and data in a different area will be output to the outputs DIOI-4 of the memory 44.

Then, the output data of the memory 44 is temporarily stored in the latch 483 and input to the correction DAC 49.
A correction current is output from C49. FIG. 6 shows a detailed timing chart of the correction current. The delay time Td of the correction current in FIG. 6 is a time for adjusting the timing with the glitch of the DAC 30.

The delay time Td is created by the delay circuit 481 in FIG. 3 and the delay control circuit 482 whose delay time is determined by the memory outputs DI05 to DI7. The delay time of the delay circuit 481 is
It is equal to the delay time of the memory 44. The output of the delay control circuit 482 is connected to the clock input of the watch 483, and the DAC
The glitch of the current source and the timing of the correction current of the correction DAC 49 are matched, and the glitch of the DAC 30 is corrected by the DAC 49.
The glitch is canceled by the correction current.

According to this embodiment, a pulse current with controlled polarity, amplitude, delay, and pulse width is generated in synchronization with the rising and falling edges of the digital input of the DAC 30, and this pulse current is sent to the analog output of the DAC 30. By adding, glitches in the DAC 30 can be canceled out. And in this case, there is no need to use an integrator, and the DA
There is no problem that the high speed and high accuracy of C are lost. Therefore, it is possible to realize a D/A converter with excellent conversion speed and conversion accuracy, and its usefulness is enormous.

FIG. 7 is a block diagram showing a schematic configuration of a second embodiment of the present invention.

In this embodiment, instead of correcting the analog output, the digital input is corrected. That is, the pigs 1 to 3 are input to data correction circuits 61, 62, and 63, and digital data corrected by these circuits is supplied to the DAC 30.

FIG. 8 is a block diagram showing details of the data correction circuit shown in FIG. 7. The data passes through the delay circuit 71 f, :, E
It is temporarily stored in the FF 72 by NB.

Further, the RF circuit 73 detects the rising edge and trailing edge of the data, and the pulse voltage generating circuit 74 generates a correction pulse Pr at the rising edge and a correction pulse Pf at the falling edge. Then, the DC components of the correction pulses Pr and Pf are removed by a capacitor C, and added to the voltage temporarily stored in the FF 72 by a resistor network. This addition output becomes the data correction output. Supplementary iE
The amplitude adjustment of Hals Pr and Pf is done by VRI and VH2, respectively.
This is done by

FIG. 9 is a block diagram showing details of the pulse voltage generating circuit 74. The ENB causes the delay circuit 81 from the FF 84 to
A signal of "H" or "L" is input.The delay circuit 81 has outputs DL1 to DL9 for each unit delay (the larger the number, the longer the near delay time).The selectors S1 and 82 select the pulse of the rising correction pulse Pr. Determine the width and delay (must be the delay selected by selector S1 and the delay selected by selector S2). Similarly, selectors S3 and 84
The pulse width and delay of the falling correction pulse Pf are determined by
(must be the selected delay). Input A.

B is the output of the RF circuit 73 in FIG. 8, which is input to the data rising and falling correction pulse gates 82 and 83 to determine rising and falling edges. In addition, in FIG. 8, 85 indicates a differentiating circuit for resetting the FF 84.

FIG. 10 is a timing chart showing the output of each part in the data correction circuit. The broken line of the data correction output in FIG. 10 is the data waveform before correction. The data correction output is obtained by adding the outputs Pr and Pf of the pulse voltage generation circuit 74 to the data waveform. The pulse width, delay and pulse amplitude of the outputs Pr and Pf of the pulse voltage generation circuit 74 are determined by the DAC.
Set the pulse response of the current source to be optimal.

As described above, according to this embodiment, the delay 1 is externally applied so that the pulse characteristics of the current sources 31 to 33 of the DAC 30 have characteristics that do not cause glitches in response to glitches in the DAc 30.
By adding a correction pulse with controlled width, amplitude, etc.
D A C3rl glitches can be removed or reduced.

FIG. 11 is a block diagram showing a schematic configuration of a third embodiment of the present invention, FIG. 12 is a block diagram showing a specific configuration of a data control circuit, and FIG. 13 is a timing chart showing its operation.

In this embodiment, ENB is input to the delay control circuit 101, the delay circuit 81 is operated, and at the same time the data control circuit 10
2 to 104 RF circuits 73 cause data to rise,
Detect falling edge. Data 1 to 3 are sent to FF72 in data control circuits 102 to 104 via LENB (DL4).
is latched at the timing of , and the input of DAC30 (D1~
3). Rising correction outputs R1 to R3 and falling correction outputs F1 of data control circuits 102 to 104
~F3 is connected to the plus input and minus input of the operational amplifier 105 through a variable resistor (which adjusts the pulse amplitude). The output of this operational amplifier 105 is then
It is added to the output of 0.

Note that a variable resistor 122 is connected to one input of the operational amplifier 105, a variable resistor 121 is connected to the tenth input, and the output of the gate 121 is connected to these resistors 122 and 123. By inputting +5■ to the gate 121 through a resistor, the gate 121 is always kept in a zero state. Data control circuit output F1-3. R1~3 (gate output)
varies with temperature. By changing the DC zero output, the amplifier output adjusts the variable resistors 122 and 123,
Make sure the amplifier output is zero. By inputting the same input to the inputs of the amplifier in a state where data 1 to 3 do not change, changes in the amplifier output due to temperature changes are canceled out.

FIG. 12 shows the configuration of the data control circuit. The rising edge correction output R gate R111 selects from the outputs A and B of the RF circuit 73 and the delayed outputs (DLI to DL8) of the delay circuit 81 to obtain the rising edge correction output R. In addition, the 12th
In the example shown in the figure, the input of the gate R111 is DL3, and the R
DL5 was selected for the f input, DL3 was selected for the F input of gate Fl12, and Ff large input DL5 was selected. Inputs Rr, Rf, Fr, F of gate R111 and gate F112
By selecting the outputs DLI to DL8 of the delay circuit 81 as f, the phase and pulse width for the data D1 to D3 are obtained, and a pulse having the opposite polarity to the glitch generated at the output of the DAC is supplied through the operational amplifier 105. Cancel the glitch. The output of the operational amplifier is a DC component connected to a capacitor 10.
6 to prevent DC voltage from being applied to the DAC.

With such a configuration, the delay circuit 8], the data control circuits 102, 103, 104, and the operational amplifier 105 control the polarity in synchronization with the rising and falling edges of the digital input of the DAC 30.

By generating a pulsed current with controlled amplitude, delay, and pulse width and adding this pulsed current to the analog output of the DAC 30, glitches in the DAC 30 can be canceled out. Therefore, ahead! The same effects as in the 81st embodiment can be obtained.

It should be noted that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit thereof. In the first embodiment, as a pulse signal generating means, the polarity, amplitude, delay, and pulse of the pulse signal are determined so as to generate a pulse signal having substantially the same waveform as the glitch of the output signal of the D/A converter and having a different polarity. Although the width is controlled, pulse density modulation may be used instead. That is, a pulse signal having a constant amplitude, a constant minute pulse width, a pulse density and a controlled polarity may be added to the output signal of the D/A converter.

[Effects of the Invention] As detailed above, according to the present invention, by adding the pulsed current a (or voltage) generated by the pulse signal generator to the digital input or analog output of the D/A converter, , D/A converter glitches can be canceled. Therefore, it is possible to reduce glitches in the output of the D/A converter by O (0) without using an integrator or the like to smooth out glitches. Realizing the A conversion device becomes nJ capability.

[Brief explanation of drawings]

FIGS. 1 to 6 show D/D according to the first embodiment of the present invention.
Figure 1 is a block diagram showing the overall configuration, Figure 2 is a timing chart showing the output current of each part, Figure 3 is a block diagram showing the pulse current generation circuit, and Figure 4 is for explaining the A converter. The figure is a block diagram showing a data rise and fall detection circuit, Fig. 5 is a schematic diagram showing the operation of the above detection circuit, Fig. 6 is a schematic diagram showing an example of DAC current compensation tF-, and Figs. 10 is for explaining the second embodiment of the present invention, FIG. 7 is a block diagram showing the overall configuration, FIG. 8 is a block diagram showing a data correction circuit, and FIG. 9 is a block diagram showing the data correction circuit.
The figure is a block diagram showing the pulse voltage generation circuit, Figure 10 is a timing chart showing each striking force, and Figures 11 to 1.
Figure 3 is for explaining the third embodiment of the present invention.
FIG. 11 is a block diagram showing the overall configuration, FIG. 12 is a block diagram showing the data control circuit, and FIG. 13 is a timing chart showing the operation of the data correction circuit. 10...Delay circuit, 20...Latch, :O...D/A converter, (DAC), 40...Pulse current generation circuit, 50...Adder, 44...Memory , 45-47...Rise and fall detection circuit (R
F circuit), 81... Delay circuit, 1 (Jl... Delay R, IJ control circuit, 102-104... Data control circuit, 105... Operational amplifier.

Claims (6)

[Claims] (1) Connect the 1st to N bits of the N-bit digital input to a current source that outputs a current corresponding to a weight of 2 to the N-1 power, and output an analog current proportional to the digital input. A D/A converter equipped with a bit D/A converter, comprising a pulse signal generating means for generating a predetermined pulse signal in synchronization with rising and falling edges of a digital input of the D/A converter; and an addition means for adding the generated pulse signal to the output signal of the D/A converter, thereby canceling out glitches that occur at the rise and fall of the output signal of the D/A converter. D/A converter. (2) The pulse signal generating means is configured to be able to control the polarity, amplitude, delay, and pulse width of the pulse, and the D/A
2. The D/A converter according to claim 1, wherein the D/A converter generates a pulse signal having substantially the same waveform as a glitch in the output signal of the converter and having a different polarity. (3) The D/A converter according to claim 2, wherein the pulse signal generating means stores data of a pulse signal generated in synchronization with rising and falling edges of the digital input in a memory. . (4) The pulse signal generating means is composed of a plurality of units corresponding to N digital inputs, each of which outputs a pulse signal with a different polarity at the rising edge and falling edge of the digital input, and at different bits of the digital input. 3. The D/A converter according to claim 1, wherein the D/A converter outputs pulse signals of different magnitudes and generates a pulse signal by combining these signals. (5) The pulse signal generating means outputs a pulse signal in which the glitch waveform of the output signal of the D/A converter is approximated by a plurality of rectangular pulses. The D/A conversion device described. (6) Connect the 1st to N bits of the N-bit digital input to a current source that outputs a current corresponding to a weight of 2 to the N-1 power, and output an analog signal proportional to the digital input. A D/A converter equipped with a bit D/A converter, comprising a pulse signal generating means for generating a predetermined pulse signal in synchronization with rising and falling edges of a digital input of the D/A converter; and an addition means for adding the generated pulse signal to the digital input of the D/A converter, thereby canceling out glitches that occur at the rise and fall of the output current of the D/A converter. D/A converter.