JPH0451546A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPH0451546A JPH0451546A JP2160616A JP16061690A JPH0451546A JP H0451546 A JPH0451546 A JP H0451546A JP 2160616 A JP2160616 A JP 2160616A JP 16061690 A JP16061690 A JP 16061690A JP H0451546 A JPH0451546 A JP H0451546A
- Authority
- JP
- Japan
- Prior art keywords
- package
- hue
- temperature
- phenomenon
- changes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 239000003973 paint Substances 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣパッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an IC package.
第３図は従来のＩＣパッケージを示す斜視図、８４図に
ＩＣパッケージの断面図である。図において、（１）は
ＩＣチップ、（２）にピン、（３）はＩＣチップ（１）
とピン（２） 、 （２１とを接続した接続線、（４）
はＩＣパッケージ、（５）はＩＣパッケージ（４）の所
定の面に設けられた標識で、例えば製造元を示す社章や
形式記号などが、所定のインクで押印されている。FIG. 3 is a perspective view showing a conventional IC package, and FIG. 84 is a sectional view of the IC package. In the figure, (1) is an IC chip, (2) is a pin, and (3) is an IC chip (1).
Connecting wire connecting pin (2) and (21), (4)
is an IC package, and (5) is a mark provided on a predetermined surface of the IC package (4), for example, a company emblem indicating the manufacturer, a type code, etc. are stamped with a predetermined ink.
このように構成されたＩＣパッケージ（４）は、ＩＣチ
ップ（１）を熱、水分、はこり等の外的環境から保護し
、電子部品として使いやすくするために設けられている
Ｑしかし、現状で用いられているＩＣパッケージでは、
外的環境からの保護と使いやすぐする目的のため、外観
からＩＣの温度ｔ−１！測することができない。The IC package (4) configured in this way is provided to protect the IC chip (1) from external environments such as heat, moisture, and dust, and to make it easier to use as an electronic component. The IC package used in
For the purpose of protection from the external environment and ease of use, the temperature of the IC is t-1 from the outside! cannot be measured.
次に動作について説明する。ここでは、Ｃ−ＭＯＳ（ｃ
ｏｍｐｌｅｍｅｎｔａｒｙ ｍｅｔａｌ−ｏｘｉｄｅ−
ｓｅｍｉｃｏｎｄｕｃｔｏｒ）ＩＣを例として第５図に
よって説明する。Next, the operation will be explained. Here, C-MOS (c
complementary metal-oxide-
This will be explained with reference to FIG. 5, taking a semiconductor (semiconductor) IC as an example.
第５図は寄生バイボーヲトランジスタを考慮し九〇−Ｍ
ＯＳインバータの断面図である。この第５図は、ニー基
板を用いたｐ−ウニ／Ｌ’構造を持つＣ−ＭＯ８ＩＣの
例である。図中のトランジスタＱ１゜Ｑ２及び抵抗Ｒ１
、Ｒ２は、前記Ｃ−ＭＯＳインバータに寄生してできた
トランジスタ及び抵抗を示している。Figure 5 shows 90-M considering the parasitic bi-bo transistor.
FIG. 3 is a cross-sectional view of an OS inverter. FIG. 5 is an example of a C-MO8IC having a p-Uni/L' structure using a knee substrate. Transistor Q1゜Q2 and resistor R1 in the diagram
, R2 indicate a transistor and a resistor parasitic to the C-MOS inverter.
第６図は第５図で示したパイボーフ型のトランジスタの
等価回路であシ、ｐｎｐｎＩｊｌｔ造のサイリスタと同
一回路になっている。FIG. 6 is an equivalent circuit of the Paibov type transistor shown in FIG. 5, and is the same circuit as the pnpnIjlt thyristor.
第７図は第６図の等価回路におけるｖｃｃ ＶＳ１１
間の電圧、電流特性である。第７図において、ｖＰ ｒ
ｙ／、は寄生サイリスタの耐圧、ｖＯは天使用電圧、ｖ
Ｍは寄生サイリスタの保持電圧、工Ｈｒｉ寄生サイリス
タの保持電流、ＲＬは寄生サイリスタの負荷抵抗を示し
ている。Figure 7 shows vcc VS11 in the equivalent circuit of Figure 6.
These are the voltage and current characteristics between. In FIG. 7, vP r
y/, is the withstand voltage of the parasitic thyristor, vO is the operating voltage, v
M indicates the holding voltage of the parasitic thyristor, Hri indicates the holding current of the parasitic thyristor, and RL indicates the load resistance of the parasitic thyristor.
サイリスタの特性として、高、低インピーダンスの二つ
の安定状態が存在する。高インピーダンス状態では、前
記サイリスタの耐圧Ｖ、は天使用電源電圧ｖ０より高く
、Ｃ−１０８回路が正常に動作している。しかし、外来
サージなどにより、サイリスタがトリガされ、耐圧がｖ
／Ｐで示される特性に変化すれば、電源電圧を支えるこ
とができなくなり、低インピーダンスの安定状態へ移行
し、ＶＣＣ−Ｖｓｓ間に大きな電流が流れる。前記電流
は、電源電圧が保持電圧ＶＩｌ（または、電源電流が保
持電流Ｘｘ）以下になるまで流れ続ける０
ＩＣｆ：使用している際外来サージ等によシ、寄生サイ
リスタがトリガされ過大な電流が流れることがある。（
以下この現象をラッチアップ現象とする。）前記フッチ
アツブ現象による過大な電流は、熱発生による前記ＩＣ
の温度上昇、及び前記ＩＣの動作不良や破壊を引き起こ
す。しかし、前記ＩＣパッケージでは、外的環境からの
保護、使いやすさを目的としておシ、温度を表示もしく
は変化を示すことにない。このため、前記ＩＣの外観だ
けで温度を観測または推定できないため、ラッチアップ
現象の発生を外観だけからでは判断できず、ＩＣの破壊
等が起こるという問題点があった。Thyristors have two stable states: high impedance and low impedance. In the high impedance state, the withstand voltage V of the thyristor is higher than the power supply voltage v0, and the C-108 circuit is operating normally. However, due to an external surge, etc., the thyristor is triggered and the withstand voltage decreases to v.
If the characteristics change to /P, it will no longer be able to support the power supply voltage, and will enter a stable state with low impedance, and a large current will flow between VCC and Vss. The current continues to flow until the power supply voltage falls below the holding voltage VIl (or the power supply current falls below the holding current It may flow. (
This phenomenon will hereinafter be referred to as a latch-up phenomenon. ) The excessive current due to the foot-absorbing phenomenon is caused by heat generation in the IC.
temperature rise, and malfunction or destruction of the IC. However, the IC package does not display temperature or indicate changes for the purpose of protection from the external environment and ease of use. Therefore, since the temperature cannot be observed or estimated only from the appearance of the IC, the occurrence of the latch-up phenomenon cannot be determined from the appearance alone, resulting in the problem that the IC may be destroyed.
従来のＩＣパッケージは以上のように構成されているの
で、Ｃ−ＭＯＳ ＩＣ’ｉ電子部品として使用している
際、外来サージによシフツチアップ現象が発生すること
がある。フッチアツブ現象により、過大な電流が流れ、
前記ＩＣの温度上昇、及びＩＣｏ動作不良や破壊を引き
起こす０
本発明は上記のような問題点を解消するためになされた
もので、ＴＣの温度上昇を外観上で判断できるようにす
ることを目的とする０
〔課題を解決するための手段〕
本発明に係るＩＣパッケージは、ＩＣの温度上昇により
、色の変化する性質をもった塗料やフィルムからなる温
度検品部材をパッケージ表面の一部もしくは全面に設け
るようにしたものである。Since the conventional IC package is constructed as described above, when used as a C-MOS IC'i electronic component, a shift-up phenomenon may occur due to an external surge. Due to the footfall phenomenon, excessive current flows,
The present invention was made to solve the above-mentioned problems, and aims to make it possible to judge the temperature rise of the TC from its appearance. [Means for Solving the Problems] The IC package according to the present invention uses a temperature inspection member made of paint or film that changes color as the temperature of the IC increases, on a part or the entire surface of the package. It was designed to be installed in
本発明によるＩＣパッケージは、フッチアツブ現象の発
生による湿度上昇によって温度検出部材が呈色費化する
。In the IC package according to the present invention, the temperature detecting member becomes discolored due to an increase in humidity due to the occurrence of the foot-absorbing phenomenon.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例によるＩＣパッケージを示すも
ので、温度変化により色の変化を示す性質をもった塗料
をＩＣパッケージ表面の一部に塗布したものである。図
において、（４）はＩＣパッケージ、（５）は所定の塗
料（６）で押印された標識である。前記塗料（６）は押
印時には所定の色相を呈し、フッチアツブ現象の発生に
よるＩＣの湿度上昇によシ、色相が所定の色相と異なる
色相に変化するものが使用されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an IC package according to an embodiment of the present invention, in which a part of the surface of the IC package is coated with a paint that changes color depending on temperature changes. In the figure, (4) is an IC package, and (5) is a mark stamped with a predetermined paint (6). The paint (6) used is one that exhibits a predetermined hue when stamping, and whose hue changes to a hue different from the predetermined hue when the humidity of the IC increases due to the occurrence of the foot build-up phenomenon.
次に動作について説明する。考案のＩＣパッケージ（４
）は、ラッチアップ現象が発生していないときの表示（
６）は所定の色相を呈し、ラッチアップ現象が発生する
と、表示（６）ハ異なる色相に変化する０この色相の変
化により、フッチアツブ現象の発生を前記ＩＣの外観か
ら知ることができる０以上のことは、ＩＣの動作不良や
破壊の原因であるラッチアップ現象の発生をＩＣの外観
で判断できることになる０
第２図はこの発明の他の実施例によるＩＣ／＜ツケージ
を示すもので、温度変化により色の変化を示す性質をも
ったフィルムをＩＣパッケージ表面の一部に貼付けたも
のである０図において、（６）は温度が変化すると色相
が変化するフィルムからなる温度検出部材である。前記
フィルムは、通常は所定の色相を呈し、フッチアツブ現
象の発生によるＩＣの温度上昇により、所定の色相と異
なる色相に変化する０この色相の変化によシ、ラッチア
ップ現象の発生を前記ＩＣの外観から知ることができる
。以上のことは、ＩＣＯ動作不良や破壊の原因であるラ
ッチアップ現象の発生をＩＣの外観で判断できることに
なる。Next, the operation will be explained. Invented IC package (4
) is the display when no latch-up phenomenon occurs (
6) exhibits a predetermined hue, and when the latch-up phenomenon occurs, the display (6) changes to a different hue.Due to this change in hue, the occurrence of the latch-up phenomenon can be known from the appearance of the IC. This means that the occurrence of the latch-up phenomenon, which causes malfunction or destruction of the IC, can be determined from the appearance of the IC. FIG. In Figure 0, which shows a film that exhibits a color change depending on the temperature change, is attached to a part of the surface of an IC package, (6) is a temperature detection member made of a film that changes hue when the temperature changes. The film usually exhibits a predetermined hue, and changes to a hue different from the predetermined hue due to an increase in the temperature of the IC due to the occurrence of the latch-up phenomenon. This change in hue prevents the occurrence of the latch-up phenomenon in the IC. You can tell from the appearance. The above means that the occurrence of the latch-up phenomenon, which is a cause of ICO malfunction or destruction, can be determined from the appearance of the IC.
なお、上記実施例においてはＩＣパッケージの表面の一
部に温度検出部材を設けた場合について説明したが、Ｉ
Ｃパッケージ表面の全面に温度検出部材を設けてもよい
。In the above embodiment, a case where a temperature detection member was provided on a part of the surface of the IC package was explained, but I
A temperature detection member may be provided on the entire surface of the C package.
さらに、ここではＩＣパッケージの例としてＤ工Ｐを図
に用いたが、他の極類のＩＣパッケージであってもよい
。Furthermore, although a D/P is used here as an example of an IC package, other types of IC packages may be used.
以上のようにこの発明によれば、ラッチアップ現象の発
生によって温度検出部材が呈色変化をするので、ＩＣの
外観からラッチアップ現象の発生を判断できる効果があ
る。また、ＩＣの温度を外観で観測できるので、ＩＣの
８度が上昇しているのに気付かず融れ火傷をするという
不注意を防ぐ効果もある。さらに、電子部品の一つとし
て組込まれ動作を確認している際でも、測定機器に接続
することなしにラッチアップ現象の発生を知ることがで
きるという効果もある。As described above, according to the present invention, since the temperature detection member changes color due to the occurrence of the latch-up phenomenon, it is possible to determine the occurrence of the latch-up phenomenon from the appearance of the IC. In addition, since the temperature of the IC can be observed visually, it is also effective in preventing carelessness such as not noticing that the temperature of the IC has risen by 8 degrees and causing the IC to melt and cause burns. Furthermore, even when the device is installed as an electronic component and its operation is being checked, it is possible to detect the occurrence of latch-up without connecting it to a measuring device.
第１図はこの発明の一実施例によるＩＣパッケージの斜
視図、第２図はこの発明の他の実施例によるＩＣパッケ
ージの斜視図、第３図〜第７図は従来のＩＣパッケージ
を説明する図で、第３図は従来のＩＣパッケージの斜視
図、第４図はＩＣの構造を説明する断面図、第５図は寄
生バイポーフトランジスタを考慮したＣ−ＭＯＳインバ
ータの断面図、第６図は第３図のバイボーフ型のトフン
ジヌタの等価回路、第７図は第６図の等価回路における
ｖｃｃ ｖｓｓ間の電圧、電流特性図である。
図において、（４）ｒｉＩＣパッケージ、（６）は温度
検６部材である。
なお、各同一符号は同一、または相当部分を示す。
代地人大岩増雄
第１図
第３図
第２図
第４図
第５図
第６図
に
寄主す１す又りｎ負荷重（４ガ。FIG. 1 is a perspective view of an IC package according to an embodiment of the present invention, FIG. 2 is a perspective view of an IC package according to another embodiment of the invention, and FIGS. 3 to 7 illustrate conventional IC packages. In the figures, Fig. 3 is a perspective view of a conventional IC package, Fig. 4 is a cross-sectional view explaining the structure of the IC, Fig. 5 is a cross-sectional view of a C-MOS inverter considering parasitic bipolar transistors, and Fig. 6 The figure shows the equivalent circuit of the Bybov type Tofunjinuta shown in FIG. 3, and FIG. 7 shows the voltage and current characteristics between vcc and vss in the equivalent circuit of FIG. 6. In the figure, (4) is an riIC package, and (6) is a temperature sensor 6 member. Note that the same reference numerals indicate the same or equivalent parts. Figure 1, Figure 3, Figure 2, Figure 4, Figure 5, Figure 6 shows the host's load (4 ga).
Claims (1)
ケージ表面の一部もしくは全面に上記ＩＣの温度上昇に
よる温度変化で色相が所定の色相から所定の色相と異な
る色相に変化する温度検出部材を設けたことを特徴とし
たＩＣパッケージ。In an IC package in which an IC is encapsulated, a temperature detection member is provided on a part or the entire surface of the IC package so that the hue changes from a predetermined hue to a hue different from the predetermined hue due to a temperature change due to a temperature rise of the IC. Featured IC package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160616A JPH0451546A (en) | 1990-06-19 | 1990-06-19 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160616A JPH0451546A (en) | 1990-06-19 | 1990-06-19 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451546A true JPH0451546A (en) | 1992-02-20 |
Family
ID=15718786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2160616A Pending JPH0451546A (en) | 1990-06-19 | 1990-06-19 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451546A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9665397B2 (en) | 2001-03-22 | 2017-05-30 | Cornami, Inc. | Hardware task manager |
-
1990
- 1990-06-19 JP JP2160616A patent/JPH0451546A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9665397B2 (en) | 2001-03-22 | 2017-05-30 | Cornami, Inc. | Hardware task manager |
| US10185502B2 (en) | 2002-06-25 | 2019-01-22 | Cornami, Inc. | Control node for multi-core system |
| US10817184B2 (en) | 2002-06-25 | 2020-10-27 | Cornami, Inc. | Control node for multi-core system |
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