JPH0451330U - - Google Patents
Info
- Publication number
- JPH0451330U JPH0451330U JP9447990U JP9447990U JPH0451330U JP H0451330 U JPH0451330 U JP H0451330U JP 9447990 U JP9447990 U JP 9447990U JP 9447990 U JP9447990 U JP 9447990U JP H0451330 U JPH0451330 U JP H0451330U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit boards
- lower printed
- matrix
- production instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案に係る生産指示装置の一実施例
を示す概略構成図、第２図はその要部拡大断面図
である。第３図は選択パターンを示す説明図、第
４図は従来の生産指示装置に於いて上記選択パタ
ーンをコンピユーターに入力するソフトの一例を
示す図面である。
ＣＲ１，ＣＲ２，ＣＲ３……リレー、ＬＡ，Ｌ
Ｂ，ＬＣ，ＬＤ……ランプ、１１，１２……プリ
ント基板、１１ａ，１２ａ……ピン孔、１３……
ピン。
FIG. 1 is a schematic configuration diagram showing an embodiment of a production instruction device according to the present invention, and FIG. 2 is an enlarged sectional view of the main part thereof. FIG. 3 is an explanatory diagram showing a selection pattern, and FIG. 4 is a drawing showing an example of software for inputting the selection pattern into a computer in a conventional production instruction apparatus. CR1, CR2, CR3...Relay, LA, L
B, LC, LD... lamp, 11, 12... printed circuit board, 11a, 12a... pin hole, 13...
pin.
Claims (1)
複数の部品に対応する複数の指示器とを縦と横に
配列し、それらを導線によつて上下のプリント基
板に網状に配線してマトリクス回路を形成し、上
下のプリント基板の上記マトリクス回路の交叉す
るそれぞれの位置に、導電性ピンが挿入されるピ
ン孔を穿設したことを特徴とする生産指示装置。 A matrix circuit is formed by arranging multiple switches corresponding to multiple work codes and multiple indicators corresponding to multiple parts vertically and horizontally, and wiring them in a net shape to the upper and lower printed circuit boards using conductive wires. A production instruction device characterized in that pin holes into which conductive pins are inserted are formed at respective positions where the matrix circuits intersect on the upper and lower printed circuit boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9447990U JPH0451330U (en) | 1990-09-07 | 1990-09-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9447990U JPH0451330U (en) | 1990-09-07 | 1990-09-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451330U true JPH0451330U (en) | 1992-04-30 |
Family
ID=31832462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9447990U Pending JPH0451330U (en) | 1990-09-07 | 1990-09-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451330U (en) |
-
1990
- 1990-09-07 JP JP9447990U patent/JPH0451330U/ja active Pending
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