JPH0451144U - - Google Patents
Info
- Publication number
- JPH0451144U JPH0451144U JP1990091617U JP9161790U JPH0451144U JP H0451144 U JPH0451144 U JP H0451144U JP 1990091617 U JP1990091617 U JP 1990091617U JP 9161790 U JP9161790 U JP 9161790U JP H0451144 U JPH0451144 U JP H0451144U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrate
- semiconductor device
- groove
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990091617U JPH0451144U (enFirst) | 1990-09-03 | 1990-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990091617U JPH0451144U (enFirst) | 1990-09-03 | 1990-09-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451144U true JPH0451144U (enFirst) | 1992-04-30 |
Family
ID=31827421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990091617U Pending JPH0451144U (enFirst) | 1990-09-03 | 1990-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451144U (enFirst) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126645A (ja) * | 1997-07-03 | 1999-01-29 | Mitsubishi Electric Corp | 半導体集積回路装置とその製造方法 |
| WO2003003445A1 (fr) * | 2001-06-29 | 2003-01-09 | Fujitsu Limited | Feuille de remplissage sous-jacent, procede de remplissage sous-jacent d'une puce semi-conductrice, et procede de montage d'une puce semi-conductrice |
| WO2008078746A1 (ja) * | 2006-12-26 | 2008-07-03 | Panasonic Corporation | 半導体素子の実装構造体及び半導体素子の実装方法 |
-
1990
- 1990-09-03 JP JP1990091617U patent/JPH0451144U/ja active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126645A (ja) * | 1997-07-03 | 1999-01-29 | Mitsubishi Electric Corp | 半導体集積回路装置とその製造方法 |
| WO2003003445A1 (fr) * | 2001-06-29 | 2003-01-09 | Fujitsu Limited | Feuille de remplissage sous-jacent, procede de remplissage sous-jacent d'une puce semi-conductrice, et procede de montage d'une puce semi-conductrice |
| JP4778667B2 (ja) * | 2001-06-29 | 2011-09-21 | 富士通株式会社 | アンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法 |
| WO2008078746A1 (ja) * | 2006-12-26 | 2008-07-03 | Panasonic Corporation | 半導体素子の実装構造体及び半導体素子の実装方法 |
| JP5039058B2 (ja) * | 2006-12-26 | 2012-10-03 | パナソニック株式会社 | 半導体素子の実装構造体 |