JPH0451093A - Display control circuit - Google Patents

Display control circuit

Info

Publication number
JPH0451093A
JPH0451093A JP15940490A JP15940490A JPH0451093A JP H0451093 A JPH0451093 A JP H0451093A JP 15940490 A JP15940490 A JP 15940490A JP 15940490 A JP15940490 A JP 15940490A JP H0451093 A JPH0451093 A JP H0451093A
Authority
JP
Japan
Prior art keywords
crt
registers
lcd
values
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15940490A
Inventor
Kazuaki Inoue
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP15940490A priority Critical patent/JPH0451093A/en
Publication of JPH0451093A publication Critical patent/JPH0451093A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To make simultaneous displays on a line-sequential type (LCD) display device and a dot-sequential type (CRT) display device by upplying values in registers which determine the display timing of the line-sequential scanning type (LCD) display device as values of registers determining the display timing of the dot-sequential scanning type (CRT) display device.
CONSTITUTION: Application software 12 sets the values necessary for display operation in the registers 4 and 7 for the CRT mode of a display control circuit 1 through a microprocessor 13. A CRT timing generating circuit 10 generates timing for the CRT according to those values. Arithmetic circuits 5 and 8 in the display control circuit 1, on the other hand, performs necessary arithmetic for the value in the registers 4 and 7 for the CRT mode corresponding to the kind of the registers and sets the values in the registers 6 and 7 for the LCD mode. An LCD timing generating crcuit 11 generates timing for the LCD according to the values. Consequently, the simultaneous displays can be made on the CRT 2 and LCD 3.
COPYRIGHT: (C)1992,JPO&Japio
JP15940490A 1990-06-18 1990-06-18 Display control circuit Pending JPH0451093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15940490A JPH0451093A (en) 1990-06-18 1990-06-18 Display control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15940490A JPH0451093A (en) 1990-06-18 1990-06-18 Display control circuit

Publications (1)

Publication Number Publication Date
JPH0451093A true JPH0451093A (en) 1992-02-19

Family

ID=15693031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15940490A Pending JPH0451093A (en) 1990-06-18 1990-06-18 Display control circuit

Country Status (1)

Country Link
JP (1) JPH0451093A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907315A (en) * 1993-03-17 1999-05-25 Ultimatte Corporation Method and apparatus for adjusting parameters used by compositing devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907315A (en) * 1993-03-17 1999-05-25 Ultimatte Corporation Method and apparatus for adjusting parameters used by compositing devices

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