JPH0450783B2 - - Google Patents
Info
- Publication number
- JPH0450783B2 JPH0450783B2 JP15604487A JP15604487A JPH0450783B2 JP H0450783 B2 JPH0450783 B2 JP H0450783B2 JP 15604487 A JP15604487 A JP 15604487A JP 15604487 A JP15604487 A JP 15604487A JP H0450783 B2 JPH0450783 B2 JP H0450783B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- averaging
- square operation
- performs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012935 Averaging Methods 0.000 claims description 29
- 238000005259 measurement Methods 0.000 claims description 21
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000000691 measurement method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
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- Dc Digital Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
（産業上の利用分野）
本発明は、デイジタル信号にデイジタル変調を
施した信号をを伝送するデイジタル通信システム
の受信側において搬送波電力対雑音電力比（Ｃ／
Ｎ）を測定するＣ／Ｎ測定回路に関する。
（従来の技術）
デイジタル通信システムでは、復調器あるい
は、復調器を含む伝送路全体の性能を評価するた
め、復調器で復号された符号のビツト誤り率
（BER）に対する性能指数として伝送情報１ビツ
ト当りのエネルギー対雑音電力密度との比
（Eb／Np）を定義するが、これは次の式(1)で示す
如く計算によつて求められる。
Eb／Np＝Ｃ／Ｎ・Ｂ／Ｒ ……(1)
ここで、Ｃ／Ｎは搬送波電力対雑音電力比、Ｂ
は復調器の等価雑音帯域幅、Ｒはデータ伝送速度
で、２−PSK変調方式ではシンボルレートと一
致するが、４−PSK変調方式ではシンボルレー
トの２倍となることは良く知られている通りであ
る。
ところで、式(1)から明らかなように、Eb／Np
を求めるにはＣ／Ｎを測定する必要がある。そこ
で、例えば衛星回線におけるEb／Npを決定する
場合の従来のＣ／Ｎ測定方式は、第５図に示す如
く、衛星の中継器に比べて狭帯域の復調器１０の
前段にバンドパスフイルタ９を配置し、受信変調
信号が入力される復調器１０の入力のIF帯で
Ｃ／Ｎを測定するようにしている。その測定手順
は、まずバンドパスフイルタ９の帯域の中心に無
変調波あるいは変調波を送信して、バンドパスフ
イルタ９出力の電力を測定しＣ＋Ｎを求める。次
に、無変調波あるいは変調波の送信を止めるか、
または送信搬送波周波数をずらして受信信号がバ
ンドパスフイルタ９の帯域外となるようにしてバ
ンドパスフイルタ９の出力電力を測定し、Ｎを求
める。そして、先に求めたＣ＋ＮからＮを引くと
Ｃが求まり、両者からＣ／Ｎが求まる。
なお、この場合のＢはバンドパスフイルタ９の
等価雑音帯域幅である。
（発明が解決しようとする問題点）
しかし、前述した従来のＣ／Ｎ測定方式には次
の如き種々の問題点がある。
まず、正確な等価雑音帯域幅が既知であるバン
ドパスフイルタが測定用として必要であり、ま
た、電力計等の測定器が別に必要である。
また、Ｃ／Ｎの測定では無変調波あるいは変調
波を送信し、それを止めるか周波数をずらす操作
をIF帯においてするので、操作が繁雑であるだ
けでなく、適用状態においてＣ／Ｎ測定を行うこ
とが困難である。
本発明は、このような従来の問題点に鑑みなさ
れたもので、その目的は、運用時におけるＣ／Ｎ
測定を簡単かつ容易に、しかも正確に行うことが
できるＣ／Ｎ測定回路を提供することにある。
（問題点を解決するための手段）
前記目的を達成するために、本発明のＣ／Ｎ測
定回路は次の如き構成を有する。
即ち、本発明のＣ／Ｎ測定回路は、デイジタル
信号にデイジタル変調を施した信号を伝送するデ
イジタル通信システムの受信側において搬送波電
力対雑音電力化（Ｃ／Ｎ）を測定するＣ／Ｎ測定
回路であつて；受信復調された復調信号をその復
調の際に再生されたシンボルクロツクのタイミン
グで標本化し各標本値を量子化ビツト数ｎからな
るデイジタル時系列データへ変換するＡ／Ｄ変換
器と；前記Ａ／Ｄ変換器の出力を受けて各デイジ
タル時系列データについて絶対値操作を行う絶対
値操作回路と；Ｎ（Ｎ＞０の整数）シンボルの間
における前記絶対値操作回路の出力について平均
化処理を行う第１の平均化回路と；前記第１の平
均化回路の出力を受けて２乗操作を行う第１の２
乗操作回路と；前記Ａ／Ｄ変換器の出力を受けて
各デイジタル時系列データについて２乗操作の行
う第２の２乗操作回路と；Ｎ（Ｎ＞０の整数）シ
ンボルの間における前記第２の２乗操作回路の出
力について平均化処理を行う第２を行う平均化回
路と；前記第２の平均化回路の出力値から前記第
１の２乗操作回路の出力値を減ずる減算回路と；
前記第１の２乗操作回路および前記減算回路の各
出力を受けて前記比（Ｃ／Ｎ）を出力するＣ／Ｎ
変換回路と；を備えたことを特徴とするものであ
る。
（作用）
次に、前記の如く構成される本発明のＣ／Ｎ測
定回路の作用を説明する。
Ａ／Ｄ変換器は、受信復調された復調信号（ア
イパターンを形成するアナログ信号）をその復調
の際に再生されたシンボルクロツクのタイミング
で標本化し、各標本値を量子化ビツト数ｎからな
るデイジタル時系列データへ変換する。
このＡ／Ｄ変換器の出力は、復調信号の信号点
における振幅値を示すが、これはまず絶対値操作
回路、第１の平均化回路においてそれぞれ絶対値
がとられ、十分に長いＮ（ｎ＞０の整数）シルボ
ル間平均化される。その結果、信号に相加された
雑音成分が相殺され第１の平均化回路の出力には
雑音成分のない信号（振幅値）が得られる。
従つて第１の２乗操作回路の出力には、雑音が
ない場合の信号電力Ｓが得られる。これを式で示
せば次の如くになる。
Ａ／Ｄ変換器の出力である時系列データをdi
（ｉ＝０，１，２，……，ｎ）、雑音がない場合の
信号点の振幅をＡ、雑音がない場合の復調信号の
電力をＳ、平均操作を行うシンボル数をＮとすれ
ば、
Ａ＝１／ＮN-1
Σi-0
(Q)di(Q) ……(2)
Ｓ＝A2 ……(3)
ところで、復調信号に相加された雑音成分は雑
音がない場合の信号点の振幅Ａを中心としたガウ
ス分布を示すが、その雑音成分の電力σ2は
σ2＝１／ＮN-1
Σi-0
（(Q)di(Q)−Ａ）2 ……(4)
で表され、式(2)を考慮すると
σ2＝１／ＮN-1
Σi-0
di 2−A2 ……(5)
となる。
即ち、Ａ／Ｄ変換器の出力を第２の２乗操作回
路において２乗操作し、さらに第２の平均化回路
において十分に長いＮシンボル間の平均化処理す
れば式(5)の第１項が得られるから、減算回路にお
いて、前記第２の平均化回路の出力値から前記第
１の２乗操作回路の出力値を減ずることで式(5)に
示す雑音電力σ2が得られる。
その結果、Ｃ／Ｎ変換回路において第１の２乗
操作回路の出力（信号電力Ｓ）と減算回路の出力
（雑音電力σ2）の比をとることでＣ／Ｎの測定を
得ることができる。
以上説明したように、本発明のＣ／Ｎ測定回路
によれば、復調信号にデイジタル数値演算を施し
て信号電力と雑音電力とを得ることができるの
で、従来の如きIF帯での繁雑な操作を行う必要
がなく、運用時のＣ／Ｎ測定を可能とし、またい
かなる測定器具も不要である。本発明のＣ／Ｎ測
定回路は復調器に組み込むことあるいは外付けす
ることが可能であつて、いずれの場合でも復調器
単体として簡単かつ容易に、しかも正確にＣ／Ｎ
測定を行うことができる。そして、本回路はデイ
ジタル回路で構成されているので、無調整で高安
定な動作を期待でき、LSI化による小形化が可能
である、等の効果が得られる。
（実施例）
以下、本発明の実施例を図面を参照して説明す
る。
第１図は本発明の一実施例に係るＣ／Ｎ測定回
路を示す。このＣ／Ｎ測定回路は、Ａ／Ｄ変換器
１と、絶対値操作回路２と、第１の平均化回路３
と、第１の２乗操作回路４と、第２の２乗操作回
路５と、第２の平均化回路６と、減算回路７と、
Ｃ／Ｎ変換回路８とを基本的に備える。
Ａ／Ｄ変換器１では、復調信号（アイパターン
を形成するアナログ信号）を再生シンボルクロツ
クのタイミング（信号点位置である）で標本化し
各標本値を量子化ビツト数ｎからなるデイジタル
時系列データdi（ｉ＝０，１，２，……，ｎ）へ
変換し、それを絶対値操作回路２と第２の２乗操
作回路５とへ送出する。
絶対値操作回路２では、デイジタル時系列デー
タdiの絶対値(Q)di(Q)を求める操作をし、それを第
１の平均化回路３へ与える。具体的には、この絶
対値操作回路２は、例えば第２図に示す如く、排
他的論理和回路１２と加算回路１３とで構成でき
る。第２図において、ｎ＝３とした場合の絶対値
操作を説明する。入力するデイジタル時系列デー
タdiが、第１表に示す如く、値３から値−４まで
の正負値を３ビツトで表現し、負数は２の補数で
表現されている場合、排他的論理和回路１２では
入力したデイジタル時系列データdi（ｉ＝０，１，
２）の最上位ビツト（MSB）が“１”のとき、
即ち入力値が負値のときは全３ビツトの論理値を
反転してそれを加算回路１３の一方の入力へ与え
る。なお、MSB＝“１”のときは、全３ビツトの
論理値をそのまま加算回路１３の一方の入力へ与
える。そして、加算回路１３では、MSBの内容
が他方の入力へ与えられるので、排他的論理和回
路１２の出力にMSBの内容（“１”または“０”）
を加える操作を行う。その結果、第２表に示す如
き絶対値が得られる。
(Industrial Application Field) The present invention provides a carrier power-to-noise power ratio (C/
This invention relates to a C/N measurement circuit that measures C/N. (Prior art) In digital communication systems, in order to evaluate the performance of a demodulator or the entire transmission path including the demodulator, one bit of transmission information is used as a figure of merit for the bit error rate (BER) of the code decoded by the demodulator. The ratio of energy per unit to noise power density (E b /N p ) is defined, and this is obtained by calculation as shown in the following equation (1). E b /N p = C/N・B/R ...(1) Here, C/N is the carrier power to noise power ratio, B
is the equivalent noise bandwidth of the demodulator, R is the data transmission rate, and as is well known, it matches the symbol rate in the 2-PSK modulation system, but is twice the symbol rate in the 4-PSK modulation system. It is. By the way, as is clear from equation (1), E b /N p
To find this, it is necessary to measure the C/N. Therefore, the conventional C/N measurement method for determining E b /N p in a satellite link, for example, uses a band pass at the front stage of the demodulator 10, which has a narrower band than the satellite repeater, as shown in Fig. 5. A filter 9 is arranged to measure the C/N in the input IF band of the demodulator 10 into which the received modulated signal is input. The measurement procedure is to first transmit an unmodulated wave or a modulated wave to the center of the band of the bandpass filter 9, measure the power of the output of the bandpass filter 9, and obtain C+N. Next, either stop transmitting unmodulated waves or modulated waves, or
Alternatively, the output power of the bandpass filter 9 is measured by shifting the transmission carrier frequency so that the received signal is outside the band of the bandpass filter 9, and N is determined. Then, C is found by subtracting N from the previously found C+N, and C/N is found from both. Note that B in this case is the equivalent noise bandwidth of the bandpass filter 9. (Problems to be Solved by the Invention) However, the conventional C/N measurement method described above has the following various problems. First, a bandpass filter whose accurate equivalent noise bandwidth is known is required for measurement, and a separate measuring device such as a power meter is also required. In addition, in C/N measurement, an unmodulated wave or a modulated wave is transmitted, and operations to stop it or shift the frequency are performed in the IF band, which not only makes the operation complicated, but also makes C/N measurement difficult in the application state. Difficult to do. The present invention was made in view of such conventional problems, and its purpose is to improve C/N during operation.
It is an object of the present invention to provide a C/N measurement circuit that can perform measurements simply, easily, and accurately. (Means for Solving the Problems) In order to achieve the above object, the C/N measuring circuit of the present invention has the following configuration. That is, the C/N measuring circuit of the present invention is a C/N measuring circuit that measures carrier power to noise power (C/N) on the receiving side of a digital communication system that transmits a signal obtained by digitally modulating a digital signal. An A/D converter that samples the received demodulated signal at the timing of the symbol clock reproduced during demodulation and converts each sample value into digital time series data consisting of n quantized bits. and; an absolute value manipulation circuit that receives the output of the A/D converter and performs absolute value manipulation on each digital time series data; and; about the output of the absolute value manipulation circuit between N (an integer of N>0) symbols. a first averaging circuit that performs an averaging process; a first averaging circuit that performs a squaring operation upon receiving the output of the first averaging circuit;
a second squaring operation circuit that receives the output of the A/D converter and performs a squaring operation on each digital time series data; an averaging circuit that performs a second averaging process on the output of the 2 square operation circuit; a subtraction circuit that subtracts the output value of the first square operation circuit from the output value of the second averaging circuit; ;
a C/N that receives each output of the first square operation circuit and the subtraction circuit and outputs the ratio (C/N);
It is characterized by comprising a conversion circuit; (Operation) Next, the operation of the C/N measurement circuit of the present invention configured as described above will be explained. The A/D converter samples the received demodulated signal (analog signal forming an eye pattern) at the timing of the symbol clock reproduced during demodulation, and converts each sample value from the number n of quantized bits. Convert to digital time series data. The output of this A/D converter indicates the amplitude value at the signal point of the demodulated signal, but the absolute value is first taken in the absolute value manipulation circuit and the first averaging circuit, and the amplitude value is determined by the sufficiently long N(n >0 integer) is averaged between silbols. As a result, the noise component added to the signal is canceled out, and a signal (amplitude value) free of noise components is obtained at the output of the first averaging circuit. Therefore, the signal power S in the absence of noise is obtained at the output of the first square operation circuit. This can be expressed as a formula as follows. The time series data that is the output of the A/D converter is d i
(i = 0, 1, 2, ..., n), the amplitude of the signal point in the absence of noise is A, the power of the demodulated signal in the absence of noise is S, and the number of symbols to be averaged is N. , A=1/N N-1 Σ i-0 (Q)d i (Q) ...(2) S=A 2 ...(3) By the way, the noise component added to the demodulated signal is free of noise. In this case, the power of the noise component σ 2 is σ 2 = 1/N N-1 Σ i-0 ((Q)d i (Q)−A) 2 ...(4), and considering equation (2), σ 2 =1/N N-1 Σ i-0 d i 2 −A 2 ...(5). That is, by squaring the output of the A/D converter in the second squaring operation circuit, and further averaging processing over sufficiently long N symbols in the second averaging circuit, the first of equation (5) can be obtained. Since the term is obtained, the noise power σ 2 shown in equation (5) can be obtained by subtracting the output value of the first square operation circuit from the output value of the second averaging circuit in the subtraction circuit. As a result, the C/N can be measured by taking the ratio of the output of the first square operation circuit (signal power S) and the output of the subtraction circuit (noise power σ 2 ) in the C/N conversion circuit. . As explained above, according to the C/N measurement circuit of the present invention, signal power and noise power can be obtained by performing digital numerical calculation on the demodulated signal, so that the conventional complicated operation in the IF band is not required. It is not necessary to perform C/N measurement during operation, and there is no need for any measuring equipment. The C/N measurement circuit of the present invention can be incorporated into a demodulator or attached externally, and in either case, the C/N measurement circuit can easily and easily measure the C/N as a single demodulator.
Measurements can be taken. Furthermore, since this circuit is composed of a digital circuit, it can be expected to operate with high stability without any adjustment, and can be miniaturized by making it into an LSI. (Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a C/N measuring circuit according to an embodiment of the present invention. This C/N measurement circuit includes an A/D converter 1, an absolute value operation circuit 2, and a first averaging circuit 3.
, a first square operation circuit 4, a second square operation circuit 5, a second averaging circuit 6, a subtraction circuit 7,
It basically includes a C/N conversion circuit 8. The A/D converter 1 samples the demodulated signal (analog signal forming the eye pattern) at the timing of the reproduced symbol clock (signal point position) and converts each sample value into a digital time series consisting of the number n of quantized bits. It converts into data di ( i =0, 1, 2, . . . , n) and sends it to the absolute value manipulation circuit 2 and the second square manipulation circuit 5. The absolute value manipulation circuit 2 performs an operation to obtain the absolute value (Q)d i (Q) of the digital time series data d i and supplies it to the first averaging circuit 3 . Specifically, the absolute value manipulation circuit 2 can be constructed of an exclusive OR circuit 12 and an adder circuit 13, as shown in FIG. 2, for example. In FIG. 2, the absolute value operation when n=3 will be explained. As shown in Table 1, if the input digital time series data d i expresses positive and negative values from value 3 to value -4 using 3 bits, and negative numbers are expressed using 2's complement, exclusive OR The circuit 12 inputs digital time series data d i (i=0, 1,
2) When the most significant bit (MSB) is “1”,
That is, when the input value is a negative value, all three bits of logical values are inverted and applied to one input of the adder circuit 13. It should be noted that when MSB="1", all three bits of logical values are applied as they are to one input of the adder circuit 13. Then, in the adder circuit 13, the contents of the MSB are given to the other input, so the contents of the MSB (“1” or “0”) are sent to the output of the exclusive OR circuit 12.
Perform the operation to add. As a result, absolute values as shown in Table 2 are obtained.
【表】
３ビツトによる正 絶対値
負表示
次に、第１の平均化回路３では、十分に長いＮ
（Ｎ＞０の整数）シンボルの間平均をとる操作を
し、その平均値を第１の２乗操作回路４へ与え
る。
具体的には、この第１の平均化回路３は、例え
ば第３図に示す如く、加算回路１３と１サンプル
遅延回路１４と、割算回路１５とで構成される。
加算回路１３と１サンプル遅延回路１４はＮシ
ンボルの間の入力値を積分する積分回路であつ
て、割算回路１５はこの積分回路の出力値をシン
ボル数Ｎで割算し平均値を求める操作を行う。な
お、１サンプル遅延回路１４はＮシンボルごとに
リセツトされる。
ここで、信号に相加される雑音成分は、雑音が
少ない場合の信号点の振幅Ａを中心としたガウス
分布を示すので、以上の処置によつて雑音成分は
相殺し合う。つまり、第１の平均化回路３の出力
は雑音がない場合の信号点の振幅Ａを与えること
になる。従つて、振幅Ａは前記式(2)で与えられ
る。また、信号電力Ｓは第１の２乗操作回路４の
出力に得られる。
一方、Ａ／Ｄ変換器１の出力は、第２の２乗操
作回路５において２乗操作が施され、さらに第２
の平均化回路６において、前記第１の平均化回路
３と同様に、十分に長いＮ（Ｎ＞０の整数）シン
ボルの間の平均がとられる。その結果、前記式(5)
の第１項が得られるので、減算回路７において第
２の平均化回路６の出力値から第１の２乗操作回
路４の出力値を減ずることを行い前記式(5)で示さ
れる雑音電力σ2を得ることができる。
斯くして、Ｃ／Ｎ変換回路８では、第１の２乗
操作回路の出力（信号電力Ｓ）と減算回路７の出
力（雑音電力σ2）の比をとることができ、測定
Ｃ／Ｎを得ることができる。なお、このＣ／Ｎ変
換回路８の構成方法であるが、実際の入力値に対
し割算をする方式、あるいは各々の入力値の対数
をとつて減算を行う方式等の他に、簡単な構成方
式として第４図に示すものがある。第４図におい
て、符号１６はROMからなる変換テーブルであ
る。この変換テーブル１６にはＳ／σ2の各種計算
値が設定してあり、信号電力Ｓと雑音電力σ2を読
出アドレスとして与えるようにしたものである。
以上が本発明によるＣ／Ｎ測定回路の原理であ
るが、本回路を適用するに当つては伝送路上で受
ける信号の歪、あるいはフイルタ系の不整合によ
る符号間干渉がなく、かつ、伝送路上で相加され
る雑音がガウス雑音である必要がある。
（発明の効果）
以上説明したように、本発明のＣ／Ｎ測定回路
によれば、復調信号にデイジタル数値演算を施し
て信号電力と雑音電力とを得ることができるの
で、従来の如きIF帯での繁雑な操作を行う必要
がなく、運用時のＣ／Ｎ測定を可能とし、またい
かなる測定器具も不要である。本発明のＣ／Ｎ測
定回路は復調器に組み込むことあるいは取付けす
ることが可能であつて、いずれの場合でも復調器
単体として簡単かつ容易に、しかも正確にＣ／Ｎ
測定を行うことができる。そして、本回路はデイ
ジタル回路で構成されているので、無調整で高安
定な動作を期待でき、LSI化による小形化が可能
である、等の効果が得られる。[Table] Positive absolute value Negative display using 3 bits Next, in the first averaging circuit 3, a sufficiently long N
An operation is performed to take an average among (N>0 integer) symbols, and the average value is given to the first square operation circuit 4. Specifically, the first averaging circuit 3 includes an addition circuit 13, a one-sample delay circuit 14, and a division circuit 15, as shown in FIG. 3, for example. The adder circuit 13 and the 1-sample delay circuit 14 are integrator circuits that integrate the input value between N symbols, and the divider circuit 15 divides the output value of this integrator circuit by the number of symbols N to obtain an average value. I do. Note that the one sample delay circuit 14 is reset every N symbols. Here, since the noise component added to the signal exhibits a Gaussian distribution centered on the amplitude A of the signal point when the noise is small, the noise components cancel each other out by the above procedure. In other words, the output of the first averaging circuit 3 gives the amplitude A of the signal point when there is no noise. Therefore, the amplitude A is given by the above equation (2). Further, the signal power S is obtained at the output of the first square operation circuit 4. On the other hand, the output of the A/D converter 1 is subjected to squaring operation in a second squaring operation circuit 5, and then
Similar to the first averaging circuit 3, the averaging circuit 6 calculates an average over sufficiently long N symbols (an integer where N>0). As a result, the above formula (5)
Since the first term of is obtained, the output value of the first square operation circuit 4 is subtracted from the output value of the second averaging circuit 6 in the subtraction circuit 7, and the noise power shown by the above equation (5) is obtained. σ 2 can be obtained. In this way, the C/N conversion circuit 8 can take the ratio of the output of the first square operation circuit (signal power S) and the output of the subtraction circuit 7 (noise power σ 2 ), and the measured C/N can be obtained. Note that the C/N conversion circuit 8 may be configured in a simple configuration, such as by dividing the actual input value or by taking the logarithm of each input value and subtracting it. There is a method shown in FIG. 4. In FIG. 4, reference numeral 16 is a conversion table made up of ROM. Various calculated values of S/σ 2 are set in this conversion table 16, and the signal power S and noise power σ 2 are given as read addresses. The above is the principle of the C/N measuring circuit according to the present invention. When applying this circuit, there is no intersymbol interference due to distortion of the signal received on the transmission path or mismatch of the filter system, and there is no interference on the transmission path. The noise added in must be Gaussian noise. (Effects of the Invention) As explained above, according to the C/N measurement circuit of the present invention, it is possible to obtain signal power and noise power by performing digital numerical calculation on the demodulated signal, so that it is possible to obtain the signal power and the noise power. There is no need to perform complicated operations, it is possible to measure C/N during operation, and there is no need for any measuring equipment. The C/N measurement circuit of the present invention can be incorporated into or attached to a demodulator, and in either case, the C/N measurement circuit can easily and easily measure the C/N as a single demodulator.
Measurements can be taken. Furthermore, since this circuit is composed of a digital circuit, it can be expected to operate with high stability without adjustment, and can be miniaturized by LSI, among other effects.
第１図は本発明の一実施例に係るＣ／Ｎ測定回
路の構成ブロツク図、第２図は絶対値操作回路の
構成ブロツク図、第３図は平均化回路の構成ブロ
ツク図、第４図はＣ／Ｎ変換回路の構成ブロツク
図、第５図は従来のＣ／Ｎ測定回路の構成ブロツ
ク図である。
１……Ａ／Ｄ変換器、２……絶対値操作回路、
３……第１の平均化回路、４……第１の２乗操作
回路、５……第２の２乗操作回路、６……第２の
平均化回路、７……減算回路、８……Ｃ／Ｎ変換
回路、９……バンドパスフイルタ、１０……復調
器、１２……排他的論理和回路、１３……加算回
路、１４……１サンプル遅延回路、１５……割算
回路、１６……ROM（変換テーブル）。
FIG. 1 is a block diagram of a C/N measurement circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of an absolute value manipulation circuit, FIG. 3 is a block diagram of an averaging circuit, and FIG. is a block diagram of a C/N conversion circuit, and FIG. 5 is a block diagram of a conventional C/N measuring circuit. 1...A/D converter, 2...Absolute value operation circuit,
3...First averaging circuit, 4...First square operation circuit, 5...Second square operation circuit, 6...Second averaging circuit, 7...Subtraction circuit, 8... ... C/N conversion circuit, 9 ... Band pass filter, 10 ... Demodulator, 12 ... Exclusive OR circuit, 13 ... Addition circuit, 14 ... 1 sample delay circuit, 15 ... Division circuit, 16...ROM (conversion table).
Claims (1)
号を伝送するデイジタル通信システムの受信側に
おいて搬送波電力対雑音電力比（Ｃ／Ｎ）を測定
するＣ／Ｎ測定回路であつて；受信復調された復
調信号をその復調の際に再生されたシンボルクロ
ツクのタイミングで標本化し各標本値を量子化ビ
ツト数ｎからなるデイジタル時系列データへ変換
するＡ／Ｄ変換器と；前記Ａ／Ｄ変換器の出力を
受けて各デイジタル時系列データについて絶対値
操作を行う絶対値操作回路と；Ｎ（Ｎ＞０の整数）
シンボルの間における前記絶対値操作回路の出力
について平均化処理を行う第１の平均化回路と；
前記第１の平均化回路の出力を受けて２乗操作を
行う第１の２乗操作回路と；前記Ａ／Ｄ変換器の
出力を受けて各デイジタル時系列データについて
２乗操作を行う第２の２乗操作回路と；Ｎ（Ｎ＞
０の整数）シンボルの間における前記第２の２乗
操作回路の出力について平均化処理を行う第２の
平均化回路理と；前記第２の平均化回路の出力値
から前記第１の２乗操作回路の出力値を減ずる減
算回路と；前記第１の２乗操作回路および前記減
算回路の各出力を受けて前記比（Ｃ／Ｎ）を出力
するＣ／Ｎ変換回路と；を備えたことを特徴とす
るＣ／Ｎ測定回路。1 A C/N measurement circuit that measures the carrier power to noise power ratio (C/N) on the receiving side of a digital communication system that transmits a signal obtained by digitally modulating a digital signal; an A/D converter that samples at the timing of the symbol clock reproduced during demodulation and converts each sample value into digital time series data consisting of n quantized bits; an absolute value manipulation circuit that receives the data and performs absolute value manipulation on each digital time series data; and; N (an integer with N>0).
a first averaging circuit that performs averaging processing on the output of the absolute value manipulation circuit between symbols;
a first square operation circuit that receives the output of the first averaging circuit and performs a square operation; a second square operation circuit that receives the output of the A/D converter and performs a square operation on each digital time series data; and the square operation circuit; N(N>
a second averaging circuit that performs averaging processing on the output of the second square operation circuit between symbols (an integer of 0); A subtraction circuit that subtracts the output value of the operation circuit; and a C/N conversion circuit that receives each output of the first square operation circuit and the subtraction circuit and outputs the ratio (C/N). A C/N measurement circuit characterized by:
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-156044A JPH01843A (en) | 1987-06-23 | C/N measurement circuit | |
| CA000570052A CA1332450C (en) | 1987-06-23 | 1988-06-22 | Carrier-to-noise detector for digital transmission systems |
| EP92201171A EP0497433B1 (en) | 1987-06-23 | 1988-06-22 | Phase controlled demodulation system for digital communication |
| EP88305685A EP0296822B1 (en) | 1987-06-23 | 1988-06-22 | Carrier-to-noise detector for digital transmission systems |
| AU18248/88A AU594621B2 (en) | 1987-06-23 | 1988-06-22 | Carrier-to-noise detector for digital transmission systems |
| DE3854505T DE3854505T2 (en) | 1987-06-23 | 1988-06-22 | Phase-controlled demodulation device for digital communication. |
| DE3886107T DE3886107T2 (en) | 1987-06-23 | 1988-06-22 | Carrier / noise detector for digital transmission systems. |
| US07/210,653 US4835790A (en) | 1987-06-23 | 1988-06-23 | Carrier-to-noise detector for digital transmission systems |
| CA000616675A CA1333922C (en) | 1987-06-23 | 1993-07-22 | Phase controlled demodulation system for digital communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-156044A JPH01843A (en) | 1987-06-23 | C/N measurement circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPS64843A JPS64843A (en) | 1989-01-05 |
| JPH01843A JPH01843A (en) | 1989-01-05 |
| JPH0450783B2 true JPH0450783B2 (en) | 1992-08-17 |
Family
ID=
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014521090A (en) * | 2011-07-15 | 2014-08-25 | テラダイン・インコーポレーテッド | ATE for detecting signal characteristics of DUT |
| US10756829B1 (en) | 2019-12-03 | 2020-08-25 | Teradyne, Inc. | Determining error vector magnitude using cross-correlation |
| US11742970B1 (en) | 2022-07-21 | 2023-08-29 | Litepoint Corporation | Correcting error vector magnitude measurements |
| US11817913B1 (en) | 2022-05-11 | 2023-11-14 | Litepoint Corporation | Correcting error vector magnitude measurements |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014521090A (en) * | 2011-07-15 | 2014-08-25 | テラダイン・インコーポレーテッド | ATE for detecting signal characteristics of DUT |
| US10756829B1 (en) | 2019-12-03 | 2020-08-25 | Teradyne, Inc. | Determining error vector magnitude using cross-correlation |
| US11817913B1 (en) | 2022-05-11 | 2023-11-14 | Litepoint Corporation | Correcting error vector magnitude measurements |
| US11742970B1 (en) | 2022-07-21 | 2023-08-29 | Litepoint Corporation | Correcting error vector magnitude measurements |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS64843A (en) | 1989-01-05 |
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