JPH01843A - C/N measurement circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a carrier power to noise power ratio (C/' N ) is related to a C/N measurement circuit that measures C/N.

(Prior Art) In a digital communication system, in order to evaluate the performance of a demodulator or the entire transmission path including the demodulator, transmission information 1 is used as a figure of merit for the bit error rate (i3 E R) of the code decoded by the demodulator. The ratio of energy per bit to noise power density (E, , ,' N nli3 is defined), which is obtained by calculation as shown in the following equation (1).

k = standing, -L--=-----< 1) oN R Here, C/N is the carrier power to noise power ratio, B is the equivalent noise bandwidth of the demodulator, and R is the data transmission rate. , 2. - P
In the SK modulation method, it matches the symbol rate, but 4
- It is well known that in the PSK modulation method, the symbol rate is twice as high.

By the way, as is clear from equation (1), E b /
To find No, it is necessary to measure C/N. So, for example, E b / N in a satellite link.

As shown in FIG. 5, the conventional C/N measurement method for determining the The C/N is measured in the 1F band of the input to the demodulator 10. The measurement procedure is as follows: First, an unmodulated wave or a modulated wave is transmitted to the center of the band of the bandpass filter 9, and the power of the output of the bandpass filter 9 is measured to obtain C+N. Next, the output power of the band-pass filter 9 is measured by stopping the transmission of the unmodulated wave or the modulated wave, or by shifting the transmission carrier frequency so that the received signal is outside the band of the band-pass filter 9. seek. Then, C is obtained by subtracting N from C+N obtained earlier, and C/N is obtained from both.

Note that B in this case is the equivalent noise bandwidth of the bandpass filter 9. (Problems to be Solved by the Invention) However, the conventional C/N measurement method described above has the following various problems.

First, a bandpass filter whose accurate equivalent noise bandwidth is known is required for measurement, and a separate measuring device such as a power meter is required.

In addition, in C/N measurement, unmodulated waves or modulated waves are transmitted, and operations to stop or shift the frequency are performed in the IF band, so not only is the operation complicated, but C/N measurement cannot be performed during operation. Difficult to do.

The present invention was made in view of such conventional problems, and its purpose is to provide a C/N measurement circuit that can easily and accurately perform C/N measurement during operation. There is a particular thing.

(Means for Solving the Problems) In order to achieve the above object, the C,/N measuring circuit of the present invention has the following configuration.

That is, the C/N measuring circuit of the present invention measures the carrier power to noise power ratio (C/N) on the receiving side of a digital communication system that transmits a signal obtained by applying digital modulation to a digital signal.
A C/N measurement circuit that measures the received demodulated signal at the timing of a symbol clock reproduced during demodulation, and converts each sample value into a digital time series consisting of the number of quantized bits n. between an A/D converter that converts to data; an absolute value manipulation circuit that receives the output of the A/D converter and performs absolute value manipulation on each digital time series data; and N (an integer where N>O) symbols. A first step that performs averaging processing on the output of the absolute value manipulation circuit in
an averaging circuit; a first squaring operation circuit that receives the output of the first averaging circuit and performs a squaring operation; the A/D
a second square operation circuit that receives the output of the converter and performs a square operation on each digital time series data;
a second averaging circuit that performs averaging processing on the output of the second square operation circuit between symbols (an integer of 0); and a second averaging circuit that averages the output of the second square operation circuit between symbols; 2
a subtraction circuit that subtracts the output value of the multiplication operation circuit; and a C/N conversion circuit that receives each output of the first square operation circuit and the subtraction circuit and outputs the ratio (C/N). It is characterized by this.

(Function) Next, the function of the C/N measuring circuit of the present invention configured as described above will be explained.

The A/D converter samples the received demodulated signal (analog signal forming an eye pattern) at the timing of the symbol clock reproduced during demodulation, and each sample value is made up of the number of quantized bits n. Convert to digital time series data.

The output of this A/D converter indicates the amplitude value at the signal point of the demodulated signal, but the absolute value of this is first taken in the absolute value manipulation circuit and the first averaging circuit, and the sufficiently long N (n >O integer) is averaged across symbols. As a result, the noise component added to the signal is canceled out, and a signal (amplitude value) free of noise components is obtained at the output of the first averaging circuit.

Therefore, the signal power S in the absence of noise is obtained at the output of the first square operation circuit. This can be expressed as a formula as follows.

The time series data that is the output of the A/D converter is d; (i=o
, 1, 2. ..., n), if the amplitude of the signal point when there is no noise is A, the power of the demodulated signal when there is no I sound is S, and the number of symbols to be averaged is N, then A = + 1 di
l −−−−−−−・(2) S=A2
=-・-・・-111・-(3) By the way, the noise component added to the demodulated signal shows a Gaussian distribution centered on the amplitude A of the signal point when there is no noise, but the noise component The power σ is σ2−−Lyo (l d Hl
−A ) 2−−−, , −, −, (4) N; −〇, and considering equation (2), σ2 = Yusho 1d, 2−A2 ...−(5
) i-0.

That is, by squaring the output of the A/D converter in the second squaring operation f7 circuit, and further averaging processing over sufficiently long N symbols in the second averaging circuit, the equation (5) can be obtained. 1st
Since the term is obtained, the noise power σ shown in equation (5) can be obtained by subtracting the output value of the first square operation circuit from the output value of the second averaging circuit in the subtraction circuit.

As a result, in the C/N conversion circuit, the output of the first square operation circuit (signal power S) and the output of the subtraction circuit (noise power σ2
), the measured value of C/H can be obtained.

As explained above, according to the C/N measurement circuit of the present invention, signal power and noise power can be obtained by performing digital numerical calculations on the demodulated signal, so that the conventional complicated operation in the IF band is not required. The C/N measuring circuit of the present invention can be incorporated into a demodulator or can be externally attached. Therefore, in any case, C/N measurement can be easily and accurately performed using a single demodulator. Since this circuit is composed of digital circuits, highly stable operation can be expected without any adjustment.
Effects such as miniaturization by LSI integration are achieved.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a C/N measuring circuit according to an embodiment of the present invention. This C/N measurement circuit includes an A/D converter 1, an absolute value operation circuit 2, a first averaging circuit 3, a first square operation circuit 4, and a second square operation circuit 5. and the second averaging circuit 6
, a subtraction circuit 7 , and a C/N conversion circuit 8 .

The A/D converter 1 samples the demodulated signal (analog signal forming the eye pattern) at the reproduction symbol clock timing (signal point position) and samples each sample value from the quantization bit number n. Digital time series data d;(i
=o, 1, 2. -.-, n) and sends it to the absolute value manipulation circuit 2 and the second square manipulation circuit 5.

The absolute value operation circuit 2 performs an operation to obtain the absolute value 1 dil of the digital time series data d; and supplies it to the first averaging circuit 3. Specifically, the absolute value manipulation circuit 2 can be composed of an exclusive OR circuit 12 and an adder circuit 13, as shown in FIG. 2, for example. Referring to FIG. 2, the absolute value operation when n=3 will be explained. The input digital time series data d; changes from value 3 to value - as shown in Table 1.
When positive and negative values up to 4 are expressed in 3 bits, and negative numbers are expressed in 2's complement, the exclusive OR circuit 12 uses the highest order of the input digital time series data dB (i=0°1.2). When the bit (MSB) is "1", that is, when the input value is a negative value, the logical values of all three bits are inverted and applied to one input of the adder circuit 13. In addition, M.S.B.
= "1", all three bits of logical values are applied as they are to one input of the adder circuit 13. Then, in the adder circuit 13, the contents of the MSB are given to the other input, so the contents of the MSB ("
Perform the operation to add ``1'' or ``0゛). the result,
Absolute values as shown in Table 2 are obtained.

Table 1 Table 2 Next, in the first averaging circuit 3, a sufficiently long N (N>0
(an integer number) symbols, and the average value is given to the first square operation circuit 4.

Specifically, the first averaging circuit 3 includes an addition circuit 13, a one-sample delay circuit 14, and a division circuit 15, as shown in FIG. 3, for example.

The adder circuit 13 and the 1-sample delay circuit 14 are integration circuits that integrate input values between N symbols.

The division circuit 15 divides the output value of this integration circuit by the number N of symbols to obtain an average value. Note that the 1-sample delay circuit 14 is reset every N symbols.

Here, since the noise component added to the signal shows a Gaussian distribution centered on the amplitude A of the signal point in the case of no noise,
By the above measures, the noise components cancel each other out. In other words, the output of the first averaging circuit 3 gives the amplitude A of the signal point when there is no noise. Therefore, the amplitude A is expressed by the above formula (2
) is given by Further, the signal power S is obtained at the output of the first square operation circuit 4.

On the other hand, the output of the A/D converter 1 is transmitted to the second square operation circuit 5.
A squaring operation is performed in the second averaging circuit 6.
As in the first averaging circuit 3 described above, an average is taken over sufficiently long N symbols (an integer where N>O). As a result, the first term of equation (5) is obtained, so
By subtracting the output value of the first square operation circuit 4 from the output value of the second averaging circuit 6 in the subtraction circuit 7, it is possible to obtain the noise power σ2 expressed by the above equation (5).

Thus, in the C/N conversion circuit 8, the output of the first square operation circuit (signal power S) and the output of the subtraction circuit 7 (noise power σ
), and the measured C/N can be obtained. The C/N conversion circuit 8 may be configured in a simple configuration, such as by dividing the actual input value or by taking the logarithm of each input value and subtracting it. There is a method shown in FIG. 4. In FIG. 4, reference numeral 16 is a conversion table made of ROM. Various calculated values of S/σ2 are set in this conversion table 16, and the signal power S and noise power σ2 are given as read addresses.

The above is the principle of the C/N measuring circuit according to the present invention, but when applying this circuit, distortion of the signal received on the transmission path,
Or, there is no code amount interference due to mismatch in the filter system,
In addition, the noise added on the transmission path needs to be Gaussian noise.

(Effects of the Invention) As explained above, according to the C/N measurement circuit of the present invention, it is possible to obtain signal power and noise power by performing digital numerical calculation on the demodulated signal, so that it is possible to obtain the signal power and the noise power. There is no need to perform complicated operations, it is possible to measure C/N during operation, and there is no need for any measuring equipment. The C/N measurement circuit of the present invention can be incorporated into a demodulator or attached externally, and in either case, C/N measurement can be easily and accurately performed as a single demodulator. . Since this circuit is composed of digital circuits, highly stable operation can be expected without any adjustment.
Effects such as miniaturization by LSI integration are achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a C/N measuring circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of the absolute value manipulation circuit, FIG. 3 is a block diagram of the averaging circuit, and FIG. is C/
The configuration block diagram of the N2t'A circuit, Figure 5, shows the conventional C/
FIG. 2 is a configuration block diagram of an N measurement circuit. DESCRIPTION OF SYMBOLS 1... A/D converter, 2... Absolute value operation circuit, 3... First averaging circuit, 4...
...First square operation circuit, 5...Second 2
Multiplication operation circuit, 6... Second average 1hi circuit,
7... Subtraction circuit, 8... C/N conversion circuit, 9... Band pass filter, 10...
... Demodulator, 12 ... Exclusive OR circuit, 13 ... Addition circuit, 14 ...
1 sample delay circuit, 15... division circuit,
16...ROM (conversion table). Agent Patent attorney Yoshihiro Hachiman Jitomi f Niji J (tsuC/N Shisara・) Sada Robmo-me 7 Hama J Ii Tairidai / Hard I-・,-4 Non-other overnight guests I breasts Button circuit, /J---Ichika summer circuit 2 2nd ward 7th jf'-kai (1 circuit linked 1 tono sa no example 3rd figure C/N moxibustion delivery schedule 0 藺 Wei na i half 4 The C/N of the pot is shown in the figure. 5 Judgment circuit

Claims (1)

[Scope of Claims] A C/N measuring circuit that measures carrier power to noise power ratio (C/N) on the receiving side of a digital communication system that transmits a signal obtained by digitally modulating a digital signal; an A/D converter that samples the demodulated signal at the timing of a symbol clock reproduced during demodulation and converts each sample value into digital time series data having a number of quantized bits n; a first circuit that performs averaging processing on the output of the absolute value manipulation circuit between N (an integer of N>0) symbols; an averaging circuit that performs a squaring operation upon receiving the output of the first averaging circuit; a second square operation circuit that performs a multiplication operation;
a second averaging circuit that performs averaging processing on the output of the second square operation circuit between symbols (integer >0); a subtraction circuit that subtracts the output value of the operation circuit; receiving each output of the first square operation circuit and the subtraction circuit;
1. A C/N measurement circuit comprising: a C/N conversion circuit that outputs a C/N (C/N);