JPH04504489A - Distributed router for connectionless packets in connection-oriented networks - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Distributed connectionless packets in connection-oriented networks Field of router invention The present invention provides support for multiple hierarchical levels and for networks at any hierarchical level. A packet router that has multiple routers that can be distributed ), and in particular, connection-oriented networks (conn datagram ( datagraas) - related to packet routers.

Background of the invention Local Area Network (Local Area Two rks) Computer communication via LANs) generally requires connections (LANs) between communication equipment. This is done by datagram without establishing a connection in advance. It will be done. The simplicity of the protocol, no connection establishment procedure required, and This eliminates the time delay caused by establishing a connection and speeds up communication. , which is advantageous. Even in large areas, without the limitations imposed by distance , having the possibility of such connectionless datagram communication is This is desirable.

Due to economic reasons, wide area communication (Wide area COA+Municatl) is required.

n) is most advantageously provided in a shared, i.e. shared mode of delivery. . Therefore, what is desired for wide area datagram communications is actually It must be linked to the development of the work, and the means to achieve this is through public networks. It must be part of the network.

In research into wide area datagram communications, there are already two studies in the field of public networks. development exists. These two developments were developed by IEEJ Project 802. 6 (Institute of Electricaland Electr. standardized by onic EngineersProject 802.6) Tsutu Aru Metropolitan Area Network (Metr.

Pol i Tan Area Networks (MANs) and National Conslative Committee Ontelegraphy and Telef. NI (International Con5ulative Comm1tt ee on Telegraphy and Telephony) (CCIT T) Stub-Group XVI I I (Study Group XVII Broadband Service Integrated Digital Network (BroadΔb), which is being standardized by I) and Integrated 5service Digital Netwo rk) (Bl5DN). Recently published texts on these two developments Among the tributes are Earl, M, Newman, Z, L, Badrikis, and Jew.

L, Barrett (R, M, Newman, Z, L, Budrikis & J, “Kupinis X Man” (“The QPSX MAN”), IEEE Communication ns Magazine), Vol. 26. No, 4゜pp20-28.April, 1988, Chi, M., Chen, and De, Ji., Messerschmitt (T., M. , Chen and D, G, Messerschmidt) “Integrated Voice/Data Exchange” tching), IEEE Communications Magazine), Vol. 26. No, 6. pp16-26. June, 198 There are 8.

MAN is an integrated digital network, including datagram communications, typically in an area of a city. It will provide telecommunications services.

If it can also provide datagram communication, it will eventually encompass MAN. . However, it is currently considered that communication to a specific person is given by a central server. only includes connection-oriented communications as a limited service; Summary of the invention The invention disclosed in No. 22 is a datagram rule applicable to MAN and B15DN. Routing datagrams with range segments of the present invention provide a network for This network consists of at least one segment. a terminal switching means connected between the switching means and the plurality of terminals; The datagram is routed from the first router to the second router via the switching system. , and sends this datagram from the second router to the second end. multiple devices configured to process data in datagrams originating from Equipped with a router.

The invention also provides at least one segment switching means and a segment switching means. A network having a plurality of routers connected between a switching means and a plurality of terminals. Provides a way to route datagrams within the work.

In this method, datagrams are routed from a first router to a second router by means of and send this datagram from the second router to the second terminal. It involves processing data in datagrams originating from a terminal.

In known systems, a central datagram server is generally not intended for this purpose. However, according to the present invention, the distributed routine method is provided. In the method of the present invention, the datagram router routine If there is no diversity (i.e., there are only a few possible paths from the source to the destination) (when there is only one router), the datagram is directed to another suitable router, increasing diversity. In some cases, it may be directed to another suitable router. Ryoru Connect datagrams if there is a permanent circuit established between them. Establishing a circuit from one router to another in an application-oriented network It is also believed that it can be sent without any hesitation. These principles apply to connection fingers. connection instructions even if the oriented network has real physical lines. The same applies even if the private network has a virtual circuit. can.

Furthermore, routers can be grouped into multiple areas (dos+ains). , these areas can be interconnected hierarchically. Furthermore, the router is theoretically The top must be on the edges of the area, so the two ends It is recognized that it is advantageous that the edge device must have a unique orientation. has been done. The router directed from region j to region i can be called Rji. . The router is an edge device in the double-headed region j,i. That router is from area j has an input socket and an output socket to area i. Regarding router R1j This is the opposite.

For universal connectionless datagram transport, it is important to routers leaving the area must be permanently connected to routers leaving the area.

The exception is that the output of router Rjj, is not connected to the input of router R1j. be. What else is needed to enable universal connectivity is the most In all areas except those at a higher hierarchy level, There is at least one router with an output that is given directly or indirectly to the area It is to be. What is also required is that there is only one area at the highest hierarchical level. and that each area is reachable from this highest hierarchical level area. be.

The area has a high-speed packet switch or multiple input ports and output ports, and all Asynchronous transfer mode switch (ATMswi) with all ports connected to each other tch). Examples of high speed packet switches are Stingray, Fang and Varnish. “Starlight, Broadband” by Knauer, A., Huang & S. Digital switch - (Starlite, A Wideband Digit al　5w1tch').

1984, Proceedings of the World Telecommunications IEEE Conference of IEEE Conference on Global Telecom municat ions), pp5. 3. 1-5. 3. 5. Written in It is listed.

The structure and characteristics described above allow routing to be based on final destination addresses around the world. It can be done anywhere. Also, the practices used in telephone numbering To approximate convention, the address itself consists of three or four subfields (s ubf 1eld), and the address itself is hierarchical, for example, a 15-digit number. The routing process can be done quickly if subdivision into subfields. can be The task at either router is to send the datagram to the appropriate route that dictates the circuit through which the datagram should be sent so that it arrives at the router at It can also be thought of as translating the final destination address into the label. There is.

This translation consists of a candidate label (candidatelabel) and a candidate label. This is done by looking up the value of a specific logical variable associated with the complementary label; There is one label candidate associated with each subfield of the final destination address.

Determine the label that is actually applied using a simple algorithm based on the values of logical variables. be able to. This procedure for determining adaptive labels is comparable to the new algorithm. be an enemy Let's keep the translation done according to this algorithm fast. when datagrams are sent at 100 Mbit/s or more. Routing can also be done quickly.

The present invention is suitable for the case where all bits of a packet are sent consecutively and the variable Also, when a datagram is sent as a long packet, the datagram is It can be applied in any case where it is divided into

IEEE803.6 and B15DN are divided into fixed length segments. described below The detailed description of the invention provided herein is for the former case.

From segments that are forwarded like plug-ins in connection-oriented networks Reassembling the datagrams depends on memory size or speed requirements. poses a similar problem to route selection. According to the invention, a large space Converting labels from space to small space is also a problem. The present invention provides less A router in a network that routes datagrams that each have one segment. I will provide a.

This router is A first means for receiving a datagram and reading a destination address from the datagram. and, Responsive to the first means, output connection data (V a second means for determining CI0UT); third means for including the output connection data (VCI 0UT) in the datagram; Equipped with After the datagram is output from the router, the datagram is sent to the output connection data. It is routed to the network based on the data (VCI 0UT). be.

Brief description of the drawing The present invention, together with the operation and implementation of the invention shown by way of example only, is illustrated in the accompanying drawings. It will be explained in more detail.

FIG. 1 is a configuration diagram of a hierarchical network implementing the routing method of the present invention; Figure 2 shows the IEEE 802.6 standard segment format % format % − format diagram; Figure 4 shows the format of CCITT E and 164 service numbers. Figure 5A shows the outline of the router circuit. Schematic diagram; FIG. 5B shows the structure of an address/VCI conversion device implementing the label conversion principle of the present invention. Figure 6 is a configuration diagram of the reassembled message identifier determination circuit; Figure 7 is A configuration diagram of a tag server which is a part of the device in FIG. 6; FIG. 8 shows a logic circuit used for priority encoding necessary for the device of FIG. 5; FIG. 9 is a schematic diagram of the multiplexer of the device shown in FIG. 5; FIG. 10 is a flowchart of a program executed by the control device of FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the prior art, datagram routing involves one or more central It goes without saying that a server (CE tralysed 5erver) is required. It seems that The central server is a computer, and subscribers Prepare a line for the computer in advance. subscriber is on that computer sends a datagram containing instructions of the intended destination to the sends the datagram to the specified destination, again using the previously prepared line. I'll send it. The line used to send the datagram is permanently established, so , there is no delay due to the establishment of a line, and in this respect the conventional method is fast. but , all datagrams must be channeled through one processor. Therefore, conventional methods have no opportunity to perform true high-speed operation or real-time operation. It will be stolen a lot. Additionally, prior art schemes allow for mutual coupling; Limited to a limited number of subscribers.

This problem is due to the fact that service functions are distributed and the method of the present invention is It can be developed without limit to the extent that it covers the substantial part, and it is connectionless for everything. or by configuring the book to be able to make Gatorgram connections. Avoided according to the invention. The system of the present invention is established for this purpose. A connection-oriented switching network or network that carries other communications traffic. overlap with connection-oriented switching networks for

Referring to Figure 1, the entire connection routing system consists of multiple areas ( In Figure 1, the area at level zero is It is shown as a circle and is indicated by 81-85. Each level zero area is mentioned earlier. It may consist of QPSX MAN. Level 1.2.3 areas are indicated by squares. , the level 1 area is indicated by 101, 102, the level 2 area is indicated by 103, and the level 1 area is indicated by 103. The Bell 3 area is indicated at 104. This device consists of three type I routers 111.113 ．． 129, and these routers receive input from the level zero area and input from the level 1 area. Output to area. ■Type router 112.114.130 receives input from level 1 area. The level zero area is output. ■Type router 119.120.121.122. 126.128 performs input and output in level 1 area and higher level area .

Unique to the system in Figure 1 is that the level zero region does not require routing. This is the assumption. If the customer or terminal device is installed exclusively for the level zero area. Ru.

Terminals are shown as small circles, e.g. the end attached to level zero area 81. The terminal device is 91.92. There is no need to route these areas. this is, These areas either have only one terminal device or The network, standardized as IEEE802.6 MAN, supports RAM transfer. This is because it is a connectionless subnetwork like a network.

Choosing the latter reduces the number of routers required for the overall scheme and is the most advantageous of the two. It is.

The level 1 area 101 connects the output socket of the router 113 to the output socket of the level 1 area 101. All ■ type routers except router 114 and ■ type router 112.116.118.1 19.121 is shown with a fixed line connecting to the input socket.

Similarly, the input to router 114 is connected to all outputs of the type I router and the type ■ router. Continued and shown. I have extracted routers 113 and 114 for simplicity. A similar line connects each router in level 1 area 101 to all other routers. There is. This is the same for the router in the area 102.103.104, but It is not shown in FIG. 1 for clarity.

Around the edge of a region, there are N incoming routers and N outgoing routers. and two regions are connected by a pair of routers in opposite directions. Assuming that each output socket generates a unidirectional or simple circuit (s implex circuit) is (N-1), and this number is It is also the number of fixed simplex lines ending in kets. of fixed unidirectional lines in that area. The total number is 2N (N-1).

Furthermore, referring to the router 113 in the area 101 in FIG. Consider the example of a datagram that is intended to go beyond 2. This data tag The router 113 connects the RAM to another router with an input socket in area 101. data must be routed.

This routing is based on the final destination address in the datagram header. It will be carried out.

This task of implementing the principles of the invention and the execution of this task are The format and transmission of datagrams are IEEE 802.6 draft standard. IEEE 802.6 Draft 5 standard (Draft D9. (August, 1989) will be explained. data graph The program is sent in a series of fixed-length segments. The format of one segment is It is shown in FIG.

Referring to Figure 2, a row is a group of 8 bits or octets. The transfer order is from left to right and from top to bottom. First 7 octets 01- 07 is the segment header, and 44 of the remaining 46 octets are transferred. It is payloaded with data for transmission, and two octets are a segment trailer.

Datagrams can be any length up to 8000 octets, 44 octets long. transferred in segments of length. The IEEE 802.6 standard is In addition to connectionless data communication, there are two service areas, namely simultaneous connection It provides connection-oriented and asynchronous connection-oriented datagrams. Ru. These three field segments start from ladder octet 01 to segment. Share up to 05. A segment is part of a connectionless datagram Whether it is VCI (Virtual C1rcuit Identifier)) Specific value of the last 4 bits of field 71, i.e. row 0 Indicated by the first 4 bits of 4. When these 4 bits are all O, the segment The client is connectionless. In the following description, “VC1” and “Labenojiha” used with the same meaning.

If the segment is connectionless, then the segment is the beginning of the message. Are you carrying a message (BOM) or a Continuation of Message (COM)? mosquito.

Carrying an End of Message (EOM) or a separate Segment Messenger Information on whether you are carrying a SSM is a 2-bit S type field, i.e. This is indicated by the subfields in FIG.

All segments of one message have the same message identifier, (M ID) Field 76 must be carried.

One datagram begins with the SSM or 80M segment in octet 08, ISO (Internat　1onal　5standards　Organisati on) starts with a level 2 header and adds the ISO level to this ISO level 2 header. 3 headers follow. According to the principles of the invention, routing also applies to the final destination address. It's cold.

This address is in the level 3 header in both cases. IEEE 802. 6 standard, CCITT E, 164 final destination address is Level 2 It can also be located in the header, and routing should be based on this header. Can be done. In the following description, it is assumed that the latter applies. in a certain situation If the level 2 header does not carry a final destination address, the level 3 header Most of the things listed here have not changed, even if you are looking for a destination in the list below. It will be held on.

Figure 3 shows the level 2 header format according to the IEEE 802.6 standard. Showing mat. Immediately relevant destination address (DA) field 1 There are 7 fields with only 42 fields. The first of the 4 bits to be formatted It consists of a subfield and a 60-bit address subfield. address is CCITT E, 164, all 60 bit positions are It is occupied by the 15 binary coded decimal digits of that address. This format is It is shown in FIG.

Our Connectionless Routine Button and Principles for Performing This Task can be understood by referring to FIG. 5A, which is a block diagram of the router. le The controller inputs serial segments in continuous time having the format shown in Figure 2. input 520 and modify those segments in an appropriate manner to serially on output line 538. Input and output are continuous during use and the transmission rate of the network is constant.

For example, if the transmission speed is 44.210 Mb i t/s, this transmission speed is One of the standard internet speeds for public network digital transport in North America. It is planned to be used in the DQDB network of The force velocity is 104.269 segments/sec. The architecture in Figure 5A and A router having components of the present invention can achieve a speed of 104.269 segments/second or more, e.g. , 140Mbit/s and 155Mbit/s, which have recently been considered for DQDB networks. bit/s is possible.

Each bit or group of bits, e.g. 8-bit group or octet Input and output can be serial, which changes the principle of the invention. It's not something you can do.

A router consists of identifiable standard components. That is, latches 503, 504, de Multiplexer-506, 507, 508, Multiplexer-509, 510, 512, 513, and delay circuits 541, 542, 543, and 544. router incorporates two systems of the present invention. That is, address-VCI (addr ess to VCT) h Lancer 501 and Bucket Assembler/Ra. This is a bell server 502. All components and operating tags in this system The timing is controlled by a timing controller 505. Controller 505 itself handles bits or bit groups and segmentation at the input. synchronized with the start of the event.

The latch 503 has a field 75 in the format of FIG. 2 indicating the segment type. Capture a certain S TYPE. The contents of latch 503 are demultiplexed. gives instructions to the server 506, system 501, 502, multiplexer 513 . Segment is a single segment message (SSM) or the beginning of a message (BOM), demultiplexer 506 sends the segment to line 52 Put it out on 1st. The segment is a continuation of a message (COM) or an end of a message (COM). EOM), the segment is placed on line 522. The delay circuit 541 segment, taking into account the contents of the latch as to which way the force should be switched. The segment is delayed sufficiently until the decision is made, so that the first bit of Segments that leave the router have the same bit fields as they entered. field 71.76 in Figure 2. D is an exception. The other exception is two cyclic redundant frames that are recalculated and changed. This is a cyclic redundancy field. child These are not done within the router, but on another unit following the router. be exposed. However, that functionality can be incorporated into router systems without modifying the invention. It can also be absorbed.

Segments leaving the router immediately receive the appropriate VCI and MI to go to their next destination. Must have D. VCI is an ATM switch, for example 1 in FIG. 01 or 103, segments from a given input socket to the intended output socket. This is the label used to forward the message. MDI is the division of a certain message. It is a label that logically connects segments that have been Regardless of whether segments of different messages are parallel or interleaved. must be different for different messages.

The appropriate VCI is the final destination address or subscriber number, 91 in Figure 1 or is determined from 97, and the final destination address or subscriber number is the header of the message. field 77 of the SSM and BOM. last line The destination is latched by the latch 504 from the incoming SSM and BOM, and the address /MCI translator (address to VCT TRANSLAT R) 501 via line 527 to address/MCI translator 501 determines the appropriate VCI and places this appropriate value C1 on line 528. S.S. M or BOM is demultiplexed in demultiplexer 508. , the demultiplexer 508 is used when the SSM or BOM is received. VCI and M ID on line 525, and the remaining fields on line 526. Put it out.

For BOM, Rai: /324 (7) VCI IN and M I Reassembler/Ra Loaded into the bell server 502, message reassembler/label server 502 recognizes the message continuation<COM and EOM, and COM and D are delay circuits. 543 to the multiplexer 512, and the multiplexer 512 Issued by the remaining twill sage reassembler/label server 502. Ru.

For SSM, the M ID is an empty field (null fi eld) and links the first segment with any following segment. Never. Please connect VCI 1N5M ID IN and MCI OUT. There is no need to store the message in the page reassembler/label server 502. The reassembler/label server 502 is suitable for SSM (empty). 1) Output M ID OUT. Therefore, SSM OUT is the same as BOM OUT. is formed by the same multiplexing and also appears on line 536.

COM and EOM are similarly demultiplexed by demultiplexer 507. demultiplexer 507 transfers the incoming VCI and MID to line 5. 24 and the remaining fields on line 523, VCI IN and M ID. The IN is input to the message reassembler/label server 502, and the message The Sage reassembler/label server 502 is a The output of multiplexer 510 is the remaining field of the segment. Multiplexed with COM RIN or EOM RIN in Xer-511 , multiplexer 511 outputs the obtained segment 5. Finally, the multiplexer -513 selects the one with 5 lines cut.

Demultiplexing and multiplexing are shown in Figure 5A along the progression stages. It is. This is for illustrative purposes only. In actual implementation, demultiplexing All demultiplexing of lexers 506, 507, 508 is done by one demultiplexing This is done more efficiently within the multiplexer, and the multiplexers 509-513 All multiplexing is done within one multiplexer. Also, theory Only for Ming BOM RIN and SSM RIN is COM RIN and EOM R It is shown separately from IN. In actual practice, they are not differentiated and are common. put out on line. Therefore, the two delay circuits 542 and 543 are one delay circuit. be.

The delay circuits 542, 543, 544 delay the different elements of the output segment. Important for proper temporal alignment. Delay circuits 542 and 543 are common. 1 if not, the delays of delay circuits 542 and 543 must be equal to each other, When generating VCI OUT and M ID OUT, the address/vCI trans Large delay between slater 501 and packet reassembler label server 502 must be equal to

A larger delay occurred in the packet reassembler label server 502. In this case, delay circuit 544 is inserted in line 528 as a trimming delay circuit. to delay VCI OUT from being output from the address/vCI translator 501. equal to the delay from the message reassembler label server 502. Multibrex. Address/VCI translator 501 has a larger If a delay occurs, the trimming delay circuit will This applies to VCI OUT and M ID OUT from the bell server 502.

Segments may enter the router one after another without any time interval, and consecutive segments The component can be of any of the following four types: BOM, SSM, COM, and EOM. may be of type , so the address / having the architecture of Figure 5A VC! ) Lancer 501 and message reassembler label server 50 The task performed by 2 must be accomplished in one segment period.

Incidentally, this means the following. That is, the delay of delay circuits 542 and 543 is maximum More importantly, the address/VC! ) The translator 501 and the message φ reassembler/label server 502 are This means performing each task within a limited amount of time.

The job of the address/vCI translator is to This can be accomplished within a short amount of time if possible by backup. Each can be sent Keep the appropriate VCI in memory for the possible destination addresses. but ,Currently, this is not possible due to the size of the address space. Going While the destination address is 60 bits, the destination address that may be sent is This is because the number is 260 or 1018.

How to enable address/VCI translation using memory lookup was developed and is called simultaneous partitioned memory lookup. sub the entire address Divide into fields, each subfield with a corresponding memory size of practicable This is a way to make it small and accessible.

Reference is made to FIG. 5B, which shows a block diagram of system 501 of FIG. 5A. line 5 The destination address DADDR of 22 is on line 211.2141. ,,． 216 ( n+1) Field, field 0, field 1, field n has a hoax Multiplexed. These fields are stored in random access memory 22L. 222,.

, , 225, 226.

Candidate vcI (candidate VCT) is read from each memory. It will be done. Also, what is read from each memory is a logical variable, i.e. IO on line 243. , 11161 is read out on line 244, and In is read out on line 246. Candidate VC I is the input to multiplexer MUX 270 and the logic input to logic device 250. It is a variable. The overall selection to logical unit line 260 allows this VCI to This becomes the VCI OUT of the lexer output line 528.

VCIs and logical variables stored in and retrieved from memory are address specific. , and the specific interconnections between the hierarchical regions created. writing to memory These tasks are performed by the network management device. In the explanation that follows , VCI selection is based on the fact that address partitioning (PARTIONrNG) is strictly hierarchical. Yes, and furthermore, the division corresponds strictly to the hierarchical division into areas. . Next, a logical variable must be directed to at least some level of routing. It is just a single binary pit binary digit that indicates whether the control device or priority encoder (priority encoder) 25 By priority encoding (priority eneodjng) with 0 executed.

The task of priority encoding is known and follows the functionality of the priority encoder. It can be understood from a mathematical explanation.

Let Ik, k-0, 1, , , n be binary value inputs to the priority encoder, and XI , j-0, , , m are the binary value outputs from the priority encoder. Overall, The output is obtained as a binary coded decimal positive integer y, and the binary coded decimal positive integer y is The largest possible value of y is at least equal to n.

It becomes equal when m > log2 (n+1) (2).

The output of the encoder is J=z+1. --for rn Iz-1 and Ij-0 (3) The value y=z only if .

The truth table of the priority encoder in the case of n-7 and therefore m-3 is shown in Table 1.

TABLE Z Engineering NP (JTS 0tJTPtJT5 0tJTPtJTALUE Engineering O”1 “2” I3 Engineering 4 “5 Engineering 6 I7 I2 “l”OYloooo ooooooooo xlOOOOOOOOll XX100OOOO102 xxx 1 00000 1 13 x　X　x　x　z　OOOOI　O’ 0　4XXXXXX1001015 XXXXXXXIO1106 XXXXXXXllll17 An implementation of the priority encoder is shown in FIG. Logical variable It~■7 is placed on line 285 via line 291. Negation of a logical variable ton or inverse, for example, negato r) or the negation of I2 by inverter 292 can be achieved by different combinations as shown. and output to OR gates 300-304.

The output of the OR gate is a certain combination of II or the negation of I. It is output to AND gates 305, 306, and 307 along with the AND gate 30. 5,306.307 is X as output. +Xl and I2 are generated and line 308.3 Output to 09 and 310 respectively. I.

is not an input to the priority encoder. That's because I. -1 corresponding output x O-IO1x, -〇, x2■0 is! , -I, are all zero, the default is This is because it is generated by the priority encoder.

Label selection is performed by multiplexer 270 in FIG. 5B. Figure 9 shows Realized a simple multiplexer that selects one item from 46 bit labels. show something In this case there are only two X elements, Xo and xl. child These are provided to decoder 410.

Depending on the values of Xo and xl, one particular output line 421.422.423.4 24 is selected. The truth table for decoder 410 is shown in Table II. these The line is tri-state buffer y (Tri-state buffer) 44 Connected to enable power at 0.441.442.443.

The power to the tristate buffer is VCI tl, respectively.

Depending on whether the buffer is selected, its label will appear at the output of its tristate buffer. and output to output bus 528.

TABLE XX VALtJE! NPU? (bits) Yxl) C□ (h bits) 0 0 0 LABER, 0 1 0 1 LABELI 21　0　LABEL2 311LABl:L3 The task of the message assembler/label server 502 in FIG. 5A is one segment. It must still be accomplished in a shorter period than the , still requires a memory lookup. Memory lookup address space The base is a combination of a 34-bit VCI and an MID, and the required access The number of address locations is 2X10''. Therefore, this is also impractical. .

A two-step memory lookup has been developed to enable this, and its implementation An example will be explained with reference to Figure 6. -3318 is Ba’:;1.3221. :　k　　　　:’　”/t’s VCI TAG and generates a 1-bit M ID TAG on the bus 324. These two The busses are combined to (k+1) pins to accommodate the required memory of these four servers. memory size is exponentially related to the number of input bits and linearly related to the number of output bits. do. The total number of bits stored in these four memories is 2" + 12" + n2 (k + 111 memory lookups are used for N + -) If the number of bits stored in that memory is N2 = (m+n)2(-+1' (5).

If (k+1) is a much smaller number than (m + n), then N 1 is much smaller than N2. For example, m is equal to 20, n is equal to 14, If k and 1 are both equal to 8, then N1 is approximately 11.000.000 and one On the other hand, N2 exceeds 5×10” or 500.000.000.000.

The four VCI TAG servers 317, 318, 325. 326 are all the same circuit, but the numerical size of the memory (nua+erical 5ize) and the line, which can be understood from FIG.

396 is the VCI TAG322. in FIG. M ID IN TAG323. VC I0UT327. M represents each of ID0UT328.

Please refer to FIG. The key 350 is used to select an address for the count RAM 340. bus 356 as an address selection to label RAM 365. given to. This allows you to read and write data stored in a specified memory location. It becomes possible to enter. The count value 347 from the count RAM 340 is the counter The label value 389 from the label RAM 365 is read into the tag label 395. Writing to count RAM and label RAM, Counter 346, latch 395 and tag FIFO (TAG-FIFO) The operation of 380 is controlled by controller 385.

Controller 385 receives segmented instructions or bus 397. Also, The controller 385 transfers the tag value read from the label RAM 365 to the bus 390. receive, the latest count value generated by counter 346 is received on bus 348; Take it. The controller 385 also inputs an externally generated label to the bus 3. You can also pick it up at 99.

If appropriate, controller 385 issues the next command. That is, (i) Write command to counter RAM 340 to HELINE 341, (i) To counter 346, load command to line 342 and increase command to line 342. At input 343, a decrease command is sent to line 344, an erase command is sent to line 345, (i i) To tag FIFO, read command to line 370, write command to Line 391, tag out to bus 372, (iv) Write command to label RAM 365 on line 360, all zeros data words on bus 366, and (V) To tag latch, erase command to line 271, load command to line 394 Put it out.

If appropriate, controller 385 also sends an error code to bus 386. Issue a new output instruction to in387.

The controller is a microprogram processor with various specific embodiments. - is fine. The processor is an ESP448 or multiple ESPs connected in parallel in cascade. Consists of the following. The functionality of the processor is described in the following pseudocode (Pascal language and (somewhat similar to the C language) can be done. The program list is shown below.

repeat (CONTROL LOOP) rep@at (do nothing ing) until n@w-1nput; (SYNCHRON Engineering ZAτ Engineering ON ON)’ clear (new-1nput); (LINE 398 )load (counter); case sagment-type ofBOM: begin if ((countarmo) and (tag@0)) read (tag- fi, fo, data); write@(label-ram, data) ;increment(countar);Writ@(Countar- ram, Counter); 1oad (tag-1atch) and @lse 1f ((count@r00) and (tag<>0)) 1, n cramant(countar);wrizo*(countar-ram, counter) rload (tag-1atch): and els@begin @rror cod@:ml; clear(tag-1atch); end; COM: begin if ((count@r00) and (tagc>0)) then beg in arrow code:so; 1oad(tag-1atch); and alse bagin error c ro de knee 2; clear(tag-1atch);'and; and; EOM: begin lf((counterc>O) and (tag<)O)) than b@ group g 1oad(tag-1atch); dacr@mant(counter); wri t@(counter-ra m, count@r);1f(counter-0) then begin write(tag-fifo, tag); write(labai-r am, O); arrow code: so; View d; and clear(tag-1atch); and= and; (END-OF CASE) pulse (new-output) ;until forever; Program flow diagrams are shown in Figures 10A-10D.

Operation of tag server (tag5erver) and tag server controller The operation of 385 is as follows for the VCI tag server, i.e., server 317 in FIG. This will be explained in more detail with reference to FIG. In this case, bus 355 and The key 350 appearing at 356 is carried and entered in the header of the current segment. This is VCI. If the segment is COM (continuation of message), The label read from the label RAM 365 is non-zero (n.

n-zero) and previously stored for that segment. cow The count reading from the component RAM 340 is also non-zero. controller is read Check if the label and count are non-zero. If either or both are zero means an error condition and the controller generates an error code on bus 3,86. and if the error state segment is a BOM (beginning of message) , the VCI TAG for that segment may or may not be present. a certain place If so, the read count and label are non-zero. In this case, the controller latches the VCI TAG in tag latch 395 as before. Also, control The roller issues an increment command on line 343, and this increment command command increments the count of counter 346 by one. Following this , the controller issues a write command on line 341 to read the latest count. It is latched in tab 395. The count is also incremented to 1 and the counter is written into the client RAM 340 as before.

When the ROM arrives and it is necessary to give the tag, the TAG FIFO 380 If empty, no tag is given. This is an error and the message will be lost. This results in The numerical size of the TAG space ignores the possibility of tags being lost. can be selected so that the probability of

Finally, when the segment is EOM (end of message), the label - RAM The conditions and operation for reading H.365 are the same as for COM. However, the tag is may be returned to the pool. Controller is decrement command is sent to counter 346 and line 344. As a result, the count is decremented by 1. and the latest count is written to the count RAM 340. Obtained If the counted count is zero, the tag is free. The tag is inserted into the tag latch 395. and also by the write command on line 391. It is also written to TAG FIFO 380. Following this, all zero tags are The write command on line 360 causes the bar to be sent to bus 366 by the controller. H.326 differs from the other two servers in the following points.

limited by the number of spaces, not by the size of the space. It is a point. The label is sent from an external sender via the label on bus 399 to the label on bus 37. The key through 2 is for a particular datagram, and the count follows the ROM. is for a specific key and returns to zero following EOM. In this way, counter The function of the RAM 340 is nil, and may be omitted in this case.

The VCI OUT server differs from the MID OUT server only in the following points: Ru. That is, This is determined by the system shown in FIG. 5 when the BOM is received.

When the EOM arrives, the VCI address location is zeroed again via bus 366. be done.

Although three types of routers have been described: types I, II, and H, a comprehensive implementation is possible. It will be recognized that it is possible.

Comprehensive by appropriately modifying the executable program in the controller It is possible to change a router from one type to another.

It is also recognized that the same function can be achieved by changing the elements of the overall device shown in Figure 1. There will be. The connecsiginless zero level area connects the terminal equipment directly to the router. i.e., by connecting a pair of routers to each separate terminal device. I already mentioned that you can do this, but to do it this way you need substantially more This is undesirable in that it requires a router. The zero level area acts as a concentrator. , one router can serve many terminal devices, and communication within the area is possible. Provide connectionless exchange services for

If all connectionless messages are sent to one router, the concentrator function is a connection indicator with simplified routing capabilities from a separate terminal device. It can also be performed by a directed area. In this case, the router approximating a server.

The connection-oriented concentrator itself does not perform connectionless intra-area communication. router functionality to provide connectionless intra-area communication. Potential cannot be realized unless it is expanded to a certain extent.

The specific context of network standards and specific embodiments of the invention within that context are shown and described here for illustrative purposes only. skilled in the art If you are Although not specifically shown or mentioned herein, Other systems implementing the principles described above and not departing from the spirit and scope of the principles described above. It would be possible to devise a For example, the system described above uses It is related to segment transfer, but if some elements are not used, segment transfer will not be possible. This can also be applied to transfers that do not involve data transfer. Also, for example, random access Mori, multiplexer, priority encoder.

FIFO memory etc. are mentioned above, but these are more basic or similar. can be replaced by specially constructed elements that perform similar functions.

Chapter 3 Special Table Sen4-504489 (17) international search report Umu0FAI Toko

Claims (1)

[Claims] 1. A net that routes datagrams with at least one segment In the network, the network has at least one segment switching system. a plurality of routers connected between the segment switching system (101,..., 104) and the plurality of terminals (91,..., 98); (111,...,130), processes the data of the datagram originating from the first terminal (91) and transfers this datagram to the first route. The segment switching system is transferred from the router (111) to the second router (118). a plurality of routers (111 . ．． ．． , 130). 2. Multiple segment switches to correspond to each hierarchical segment transfer level a first level segment switching system (101, 102) is connected to the terminal and a second level segment switching system (103); 2nd race Bell's segment switching system (103) comprises at least one of said first levels; Both are connected to two segment switching systems (101, 102). The network according to claim 1. 3. 3. The network of claim 2, wherein one segment switching system 101 of the first level is connected to another segment switching system of the first level. 4. The segment switching system (101, 103) The segment switching system (103, 104) at the Except for the segment switching system (104), which also has a high segment transfer level. 4. The network according to claim 3, wherein all of the networks are connected. 5. A network according to any preceding claim, wherein datagrams are forwarded through the network based on the address of their final destination. 6. The terminal is connected to the segment by the router (111,...,130). at least one area network means (81,..., 85) connected to a switching system (101,..., 104). The network according to any one of the preceding claims, wherein both of the networks are made into one group. 7. The router (111,..., 130) receives the datagram and has first means (503, 504, 505, 506, 507, 541) for accessing the final destination address from the datagram; In response to said first means, an output connection is configured based on said final destination address. second means (501) for determining the connection data (VCI OUT); a third means (50 2, 505, 508, 509, 511, 512, 513, 540, 542, 54 4, 543) for including action data (VCI OUT) in the datagram; After being output from the router, the output connection data 6. The VCI OUT is routed to the network based on the VCI OUT. network. 8. The second means (501) includes a memory circuit in which output connection data (VCI OUT) and selection data are stored. Divide the route (221,...,226) and the final destination address into fields, and save these fields in the memo. each of the recircuits (221,..., 226) to connect multiple corresponding a fourth means (201) for accessing connection data and selection data; and a fifth means for selecting output connection data (VCI-〇UT) from the plurality of corresponding connection data based on the selection data. 8. The network according to claim 7, comprising: 9. The selected data corresponds to a priority code such that the selected data is selected based on a priority corresponding to the hierarchical segment transfer level. 9. The network according to claim 8. 10. The third means (502, 505, 508, 509, 511, 512, 51 3, 540, 542, 544, 543) is configured to access from at least one segment. the at least one segment of the datagram based on accessed input connection data (VCI-IN) and input message data (MID-IN); Message hand that determines the output message data (MID-OUT) for the component. a stage (502), said third means (502, 505, 508, 509, 511, 512, 513, 540, 542, 544, 543) for said output in said at least one segment; the at least one segment having power message data (MID-OUT); 10. The method according to claim 7, 8 and 9, wherein the output message data (MID-OUT) indicates, upon output from the router, that the message belongs to the datagram. network mentioned in the above. 11. further determining the output connection data (VCI OUT) for subsequent segments of the datagram after the first segment of the datagram is processed by the router; The third means is determined based on the input connection data (VCI-IN) and the input message data (M-ID-IN), and the third means is (502, 505, 508, 509, 511, 512, 513, 540). , 542, 544, 543) is a request having the output connection data (VCI OUT) in the following segment. The network according to claim 10. 12. Said message means (502) comprises at least two tag serving means (317, 318), each of said tag serving means connected to said input connection. connection data (VCI-IN) and the input message data (M-ID-IN) to output a connection tag and a message tag, respectively, and the output connection data (VCI OUT) is accessed based on the tag. 12. The network of claim 11, wherein: 13. In response to the connection tag and the message tag, the output connection The tag serving means outputs the application data (VCI OUT) and the output message data (M-ID-OUT), and the three tag serving means The stages (317, 318, 325, 326) include an available tag storage means (380) for storing available tags, a memory (365) for storing a current tag for a datagram, and a memory for storing a current tag for a datagram when said current tag is no longer needed. Na 13. The network of claim 12, further comprising means (340, 346, 385) for determining when to return the current tag to the tag storage means. 14. A network according to any of the preceding claims, wherein the router processes the datagrams in real time. 15. A network that routes datagrams with at least one segment. At a router in the network, the router receives a datagram and accesses the final destination address from the datagram. first means (503, 504, 505, 506, 507, 541) for determining output connection data (VCI OUT) based on the final destination address in response to the first means; 2 means (501) and said output connector. and third means (502, 505, 508, 509, 511, 512, 513, 540, 542, 544, 543) for including version data (VCI OUT) in the datagram, the datagram being output from the router. After the output connection data is A router that is routed to the network based on the VCI OUT. 16. The second means (501) includes a memory circuit in which output connection data (VCI OUT) and selection data are stored. Divide the route (221,...,226) and the final destination address into fields, and save these fields in the memo. to each of the recircuits (221, . . . 226) to a fourth means (201) for accessing connection data and selection data; and a fifth means for selecting output connection data (VCI OUT) from the plurality of corresponding connection data based on the selection data. The router according to item 15. 17. The selected data is selected based on the priority corresponding to the hierarchical segment transfer level. 17. The selection data corresponds to a priority code such that the data is selected. network. 18. The third means (502, 505, 508, 509, 511, 512, 51 3, 540, 542, 544, 543) is configured to access from at least one segment. the at least one segment of the datagram based on accessed input connection data (VCI IN) and input message data (M ID IN); Message that determines the output message data (M ID OUT) for the said third means (502, 505, 508, 509, 511, 512, 513, 540, 542, 544, 543), wherein said at least one segment said output message indicating that it belongs to said datagram upon output from said datagram. The router according to any one of claims 15, 16, and 17, having message data (M ID OUT). 19. Further determining the output connection data (VCI OUT) for subsequent segments of the datagram after the first segment of the datagram has been processed by the router, and the output connection data (VCI OUT) is equal to the input connection data (VCI IN). ) and the input message data (MID IN), and the third means (502, 505, 508, 5 09, 511, 512, 513, 540, 542, 544, 543) Router according to claim 18, comprising the output connection data (VCI OUT) in a segment. 20. Said message means (502) comprises at least two tag serving means (317, 318), each of said tag serving means connected to said input connection. accessed by the connection data (VCI IN) and the input message data (M ID IN) to output a connection tag and a message tag, respectively, and the output connection data (VCI OUT) is determined based on the tags. The network according to claim 19. 21. In response to the connection tag and the message tag, the output connection The tag serving means outputs the application data (VCI OUT) and the output message data (M ID OUT), and the three tag serving means The stages (317, 318, 325, 326) include an available tag storage means (380) for storing available tags, a memory (365) for storing a current tag for a datagram, and a memory for storing a current tag for a datagram when said current tag is no longer needed. Na 21. The network of claim 20, further comprising means (340, 346, 385) for determining when to return the current tag to the tag storage means. 22. 22. A network according to any of claims 15 to 21, wherein the router processes the datagrams in real time. 23. at least one segment switching system (101,..., 104) and between this segment switching system (101,..., 104) and the plurality of terminals (91,..., 98). Multiple connected routes routers (111,...,130) In this method, the datagram data transmitted from the first terminal (91) is processing the datagram to pass the datagram from the first router (111) to the second router (118) via the segment switching system (101,...,104); 2 router (118) to the second terminal. How to route a datagram consisting of. 24. Advances the datagram based on the address of its final destination. 24. The datagram module of claim 23, comprising: transmitting the datagram over the network. coaching method. 25. accessing the final destination address from the datagram; determining output connection data (VCI OUT) based on the final destination address; OUT) and when the datagram is output from the router. Based on the output connection data (VCI OUT), the network 25. The datagram of claim 24, further comprising ruching the datagram within a network. How to route datagrams. 26. By dividing the final destination address into fields, and by dividing these fields, accessing a plurality of corresponding connection data and selection data by applying a field to each memory circuit storing the connection data and selection data, and accessing the plurality of connection data based on the selection data. 26. The method of claim 25, further comprising selecting output connection data from the data. 27. The selection data corresponds to a priority code such that the connection data is selected based on a priority that corresponds to a hierarchical segment transfer level. 27. A device according to any of claims 25 and 26, wherein the segment forwarding level comprises respective segment switching systems (101,..., 104) connected by said routers (111,..., 130). How to route datagrams. 28. accessing input connection data (VCI IN) and input message data (M ID IN) from said at least one segment; and also accessing said input connection data (VCI IN) and said input message data (M ID IN). determining output message data (M ID OUT); and including the output message data (M ID OUT) in the at least one segment, the at least one segment including the data. Claims 25, 26, and 27, wherein the output message data (M ID OUT) indicates that the message belongs to a program when output from the router. How to route datagrams as described in either. 29. After processing the first segment of the datagram, the input connection data Based on the data (VCI 1N) and the input message data (M ID IN) determining the output connection data (VCI OUT) for subsequent segments of the datagram; 29. The method of claim 28, further comprising including the datagram in a message. 30. The input connection data (VCI IN) and the input message data accessing the connection tag and the message tag from the tag serving means (317, 318) respectively based on the connection tag (M ID IN); determining the output message (MID OUT) and the output connection data (VCI OUT) based on the connection tag and the message tag; 30. The method of routing datagrams of claim 29, further comprising: 31. obtaining the output message (MID OUT) and the output connection data (VCI OUT) from a tag servicing means (325, 326) further provided based on the connection tag and the message tag; Furthermore, the tag serving means (317, 318, 325, 326) an available tag is stored in a tag storage means, a current tag for a datagram is stored in memory, and the current tag is updated when the datagram passes through the router. 31. Routing datagrams according to claim 30, wherein said datagrams are routed back to said tag storage means. How to do it. 32. 33. A method according to claim 23, wherein the steps of the method are performed in real time.