JPH04503287A - Digital-to-analog converter with onboard unit gain inverting amplifier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Onboard-in - Iji Rua Log comparator - Mitsuno Ojide The present invention relates to digital-to-analog converters. More specifically, the present invention has analog ground current cancellation and supports both unipolar and bipolar models. 4-quadrant digital-to-analog converter that can operate at .

willpower street Many of today's digital-to-analog converters (DACs) are of the R-2R type. It is configured. Figure 1 shows a simplified version of a conventional 8-bit R-2R ladder DAC. It is a circuit diagram. Switches S1 through S8 are 8-bit digital inputs to the DAC. A FET switch controlled by a word. In that digital word Each bit position controls a respective switch, controlling a respective leg of the circuit. (i.e., the resistor 2R above the switch), if the corresponding focus is 0, the analog connection 12, and if the corresponding bit is 1, the summation junction (Sums+ing jun ction). Sl is determined by the most significant bit of the digital word. Each subsequent switch is controlled by the next higher level focus. addition Connection point 14 is held at virtual ground by output sofa amplifier 16. R and By placing a resistor with an impedance of 2R, the current in each leg is The current is half of the current of the next most significant bit. However, astragalus (leg) 9 Since there is no resistor R in series with resistor 2R, the currents in legs 8 and 9 will be equal.

The input voltage Vref to the R-2R ladder is the reference voltage that supplies current to the ladder. be. With the R-2R arrangement, the input current I is connected to the switch 5l-38 and the digital According to the file input word, it is divided into an analog ground 12 and a summing junction 14. Ba Buffer amplifier 16 converts the current at summing node 14 to a voltage Vout. That V out becomes the analog output voltage corresponding to the digital input word.

For example, if the digital input word is 1ootooto, legs 1.4 and 7 The current flowing through leg 2. is directed to summing node 14 and leg 2. 3. 5. 6 and 8 The current flowing through will be sent to analog ground 12. Current flowing through leg 1 If is lm5b, the current at the addition connection point 14 is lm5b + 1/8 lm5b +1/128msb. Remaining current 1/21m5b +1/4 1+ssb +1/161m5b +1/321m5b +1/128 lm5b is analog ground. Buffer amplifier 16 converts the current at summing node 14 to Vout. Convert to voltage. The buffer amplifier 16 is an inverting amplifier. amplifier), so when Vref is a positive voltage, Vout is becomes a negative voltage. To obtain a positive output voltage, the Vout signal must be It will be reversed in the latter part of the theory.

The R-2R ladder (R2R1 adder) shown in Figure 1 is in uni-polar mode. It is configured to operate only in That is, its output is the supplied V This is the only possible positive electrode of ref. Four quadrant operation (four quadrant op) generation), i.e. using offset binary or two complementary codes. Accepts positive or negative analog output voltages in response to positive or negative digital input words In order to Added to 14. This ensures that the full scale range of the DAC is offset by 172. A voltage is generated at Vout so that the voltage is turned off. So, if you go to unipolar mode If Vout has a range of 0 to 5 volts, then Vout is bipolar • Will have a full scale range of ±2.5 volts in mode. off The set reference current may be provided by a separate offset reference. more general In order to minimize the output zero drift with temperature, it is necessary to adjust the DAC's base Vref to minimize the output zero drift with temperature. derived from the signal.

If the analog ground found in the R-2R ladder, i.e. analog ground 1 2 is found on associated circuit elements (i.e. chip ground bin connector) If it drifts from true ground (i.e., effectively ground), the error is DA is introduced into the analog output of C. Ideally, from the switch terminal to ground. The leading conductor and ground wire themselves are perfect conductors and offer no electrical resistance to the circuit. do not have. Unfortunately, however, the DAC conductor adds a small but non-negligible resistance to the circuit. I can do it. This resistor creates a voltage at the switch terminals with some offset from true ground. drifts to the ground value, so the offset operation is additive with analog ground 12. Current flows through both nodes 14 and produces an inaccurate reading. It is called , the lowest focus (as determined by Vref and the number of resolution focuses) ) with an amplitude of approximately 172 or more Unfortunately, 1/2 Errors larger than the least significant bit (Isb) can easily accumulate, especially when the DAC is This is especially true for monolithic chips that perform multiple functions. To Chi Nobu like this conductor between the bin and the DAC's actual switch connected to analog ground. The total value of the resistor is quite important and especially troublesome in higher precision DACs. It is.

For example, a 12 pino (12 pin) DAC with a reference voltage of 10 ports will have a minimum voltage of 2.5 mV. will have a bit value. Analog of 1.25mV (1/21sb) or more - Ground drift will cause errors in the analog output of the DAC.

If the ground wire presents a resistance of 1 ohm to the circuit, then this Peak level 1, 25mA analog ground current is 1.25mV unacceptable will result in analog ground drift.

Another error introduced in prior art DACs to their analog output is that The FET switch used in the R-2R ladder, as well as the additional FET switch (this These additional FET switches select unipolar or panpolar operation. included for the purpose of selecting the full scale range of the DAC. This is due to the temperature dependence of Those FETs The resistance shown in that circuit of the switch will drift with temperature, thereby causing its The log output will also drift with temperature. Those FET switches The amount by which a resistor drifts with temperature is determined by the "temperature coefficient (TC)" of the switch. It is something that

Therefore, it is an object of the present invention to To provide a monolithic D-A converter that is substantially immune to lift. It is.

Another object of the invention is to substantially reduce the effect of analog ground current on the output analog voltage. It is an object of the present invention to provide a simple monolithic D-A converter.

Yet another object of the invention is to Monolithic D-to-A converter that can be selectively programmed to operate in either The goal is to provide the following.

In addition, another object of the invention is to provide an improved monolithic D-to-A converter. Is Rukoto.

Two places Ω agreement The present invention provides a monolithic and resistive ladder. r) type D-A converter has 4-quadrant operation, analog ground current cancellation, optional unipolar/bipolar operation, optional gain selection It has the ability to select and cancel the temperature coefficient. The circuit has an input reference voltage An onboard single gain inverting amplifier is provided between the resistor ladder array and the resistor ladder array. It's sea urchin. This results in a certain positive output from this DAC in response to a certain positive reference voltage. Make the output voltage supplied. Additionally, for optional bipolar operation can be started by closing one switch, and That switch connects that reference voltage to the inverting input of the DAC's output buffer amplifier. A resistor that directs the current at the inverting input of the output buffer amplifier to its (scaled to offset the reference current by 172) It is something to do.

For analog ground voltage drift, its effective cancellation is The magnitude of the current that the resistor ladder array supplies to analog ground relative to the ground connection point is This is done by applying currents that are substantially equal but of opposite polarity. this is, Small, non-trimmed 4-bit R-2 with non-inverting reference input added This is done by providing an R ladder, which is the top 4 of the main R-2R ladder. The switch should be made in parallel with the focus, and this will cause the main focus to change. Provides the same amount of current but opposite polarity as the 4 most significant bits of the data array. Or sync it. This cancels a significant portion of the ground current. cell and therefore the output voltage and current impedance in the analog ground current line. the effect on switch voltage is substantially reduced.

mode select) FET switch is set at the reference voltage through an appropriately sized resistor. Provided to selectively switch to the inverting input of the output buffer amplifier, thereby Therefore, a choice is made between unipolar and bipolar operation. Two more F's The ET switch, ie the gain select switch, of the output buffer amplifier provided to switch between one of two possible resistance values at each end, thereby allowing the two Different gain possibilites are provided. In a preferred embodiment, the The resistance value is 1o volts or 2o volts in response to a 10 volt input reference voltage. determined to provide a sufficiently large output voltage range.

Temperature reduction of FET switches used in R-2R ladders without using excessive semiconductor area Contrary to the effect of the gain coefficient, the gain select switch be appropriately determined to be the minimum size necessary to maintain integrity. Furthermore, the said model The gain select switch reverses the temperature drift of the gain select switch. and to maintain linearity, in conjunction with the gain select switch. Determined proportionately. The gain select switch and mode select switch Since the chip is smaller than the DAC ladder switch, the DAC ladder switch is the temperature that exceeds the temperature equal to the resistance of the gain and mode select switch. There is no way to trace it. Therefore, the temperature coefficient of the DAC switch is equal to the output voltage increases with temperature, which reduces the accuracy of the DAC's output. , to compensate for this, four switches are added to the input of the single gain inverting amplifier. has been done. These four switches are determined to have certain resistance values.

This certain resistance value reduces the output of the single gain inverting amplifier and virtually cancels the effect of increased voltage on the output of the system and increases the output of the system with temperature variations. This is a resistance value that is a constant value for monitoring as the temperature changes.

The invention will be more fully understood from the following detailed description read in conjunction with the accompanying drawings. It will be. This description is given by way of example only and the invention defined only by the claims appended at the end of the description.

Concave plate q gong single star alliance FIG. 1 shows a prior art 8-bit digital-to-analog converter.

FIG. 2 shows a general circuit diagram of the digital-to-analog converter of the present invention.

Figure 3 shows details of the R-2R ladder of the present invention and the R-2R ladder for ground current cancellation. A circuit diagram is shown.

FIG. 4 shows a second, more detailed circuit diagram of the digital-to-analog converter of the present invention. vinegar.

Figure 5 shows the mode select register for the digital-to-analog converter of the present invention. Indicates the data.

na no na Figure 2 shows the three main parts: the input buffer amplifier 20 and the digital input. The present invention consists of a resistive ladder portion 30 and an inverting output buffer amplifier 40. This diagram shows a conventional digital-to-analog converter, which is basically a prior art R- Input buffer amplifier 2o to 2R ladder section 30 and output Hannover amplifier 40 Indicates the addition of In the simplified form of Figure 2, Vref is the inverse of the unit gain. is applied to the input of the input amplifier, whereby the ladder section 30 receives the inverter as its input. Receive the transferred Vref. V ref is further passed through a 20 kilohm resistor. and is fed to the input of the inverting output amplifier. This connection is full scale at summing junction 4. Inject half the current, thereby giving bipolar operation. If digital If word 32 is given in two's complement or offset binary form, then all four words Drant action can be obtained.

By adding an input inverting bumper amplifier, the Excessive analog ground voltage resulting in non-zero voltage appearing at the “ground” terminal of the FET switch. Provides a very simple and effective way to eliminate flow problems. at the ground node Analog ground drift due to excess current is due to offset drift and full scale DAC resistor ladder segment outputs. Causes linearity.

The effects of analog ground drift are channeled into the analog ground by a resistor ladder. By passing an additional current substantially the same and opposite to the current through the analog ground connection. It can be removed by This effectively eliminates the current in the analog ground, resulting in a resistive ladder. Virtually no voltage appears at the ground terminal of the switch in the DAC, and the DAC has an inverting input buffer. Adding an amplifier to provide such current to analog ground is very simple. Give a simple and effective method.

Referring to FIG. 3, a 12-bit main resistance ladder 52 is generally shown. addition Nodes are represented by 14 bits and analog ground by 16 bits. As mentioned above, the inverted The Vref signal is fed to the input of the main resistor ladder via an inverting input buffer amplifier. be done. Cancellation of analog ground current is achieved by applying Vref directly to the input, i.e. by inverting it. A small untrimmed 4-bit R-2R ladder 56 is available This is achieved by The four legs of the current canceling R-2R ladder 56 are is switched in parallel with the upper 4 bits of the main R-2R ladder 52, thereby It current cancel that supplies (or absorbs) the opposite current to the upper 4 bits of the ・The analog ground terminal of the switch in the ladder is analog ground 1 as well as the main ladder. 6. The “summing node” terminal of the switch returns additional current to ground. The summing node terminal is connected to a circuit 54 that drives the summing node terminal equal to ground without causing any damage.

This circuit may not be required if a separate path to external ground is available.

The current canceling resistor ladder is approximately equal to analog ground, but the main resistor ladder A voltage that is the opposite of the current supplied to analog ground by the four topmost pins of the It is clear that the current will be supplied. In fact, as the equation below shows, The current cancellation ladder is designed for the worst-case situation (i.e., if the digital word The current supplied to analog ground by the current canceling ladder is transferred by the main ladder to Even situations that cause the current supplied to the analog ground to differ from the current supplied to the analog ground Cancels over 90% of earth current. This means that the DAC is set to all zeros. Occurs when all DAC currents are switched to ground. V ref is the current Assuming feeding the input of the -2R main ladder, the following equation holds true.

The current supplied to analog ground by the main ladder is given by:

Analog ground current - (4095/4096) X I = 0.9997588I The current supplied to analog ground by the current cancel ladder is given by: It will be done.

Opposite analog ground current = -(15/16) x I = -0,9375I or less This cancels over 90% of the analog ground current, as shown by the equation I'm celling.

0.937510.9997588=0.938=93.8%R-2R ladder Provides a current cancellation ladder so resistors do not need to be trimmed to exact values Cost is low. The small analog connection that remains after substantial current cancellation Earth currents are not large enough to enforce the integrity of the analog output voltage, so No trimming is necessary. However, precise cropping cannot be done if desired. Ru. The current canceling ladder also has four astragalus (l) depending on the desired accuracy. eg) may have more or less legs.

The addition of a unity gain inverting amplifier also adds another stage to the DAC's resistor ladder for output inversion. Eliminating the need for additional circuitry following. Unity gain inverting amplifier is the first part of the DAC ladder. inverts the Vref supplied to the can be obtained from the DAC in response to a positive Vref without the need for an inverting circuit in the stage. Ru.

Figure 4 shows the DAC (Analog/Digital Converter) of the present invention in more detail. This is a diagram. The UNI/B I switch 42 is composed of a FET switch, When the switch 42 is in the on state, an output voltage is applied to the input of the output sofa amplifier 40 to 20. voltage Vref through the resistor of the DAC, thereby increasing the full-scale current of the DAC. A current equal to 1/2 of the current is supplied to node 4. The DAC is switched on when the switch 42 is turned on. When the switch 42 is in the off state, it operates in bipolar mode, and when the switch 42 is in the off state, it operates in unipolar mode. Operates in la mode. Switches 44 and 46 are also comprised of FET switches. and is selectively used to set the gain of the output buffer amplifier 40 to a predetermined value. Ru. Switches 44 and 46 are turned on and off alternately, so that only one of them is on at any given time. Controlled to be in the on state. When the switch 44 is turned on, the IOK ohm Resistors 48 and 50 are connected in series to provide a voltage of 20 to 20 ohms between the input and output of operational amplifier 40. provides a feedback resistance of The resistor ladder has a total input of approximately It provides a resistance of IOK ohms, so in this mode there is a gain of 2 and the output The maximum output range of Vout is twice the voltage of Vref. switch 46 is on Then only a resistor 50 of IOK ohms is connected between the input and output of the operational amplifier, and therefore In the case of a lever, the gain is 1.

By combining switches 42, 44 and 46, four movements can be made to the DAC. operation mode is possible. If Vref is 10 volts, 0 to 10 volts unipo – polar mode, unipolar mode from 0 to 20 volts, bipolar mode from –5 to +5 volts bipolar mode and -10 to +10 volts are selected. suitable In the example embodiment, the bit pattern for selecting these options is 2 runs. It is stored in the credit register and configured so that the mode can be updated with one instruction. It is. The output of this register is M20V, MIOV, UNT/B I. It is shown in FIG. As mentioned above, the M20V and MIOV lines alternate One is always on and the other is off. third line , that is, UNI/B I is -rref/2 at the output of the resistor ladder section 30. Controls the voltage applied as an offset. The first two The switch controls the feedback loop of the output operated amplifier as shown in Figure 4. , and the gain is adjusted accordingly.

The UNI/BT switch introduces -r ref and outputs in MIOV mode. Pull down the force by Tref/2, and in M20V mode, only Iref In the pull-down circuits of Figures 4 and 5, there are technically four modes to choose from. However, the option of unipolar mode in the 20 port range is thereby indicated. This is because the full-scale voltage often exceeds the output range of the operational amplifier 40. , not commonly used. However, it is not suitable for amplifying small output codes. It is.

Each of the FET switches 42, 44, 46 is connected to the other switches in the circuit. each switch in the system gain. The opposite effects of and therefore the precision cancel each other out. These switches are mutually , the resistance value in the switching state is set to be directly proportional. Since the switch 46 is connected to a resistor 50 of IOK ohms, the switch 46 A switch connected to a resistor of 42.44 ohms has a resistance value of 172 to 20 It is set as follows. A FET switch has a non-zero temperature coefficient, so the switch has a temperature-dependent resistance drift. However, a monolithic structure Since all switches in the circuit have approximately the same temperature coefficient, The switch resistance values almost cancel each other out regardless of the relationship.

Gain selection switches 44, 46 are of the minimum size necessary to prevent nonlinear characteristics. scaled to avoid adversely affecting the linearity of the DAC transition function. one In the preferred embodiment, each of the gain selection switches 44,46 is R- Give an equal on-resistance to the DAC switch that switches the equivalent value of the resistance of the 2R ladder. scaled ratiometrically so that However, with such a low resistance in the switch, I don't like giving. Extremely large silicon for each switch This is because it requires space. This allows parasitic capacitance and leakage current to be added to the DAC. at the connection point, causing frequency instability and temperature drift. at least one In the preferred embodiment, gain selection switches 44,46 are used for the DAC transition function. chosen to have the minimum size necessary to maintain linearity. Implementation of Figure 4 In the example, gain selection switch 46 is equal to or greater than the total on-resistance of the AC switch. can be scaled to approximately 4 times the total size (ie, 174 times the size). So, switch Switch 44 is twice the size resistor of switch 46 (20K versus 10K). scaled to be twice the on-resistance of switch 46 due to the fact that be done. Mode selection switch 42 then has a scale equal to that of switch 44. will be sent. This is because the resistance is switched to 20 in both cases. Switch 42.44. Since 46 is ratiometrically correct, its temperature coefficient is i.e. when the DAC is switched off and the device is in bipolar mode. properly so that there is virtually no temperature drift in the total gain of the system when at Follow.

However, when the effect of the DAC ladder is not zero, the DAC switch 42, 44, 46, so the circuit output varies with temperature. Drift with. Because of this effect, the gain of the output amplifier is equal to the DAC's output current changes with temperature at a faster rate than That is, for example, as the temperature increases, The on-resistance of the DAC switch increases by almost 5 ohms, but the gain selection switch in series On-resistance varies by 20 ohms. This mismatch may result in some form of compensation. If not introduced, the gain of the system is increased with respect to temperature. bias switch A switch 52 is added to the inverting input of the input amplifier to provide this compensation. Swish (i.e., FET resistor 52) with the same temperature characteristics as the FET resistor 52. By inserting a temperature-dependent resistor into the gain path of the circuit, temperature drift can be effectively eliminated. qualitatively removed from the DAC.

The example below shows the effectiveness of the switch in preventing errors in the output voltage Vout. There is. The full scale resistance of DAC30 is 10.010 ohms (i.e. 10.00 0 ohm plus the switch resistance at full scale of 10 ohm) , the following switch resistance values are selected for the switch:

Gain selection switch 44 (20 volt span) -80 ohm gain selection switch 4 6 (10 volt span) = 40 ohm mode selection switch 42 = 80 ohm bias switch 52 = 60 ohms These resistors are Accurately set by rimming.

in unipolar ±5 volt mode in response to the full scale digital word previously applied. The gain of a circuit with a resistance value is given by the following equation.

=0.9999969 Vref! :1Vref switch 52 removed from the circuit and all other switch resistances are the same as shown in Figure 4. The equation for the ±5 volt mode is:

=1.002997Vref As is clear from the above equation, the insertion of the bias switch 52 significantly reduces the accuracy of the DAC. Always increase. Vo in bipolar ±5 volt mode with and without switch 52 The valid values (hold true) for ut are as follows.

In bipolar ±10 volt mode, the first The valid values for the circuit of Figure 4 are as follows.

As the temperature changes, the switch resistance also changes. However, the DAC is Since it is a nolithic structure, all switch resistances change at approximately the same rate, Therefore, the ratio of Vout to Vref can be changed to a remarkable degree from the value shown by the above formula. There's nothing to do. Bias switch 52 is proportionally adjusted to provide an on-resistance. This resistance changes with temperature and adjusts the DAC switch resistance and gain/mode. In the same way that the unbalance between the switch resistance and the At the same rate, the gain of the human power amplifier decreases with increasing temperature. Includes switch 52 Otherwise, the gain could be precisely trimmed at one temperature, but if switch 52 The error accumulates over the approximate temperature drift shown in the calculations above if Multiply.

Although one particular embodiment has been described, various alterations, modifications, and improvements may occur to those skilled in the art. Therefore, such changes or modifications as may be readily made by this disclosure, may be readily made. Modifications and improvements not described herein are part of this description and include modifications and improvements to the invention. It is in spirit and scope. Accordingly, the foregoing description is for illustrative purposes only. It shouldn't be restricted. The invention is defined by the following claims and their equivalents: It's just that it's limited.

Submission of translation of written amendment (Article 184-8 of the Patent Act) April 4, 1991

Claims (10)

[Claims] 1. a first inverting operational amplifier having an input terminal for receiving a reference voltage and an output terminal; and, Resistor ladder array that converts digital words to corresponding analog currents b, the array has an input terminal connected to the first inverting operational amplifier and a summing an output terminal connected to the junction, and the array has a supply terminal connected to the input terminal. divide the input current according to the digital word, and divide the first part of the input current into the resistor. the output terminal of the ladder array and the second part to the analog ground junction. The model to be sent, a second inverting operational amplifier having an input terminal and an output terminal, the input terminal being connected to the output of the resistor ladder array at the summing junction. A digital-to-analog converter characterized by: 2. The resistor ladder array includes a plurality of resistor leg portions, each leg having a front corresponding to the bits of the digital word and relative weights of the corresponding bits. carrying a corresponding portion of said current, each of said legs having switch means; The switching means is controlled by said corresponding bit to Apply that current to analog ground when the corresponding bit is in the first state. The characteristic is that the current is applied to the summing junction when the cut is in the second state. The analog-to-digital converter according to claim 1, wherein: 3. a second resistor ladder array having an input terminal connected to the reference voltage source; Thus, the second resistive ladder array has no more series than the first resistive ladder array. having a plurality of successive resistive leg sections, each leg containing the current section of the preceding leg. The switch carries the current part, and each leg is controlled by a digital input bit. and switching means for switching the associated record if the corresponding bit is zero. The current in the analog circuit is caused to flow through the analog ground, and the corresponding bit is one. current in the associated rec to a virtual ground separate from the analog ground. flowing and the second resistor ladder array parallel to the most significant bit of the digital word; to be switched The analog-to-digital converter according to claim 2, characterized in that: 4. further comprising a mode selection switch, wherein the mode selection switch is in the first state. A reference voltage is connected to the summing junction and an optional voltage is applied when in the first state. characterized by forming an open circuit in the case of the second state so as to permit polar operation. 4. The analog-to-digital converter according to claim 3. 5. to provide a plurality of possible gain factors for the second amplifier; The output of the second inverting operational amplifier is connected to the inverter of the second inverting amplifier via a plurality of resistors. a plurality of gain selection switches changeably connected to the input input; a bias switch between the first inverting amplifiers, the switch being normally in a closed position; 5. The analog digital according to claim 4, characterized in that it is biased in position. converter. 6. The plurality of gain selection switches include first and second switches. 6. The analog-to-digital converter according to claim 5, wherein the analog-to-digital converter has the following characteristics. 7. The mode selection switch, gain selection switch and bias switch are F. An analog-to-digital converter characterized by being an ET switch. 8. The mode selection switch, the bias switch, the ladder switch and the first and and a second gain selection switch respectively Other switches such that the net effect of the temperature coefficient of resistance of the switch on the power is zero The analog/digital converter according to claim 7, having a temperature coefficient of resistance associated with Mbaata. 9. The digital-to-analog converter is monolithic, which allows the total According to claim 8, the switches have substantially equal temperature coefficients. analog to digital converter. 10. the first resistance ladder having three times the number of legs as the second resistance ladder; The analog-to-digital converter according to claim 9, characterized in that: