JPH0449851A - Driving circuit for dc/dc converter - Google Patents

Abstract

PURPOSE:To reduce a stress of a MOSFET and to reduce noise by lengthening only a delay time of rising times of gate and source voltages of a switching MOSFET. CONSTITUTION:When MOSFETs 1, 4 are simultaneously turned ON, rising delay times of gate and source voltages of the MOSFETs 1, 2 are lengthened by inductances 7, 8. Since the output capacities of the MOSFETs 2, 3 are charged, the peak value of a spikelike current when the drain and source currents of the MOSFETs 1, 4 rise is reduced. When the MOSFETs 1, 4 are simultaneously turned OFF, the inductances 7, 8 are clamped by diodes 5, 6. Accordingly, the delay times of falling gate and source voltages of the MOSFETs 1, 4 are not lengthened, and hence a switching loss is not increased. Thus, a stress to be applied to the MOSFET and noise to be generated can be reduced.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention increases the delay time of the drive circuit of a DC-DC converter, especially when the switching MOSFET is turned on, thereby reducing stress on the MOSFET and noise generated. The present invention relates to a drive circuit for a DC-DC converter that reduces power consumption.

[Conventional technology]

Conventionally, the )'-IF circuit of this type of DC-DC converter has two parts of the drive transformer 9, as shown in FIG.
Connect the gate terminal of MOSFET I5 at the beginning of winding of the next winding 19, connect the end of winding of the secondary winding 19 of the drive transformer 9 and the source terminal of MO8FEr16,
Resistor 21 is connected in parallel between the gate terminal and source terminal of ET15.
are connected.

By generating a pulse voltage between the beginning and end of the winding of the secondary winding 19 of the transformer, a pulse voltage is generated in the resistor 21, and a pulse voltage serving as a switching signal is applied between the gate terminal and the source terminal of the MOSFET 15.
SFET15 is switched.

[Problem to be solved by the invention]

The conventional DC-DC converter drive circuit described above reduces the rise and fall times of the voltage between the drain and source by shortening the delay time at the rise and fall of the switching signal applied between the gate and drain of the MOSFET. When trying to shorten the delay time of MO
SFET45.18 at 08:00 MOSFET18.1
Because the peak value of the current that charges the output capacitance of MSOFET 15.18 increases, the peak value of the spike-like current flowing between the drain and source of MSOFET15.18 increases, and the
The stress placed on 15.18 increases, and the noise also increases.

Similarly, MOSFET16.17 turns off at 08:00.
Because the peak value of the current charging the output capacitance of MOSFET 15.18 in the state increases, MOSFET 16.1
The disadvantage is that the peak value of the spike-like current at the rise of the drain-source current of No. 7 increases, the stress applied to the MOSFETs 16 and 17 increases, and the noise also increases.

[Means to solve the problem]

The drive circuit of the DC-DC converter of the present invention includes the winding start of the secondary winding of the drive transformer and the switching M
For switching, the resistor is connected in parallel between the gate and source terminals of the OSFET, and the inductance is connected in series with the terminal connected to the gate terminal of the MOSFET, and the winding start and cathode terminal of the drive transformer are connected for switching. A diode whose anode terminal is connected to a terminal connected to the gate terminal of the switching MOSFET and a resistor connected between the gate and source terminals of the switching MOSFET is used.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Inductance 7 is the secondary winding 19 of drive transformer θ
is connected in series between the winding start of the resistor 10 and one end of the resistor 10 connected to the gate terminal of the MOSFET I.

The diode 5 has a cathode terminal connected to one end of the secondary winding 19 of the drive transformer 9 at the beginning of winding and an anode terminal connected to the gate terminal of the MOSFET I of the resistor 10 so as to be parallel to the inductance 7 .

The inductance 8 is the secondary winding 20 of the drive transformer 9
is connected in series between the winding start of the resistor 10 and one end of the resistor 10 connected to the gate terminal of the MOSFET 4. The cathode terminal of the diode 6 is connected to the beginning of the winding of the secondary winding 20 of the drive transformer 9 so that it is parallel to the inductance 8.
The anode terminal is connected to one end of the resistor 11, which is connected to the gate terminal of the MOSFET 4.

The end of the secondary winding 19 of the drive transformer 9 is connected to the source terminal of the MOSFET with resistance 0, and the end of the secondary winding 20 is connected to the source terminal of the MOSFET with resistance 11.
Each of the terminals is connected to one end connected to the source terminal of No. 4.

When MOSFETI and 4 are turned on at the same time, MOSFET
Since the rise delay time of the gate-source voltage of ETI,2 becomes longer due to the inductance 7.8, the MOS
Since the output capacitance of FET2.3 is charged, the MOSFE
The peak value of the spike-like current at the rise of the drain Φ source current of T1.4 can be reduced.

When MOSFET 1.4 is turned off at the same time, inductance 7.8 is clamped by v2 of diode 5.6, so the delay time when the gate O source voltage of MOSFET 1.4 falls does not become long, so switching loss increases. do not.

The drive circuit connected to MOSFET 3.2 also has a diode and an inductance as described above, so that the MOSFET 3.2 is
The peak value of the spike-like current at the rise of the drain Φ source current of T3,2 is reduced.

When MOSFET2.3 is OFF, MOSFET2
, 3) - Since the fall delay time of the source voltage does not become long, the rise delay time of the drain-source voltage of MOSFET 2.3 does not become long, so the switching loss does not increase.

〔Effect of the invention〕

As explained above, the present invention provides switching MOS
By increasing only the delay time when the FET gate-source voltage rises, switching MOSFE
This has the effect of reducing stress on T and reducing noise, and further preventing an increase in switching loss when the switching MOSFET is turned off.

MOSFET for switching15.6...Diode, 7,8...Inductance, 9.14...Drive transformer, 10.11...Resistance.

Claims (1)

[Claims] An inductance connected in series between the winding start of the secondary winding of the drive transformer and one end connected to the gate terminal of the switching MOSFET of a resistor connected in parallel between the gate and source terminals of the switching MOSFET. The switching MOSFET is connected at the cathode terminal to the beginning of the secondary winding of the drive transformer.
has a diode whose anode terminal is connected to one end connected to the gate terminal of the switching MOSFET of a resistor connected in parallel between the gate and source terminals of the resistor, and the other end of the resistor is connected to the source terminal of the switching MOSFET. A drive circuit for a DC-DC converter, characterized in that a terminal is connected to an end of a secondary winding of the drive transformer.