JPH0448762A - Semiconductor substrate for electronic apparatus - Google Patents

Semiconductor substrate for electronic apparatus

Info

Publication number
JPH0448762A
JPH0448762A JP15518090A JP15518090A JPH0448762A JP H0448762 A JPH0448762 A JP H0448762A JP 15518090 A JP15518090 A JP 15518090A JP 15518090 A JP15518090 A JP 15518090A JP H0448762 A JPH0448762 A JP H0448762A
Authority
JP
Japan
Prior art keywords
chip
groups
mounting
temperature
upstream side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15518090A
Other languages
Japanese (ja)
Inventor
Yoshihiro Kondo
義広 近藤
Hitoshi Matsushima
均 松島
Toshio Hatada
畑田 敏夫
Takao Oba
大場 隆夫
Akira Yamagiwa
明 山際
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15518090A priority Critical patent/JPH0448762A/en
Publication of JPH0448762A publication Critical patent/JPH0448762A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve cooling performance due to proper array of IC chip groups and to further activate a board by arranging the groups of both-side mounting at the upstream side of cooling fluid from the group of one-side mounting. CONSTITUTION:If IC chip 2 groups of one-side mounting 3 and IC chip 2 groups of both-side mounting 4 are mixed, the groups of the mounting 4 are arranged at the upstream side and the groups of the mounting 3 are arranged at the downstream side to suppress the highest temperature of the chip to a relatively low value. The reason is because, if the groups of the mounting 4 are arranged at the upstream side, cooling air having not large air temperature rise can be activated. Since the groups of the mounting 3 at the downstream side occupies a large weight of heat dissipating from a board, the rise of the chip temperature can be suppressed to a small value even by considering the air temperature rise due to the groups of the mounting 4 at the upstream side. Further, in order to improve cooling performance, when the IC chip 2 groups are arranged in a zigzag manner, the effect is further large.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、コンピュータなどの電子装置における片面実
装と両面実装のICチップ群の混在する基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a board in which single-sided and double-sided IC chip groups are mixed in electronic devices such as computers.

〔従来の技術〕[Conventional technology]

コシピユータ等の電子装置におけるICチップ群の基板
配列において、基板の両面実装と片面実装が混在する場
合の公知例はほとんどない。なお、この種のものに関連
するものには、例えば、特開昭59−214246号公
報が挙げられる。
In the substrate arrangement of IC chip groups in electronic devices such as computer computers, there are almost no known examples of a case in which double-sided mounting and single-sided mounting of the substrate are mixed. Note that related to this type of device, for example, Japanese Patent Application Laid-Open No. 59-214246 can be cited.

また、ICチップの冷却方法は特開平l−115198
号公報に記載のように、冷却空気を導通させるためのダ
クトを有し、このダクトに噴出孔を設けて発熱部分にだ
け冷却空気を送り、衝突冷却を行っていた。
Also, the method for cooling IC chips is disclosed in Japanese Patent Application Laid-open No. 1-115198.
As described in the above publication, it had a duct for conducting cooling air, and this duct was provided with blow-off holes to send cooling air only to the heat-generating parts, thereby performing collision cooling.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術は、基板の配列について考慮がされておら
ず、基板上の下流側のICチップの温度上昇を低下させ
、信頼性を確保するという面から基板上のICチップ群
の配列を考える余地があった。
The above conventional technology does not take into consideration the arrangement of the substrate, and there is room to consider the arrangement of the IC chips on the substrate from the viewpoint of reducing the temperature rise of the IC chips on the downstream side of the substrate and ensuring reliability. was there.

本発明の目的は、コンピュータ内の基板上に搭載された
片面実装、両面実装のICチップ群の配列の適正化によ
る冷却性能の向上を図り、さらに基板を活用することに
より、−層の冷却性能向上を目指したものである。
The purpose of the present invention is to improve the cooling performance by optimizing the arrangement of single-sided and double-sided IC chip groups mounted on a board in a computer, and to improve the cooling performance of the -layer by utilizing the board. The aim is to improve this.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、基板上に搭載された、片面
実装1両面実装のICチップ群の配列を上流側の両面実
装のICチップ群、下流側に片面実装のICチップ群を
設けて、ICチップの最高温度を低減するようにしたも
のである。
In order to achieve the above object, the arrangement of single-sided mounting and double-sided mounting IC chip groups mounted on the board is such that the double-sided mounting IC chip group is provided on the upstream side, and the single-sided mounting IC chip group is provided on the downstream side. This is designed to reduce the maximum temperature of the IC chip.

さらに、ICチップ群の一層の冷却性能の向上と各IC
チップの温度の均一化のために、基板に空気流入の小穴
を下流方向へ行くに従い、径が大きくなるように設け、
傾斜スリットを取り付けたものである。
Furthermore, we have further improved the cooling performance of the IC chip group and
In order to equalize the temperature of the chip, small holes for air inflow are provided in the substrate so that the diameter increases as you go downstream.
It is equipped with an inclined slit.

〔作用〕[Effect]

両面実装のICチップ群を上流側へ、片面実装のICチ
ップ群を下流側へ配列することは、局部的な風温上昇を
抑えることができる。それによって、ICチップの最高
温度を低減できるので、ICチップの冷却性能は向上し
、信頼性は確保される。さらに、ICチップ群を千鳥配
列によることにより、冷却風の活用ができそれによって
、ICチップの冷却性能は向上する。さらに、基板を活
用し、冷却風を取り込むことにより、風温上昇を抑える
ことができる。それによって、ICチップの最高温度を
低減できるので、ICチップの冷却性能は一層向上し、
信頼性も大きく確保できる。
By arranging the double-sided mounted IC chip group on the upstream side and the single-sided mounted IC chip group on the downstream side, it is possible to suppress a local increase in air temperature. As a result, the maximum temperature of the IC chip can be reduced, improving the cooling performance of the IC chip and ensuring reliability. Furthermore, by arranging the IC chip groups in a staggered manner, cooling air can be utilized, thereby improving the cooling performance of the IC chips. Furthermore, by utilizing the board and taking in cooling air, it is possible to suppress the rise in air temperature. As a result, the maximum temperature of the IC chip can be reduced, further improving the cooling performance of the IC chip.
Reliability can also be greatly ensured.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明する0本図
はコンピュータのICチップ群1片面実装3のICチッ
プ2を下流側に、両面実装4のICチップ2を上流側へ
もってゆき、千鳥配列した場合の例である。ICチップ
2内の数値は、そのICチップ2の表面温度TLsr 
と流入空気温度Ta5rの差、ΔT (= Tt、sr
  Tier)である。
Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 1. This figure shows a computer IC chip group 1 in which an IC chip 2 with single-sided mounting 3 is brought to the downstream side and an IC chip 2 with double-sided mounting 4 is brought to the upstream side. , is an example of a staggered arrangement. The value inside the IC chip 2 is the surface temperature TLsr of the IC chip 2.
and the inflow air temperature Ta5r, ΔT (= Tt, sr
Tier).

ΔTの最高温度は、45.8度となり、ICチップ2の
温度分布もほぼ均一に保たれている。この理由として、
千鳥配列にすることにより、前方のICチップ2からの
放熱による風温上昇した空気を受けにくい、すなわち、
新鮮な冷却風による効果を取り入れられるためである。
The maximum temperature of ΔT was 45.8 degrees, and the temperature distribution of the IC chip 2 was also kept almost uniform. The reason for this is
By using a staggered arrangement, it is difficult to receive air whose temperature has increased due to heat dissipation from the IC chip 2 in front, that is,
This is because the effect of fresh cooling air can be taken into account.

次に、第1図の上流側にある両面実装4のICチップ2
群の配列を基盤目にした場合の例を第2図に示す、八T
の最高温度は46.6度となり、第1図の千鳥配列の場
合よりも0.8 度高くなっている。これは、前方のI
Cチップ2の風温上昇した空気による冷却効果のためで
ある。しかし。
Next, the IC chip 2 of double-sided mounting 4 on the upstream side of FIG.
An example of the case where the group arrangement is seen as the base is shown in Figure 2, 8T.
The maximum temperature was 46.6 degrees, which is 0.8 degrees higher than in the staggered arrangement shown in Figure 1. This is the front I
This is due to the cooling effect of the air at the C-chip 2 whose temperature has increased. but.

ICチップ2の温度分布は、第1図の場合と同様に、は
ぼ均一に保たれている。
The temperature distribution of the IC chip 2 is kept almost uniform as in the case of FIG.

次に、第2図とは逆に、下流側に両面実装4のICチッ
プ2群を、上流側に片面実装3のICチップ2群をもっ
てきた場合の例を第3図に示す。
Next, FIG. 3 shows an example in which, contrary to FIG. 2, two groups of IC chips with double-sided mounting 4 are brought on the downstream side and two groups of IC chips with single-sided mounting 3 are brought on the upstream side.

ΔTの最高温度は、48.8度と第2図の場合よりも高
く、ICチップ2の温度分布も不均一性が大きくなり、
信頼性に欠けている。
The maximum temperature of ΔT is 48.8 degrees, which is higher than in the case of FIG. 2, and the temperature distribution of the IC chip 2 also becomes more non-uniform.
Lacks reliability.

また1片面実装3のICチップ2群を基板1の下方に、
両面実装4のICチップ2群を基板1の上方に配列した
場合の例を第4図に示す。ΔTの最高温度は、50.5
 度と第3図の場合より更に高くなっている。また、I
Cチップ2の温度分布も、極めて不均一となっている。
In addition, two groups of IC chips mounted on one side 3 are placed below the substrate 1,
FIG. 4 shows an example in which two groups of IC chips mounted on both sides 4 are arranged above the substrate 1. The maximum temperature of ΔT is 50.5
This is even higher than in the case of Figure 3. Also, I
The temperature distribution of the C chip 2 is also extremely non-uniform.

この理由として、片面実装3の場合、基板1からの放熱
が大きなウェイトを占めているのに対し、両面実装4の
場合は、基板1からの放熱がほとんどなく、下流側へ行
くに従い、風温上昇した空気を受けるため、ΔTの最高
温度も高い値となっている。従って、ICチップ2の信
頼性が失われている。
The reason for this is that in the case of single-sided mounting 3, the heat dissipation from the board 1 accounts for a large amount of weight, whereas in the case of double-sided mounting 4, there is almost no heat dissipation from the board 1, and as you go downstream, the air temperature increases. Due to the rising air, the maximum temperature of ΔT is also high. Therefore, the reliability of the IC chip 2 is lost.

以上のことをまとめたものを第5図に示す、縦軸にはΔ
T、横軸には上流側から下流側への距離が取られている
6第1図、第2図の例の場合の温度分布は波はあるもの
の、比較的均一で、最高温度も低くなっている。それに
対し、第3図、第4図の例の場合の温度分布は、不均一
で、最高温度も高くなっている0以上の事象より明らか
なように、片面実装3のICチップ2群と、両面実装4
のICチップ2群が混在する場合、上流側に両面実装4
のICチップ2群を、下流側に片面実装3のICチップ
2群を配列することにより、チップ最高温度を比較的小
さく抑えることができる。その理由として、両面実装4
のICチップ2群を上流側に配列した場合、風温上昇が
大きくない冷却風を活用でき、その上、下流側の片面実
装3のICチップ2群は、基板からの放熱が大きなウェ
イトを占めるため、上流側の両面実装4のICチップ2
群による風温上昇を考慮しても、チップ温度の上昇を小
さく抑えることができる。更に、冷却性能を向上させる
上で、ICチップ2群を千鳥配列にすると、−層効果が
大きい。
A summary of the above is shown in Figure 5, where the vertical axis shows Δ
T, the horizontal axis shows the distance from the upstream side to the downstream side.6 Although the temperature distribution in the examples in Figures 1 and 2 has waves, it is relatively uniform and the maximum temperature is low. ing. On the other hand, the temperature distribution in the examples shown in FIGS. 3 and 4 is non-uniform, and as is clear from the phenomenon of 0 or more where the maximum temperature is high, two groups of IC chips with single-sided mounting 3 and Double-sided mounting 4
If two groups of IC chips are mixed, double-sided mounting 4 is installed on the upstream side.
By arranging two groups of IC chips with single-sided mounting 3 on the downstream side, the maximum chip temperature can be kept relatively low. The reason for this is that double-sided mounting 4
If two groups of IC chips are arranged on the upstream side, cooling air that does not cause a large increase in air temperature can be used, and in addition, for the two groups of single-sided mounted IC chips on the downstream side, heat radiation from the board occupies a large portion. Therefore, the IC chip 2 of double-sided mounting 4 on the upstream side
Even if the increase in wind temperature caused by the group is taken into consideration, the increase in chip temperature can be suppressed to a small level. Furthermore, in order to improve the cooling performance, if the two groups of IC chips are arranged in a staggered manner, the negative layer effect is large.

以上述べたように、ICチップ2群の配列は、両面実装
4のICチップ2群を上流側へもってゆき、さらに千鳥
配列にすることで、冷却性能が向上し、ICチップ2群
の温度分布をほぼ均一とし、ICチップ2の信頼性を確
保する上で最も効果がある。
As mentioned above, the arrangement of the two groups of IC chips is such that the two groups of IC chips with double-sided mounting 4 are brought to the upstream side and further arranged in a staggered manner, which improves the cooling performance and improves the temperature distribution of the two groups of IC chips. This is most effective in ensuring the reliability of the IC chip 2 by making it substantially uniform.

第6図の実施例は、さらに、ICチップ2群の冷却性能
、温度分布の均一化を向上させるために基板1に空気流
入のための小穴5を下流側へ行くに従い、径を大きくシ
、また、この流入空気量を制御するために、スリット板
6を設けたものである。スリット板6(a)とスリット
板6(b)に基板1に平行に置かれているが、ICチッ
プ2の温度上昇に伴い、空気温度も上昇し、それに反応
して流入量を制御できるように、スリット板6(a)。
In the embodiment shown in FIG. 6, in order to improve the cooling performance of the two groups of IC chips and to make the temperature distribution uniform, the diameter of the small holes 5 for air inflow into the substrate 1 is increased toward the downstream side. Furthermore, a slit plate 6 is provided in order to control the amount of air flowing in. The slit plates 6 (a) and 6 (b) are placed parallel to the substrate 1, but as the temperature of the IC chip 2 rises, the air temperature also rises, and the inflow amount can be controlled in response to this. , slit plate 6(a).

6(b)の一端に形状記憶合金でつくられたバネ7が設
けられている。バネ7の伸縮により、スリット板6(a
)と基板1の間では下流側に行くに従い、空気は膨張し
て圧力が低くなり、基板1とスリット板6(b)の間で
は、下流側に行くに従い、空気は圧縮されて圧力は高く
なる。この開領域の圧力差から、はとんど温度上昇をし
ていない空気が基板1の小穴5を通って、ICチップ2
間に流入し、温度境界層8をかく乱して、ICチップ2
の温度上昇を抑え、ICチップ2群の温度分布の均一化
を達成できる。
A spring 7 made of shape memory alloy is provided at one end of 6(b). Due to the expansion and contraction of the spring 7, the slit plate 6 (a
) and the substrate 1, the air expands and the pressure decreases as it goes downstream, and between the substrate 1 and the slit plate 6(b), the air compresses and the pressure increases as it goes downstream. Become. Due to the pressure difference in this open area, air whose temperature has not risen at all passes through the small hole 5 of the substrate 1 and reaches the IC chip 2.
The temperature boundary layer 8 is disturbed, and the IC chip 2
It is possible to suppress the temperature rise of the IC chips and achieve uniform temperature distribution of the two groups of IC chips.

第7図は、第6図の実施例の基板1を多層化したもので
ある。本実施例では、筐体実装への適用性を示したもの
である。
FIG. 7 shows a multilayer version of the substrate 1 of the embodiment shown in FIG. This example shows the applicability to case mounting.

第8図と第9図の実施例は、ICチップ2群に限らず、
基板1のチップ9の温度分布均一化のための装置である
。これらを組み合わせることにより、チップ9の温度分
布の均一化と冷却性能向上につながる・ 第10図の実施例は、第6図の実施例の基板1を小形高
性能電子演算機10に実装した場合である。基板1上に
は、ICチップ2群の他に半導体パッケージ11も1個
ないし複数個搭載されている。基板1は筐体12中に保
持されており、スリット板6は形状記憶合金のバネ7に
より可変であり、筐体12上部に基板1を冷却するため
のファン13が設置されている0本実施例では基板1上
のICチップ2の温度分布が均一となり、冷却風のむだ
がなく、ファン13の負荷の軽減にも役立ち、ファン1
3の回転により発生する騒音の低減にもつながる。
The embodiments shown in FIGS. 8 and 9 are not limited to the two groups of IC chips;
This is a device for making the temperature distribution of the chip 9 of the substrate 1 uniform. By combining these, the temperature distribution of the chip 9 can be made uniform and the cooling performance can be improved. The embodiment shown in FIG. 10 is a case where the board 1 of the embodiment shown in FIG. It is. In addition to two groups of IC chips, one or more semiconductor packages 11 are also mounted on the substrate 1. The board 1 is held in a housing 12, the slit plate 6 is variable by a shape memory alloy spring 7, and a fan 13 is installed on the top of the housing 12 to cool the board 1. In the example, the temperature distribution of the IC chip 2 on the board 1 becomes uniform, there is no wasted cooling air, and it also helps to reduce the load on the fan 13.
This also leads to a reduction in the noise generated by the rotation of No. 3.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように構成されているので以下
に記載されるような効果を奏する。
Since the present invention is configured as described above, it produces the effects described below.

同一流速で、片面実装のICチップ群1両面実装のIC
チップ群が混在する場合、ICチップ群の配列を上流側
へ両面実装のICチップ群、下流側に片面実装のICチ
ップ群とし、更に千鳥配列にすることにより、冷却風の
有効利用ができ、ICチップの信頼性が確保できる。ま
た、基板に空気流入の小穴を下流側になるに従い、径が
大きくなるように設け、形状記憶合金からなるバネを使
って、基板上のチップ群の温度分布を均一にするように
スリット板で制御し、冷却性能の向上を達成することが
出来る。
Same speed, single-sided IC chip group 1 double-sided IC
When chip groups are mixed, cooling air can be used effectively by arranging the IC chip groups, with double-sided mounting IC chips on the upstream side and single-sided mounting IC chip groups on the downstream side, and a staggered arrangement. The reliability of the IC chip can be ensured. In addition, small holes for air inflow are provided on the substrate so that the diameter increases toward the downstream side, and a slit plate is installed using a spring made of a shape memory alloy to even out the temperature distribution of the chips on the substrate. control and achieve improved cooling performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の正面図(a)および断面図
(b)、第2図は本発明の適用例の正面図(a)および
断面図(b)、第3図、第4図は本発明の他の異なる実
施例の正面図(a)および断面図(b)、第5図は本発
明の一実施例のICチップの流れ方向への温度分布図、
第6図は本発明の一実施例のICチップ群の温度分布を
均一にした場合の適用例の説明図、第7図は第6図の一
実施例の基板を多層化した場合の適用例の説明図、第8
図、第9図は本発明のガイド板を取り入れた場合の適用
例の説明図、第10図はICチップ群を筐体中に実装し
た場合の適用例の説明図である。 1・・・基板、2・・・ICチップ、3・・・片面実装
、4・・・両面実装、5・・・小孔、6・・・スリット
板、7・・・ばね。 8・・・温度境界層、9・・・チップ、1o・・・小形
高性能電子演算機、11・・・半導体パッケージ、12
・・・筐体、 13・・・ファン、 14・・・フィン、 15・・・ガイド 板・ 第2−図 (α) 第1図 牛 両菌昇辰 荊3図 (α) を 牛 雨I実殻 U=2 DMy/。 嵩牛図 牛 白面要叢 小穴 入り、、トv反 へ年 i側v1 栗 10+・Iブ÷1O距難 小穴 入り・、、ト他 パ冬 i*ii*喝 13−一−ファソ 牛−−−フィソ
FIG. 1 is a front view (a) and a cross-sectional view (b) of an embodiment of the present invention, FIG. 2 is a front view (a) and a cross-sectional view (b) of an application example of the present invention, FIG. 4 is a front view (a) and a sectional view (b) of another different embodiment of the present invention, and FIG. 5 is a temperature distribution diagram in the flow direction of an IC chip according to an embodiment of the present invention.
FIG. 6 is an explanatory diagram of an application example where the temperature distribution of an IC chip group is made uniform according to an embodiment of the present invention, and FIG. 7 is an application example when the substrate of the embodiment of FIG. 6 is multilayered. Explanatory diagram, No. 8
9 are explanatory diagrams of an application example in which the guide plate of the present invention is incorporated, and FIG. 10 is an explanatory diagram of an application example in which an IC chip group is mounted in a casing. DESCRIPTION OF SYMBOLS 1... Board, 2... IC chip, 3... Single-sided mounting, 4... Double-sided mounting, 5... Small hole, 6... Slit plate, 7... Spring. 8... Temperature boundary layer, 9... Chip, 1o... Small high performance electronic computing machine, 11... Semiconductor package, 12
...Housing, 13...Fan, 14...Fin, 15...Guide plate・Figure 2 (α) Fruit shell U = 2 DMy/. Bulky ox illustration cow white side with a small hole, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , other winter i * ii * , 13 - 1 - Faso cow -- −Fiso

Claims (1)

【特許請求の範囲】 1、基板上に配列された、片面実装、両面実装の混在す
るICチップ群より成る半導体装置において、 両面実装であるICチップ群を片面実装であるICチッ
プ群よりも冷却流体の上流側に配列したことを特徴とす
る電子機器用半導体基板。
[Claims] 1. In a semiconductor device consisting of a group of IC chips arranged on a substrate and having a mixture of single-sided mounting and double-sided mounting, the IC chip group that is double-sided mounted is cooled more than the IC chip group that is single-sided mounted. A semiconductor substrate for electronic equipment characterized by being arranged on the upstream side of a fluid.
JP15518090A 1990-06-15 1990-06-15 Semiconductor substrate for electronic apparatus Pending JPH0448762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15518090A JPH0448762A (en) 1990-06-15 1990-06-15 Semiconductor substrate for electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15518090A JPH0448762A (en) 1990-06-15 1990-06-15 Semiconductor substrate for electronic apparatus

Publications (1)

Publication Number Publication Date
JPH0448762A true JPH0448762A (en) 1992-02-18

Family

ID=15600240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15518090A Pending JPH0448762A (en) 1990-06-15 1990-06-15 Semiconductor substrate for electronic apparatus

Country Status (1)

Country Link
JP (1) JPH0448762A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120386A (en) * 1992-10-06 1994-04-28 Hitachi Ltd Method for cooling lsi and electronic circuit packaging
JP2009300779A (en) * 2008-06-13 2009-12-24 Konica Minolta Business Technologies Inc Heat dissipating device and image forming apparatus using the same
JP2017531913A (en) * 2014-09-16 2017-10-26 エスゼット ディージェイアイ テクノロジー カンパニー リミテッドSz Dji Technology Co.,Ltd Heat dissipation device and UAV using this heat dissipation device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120386A (en) * 1992-10-06 1994-04-28 Hitachi Ltd Method for cooling lsi and electronic circuit packaging
JP2009300779A (en) * 2008-06-13 2009-12-24 Konica Minolta Business Technologies Inc Heat dissipating device and image forming apparatus using the same
JP2017531913A (en) * 2014-09-16 2017-10-26 エスゼット ディージェイアイ テクノロジー カンパニー リミテッドSz Dji Technology Co.,Ltd Heat dissipation device and UAV using this heat dissipation device
US10178812B2 (en) 2014-09-16 2019-01-08 SZ DJI Technology Co., Ltd. Heat dissipation device and UAV using the same
US10681849B2 (en) 2014-09-16 2020-06-09 SZ DJI Technology Co., Ltd. Heat dissipation device and UAV using the same

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