JPH0448498A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable high-speed serial access by generating an address signal preceding to the address signal for serial access to be compared with a defective address and making the timing of redundant selection signal coincident with address output timing to serial access. CONSTITUTION:When taking in a top address signal AYi by a set address signal ALC, the top address signal AYi of the least significant bit is outputted as it is through a pass Pb when a carry input signal SCiB in a calculation part corresponded with the least significant bit is turned to be a high level. Therefore, +0 address operation is performed against the top address. On the other hand, the address turned to be +1 through a pass Pa against the top address corresponded with the least significant bit is formed when the carry input signal SCiB in the calculation part corresponded with the least significant bit is turned to be a low level. Thus, the high-speed serial access can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a technique effective for use in repairing defects in a semiconductor memory device having a serial access function.

[Conventional technology]

RAM (random access memory) section and SAM (
There is a multi-board RAM with serial access memo section. An example of such a memory is page 944 of the magazine "Toshiba Review" Vol. 43, No. 12 (1988).
There are ~pages 947.

[Problem to be solved by the invention]

In the conventional multi-board memory as described above, a comparator circuit determines whether an address is a rescue address or a non-repair address with respect to the output of an address counter, as shown in FIG. Therefore, when viewed as a whole, a comparison circuit for determining relief/non-relief is placed in the bus from the address counter to the decoder of the SAM section. Normally, it is impossible to enable the decoder until the comparison circuit completes the determination, so it is necessary to delay the timing of address determination. In low-speed operation, the overhead caused by such address comparison does not pose much of a problem. However, when used in the image field, etc., high bit rate read operations are required, so high-speed serial output is required, and the overhead spent on address comparison operations as described above cannot be ignored. It is.

An object of the present invention is to provide a semiconductor memory device that achieves high-speed operation while relieving defects.

The above-mentioned and other objects and novel features of the present invention will become apparent from the written description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor memory device equipped with a serial access function according to an address signal generated internally and a redundant circuit for relieving defects, an address signal that precedes the address signal for serial access is generated and the defect is removed. A comparison is made with the address, and the timing of the redundancy selection signal is made to match the address output timing for the serial access.

[For production]

According to the above-mentioned means, since it is possible to compare the next address with the defective address in parallel with address output for serial access, it is possible to eliminate the overhead caused by address comparison for defect relief, and to achieve high speed. Serial access is possible.

〔Example〕

FIG. 8 shows a functional block diagram of an embodiment of a multi-board memory to which the present invention is applied.

This figure is a block diagram expressed in terms of circuit functions. Although not particularly limited, the memory array MARY for random access has a storage capacity of 1024 (rows) x 512 (columns) = approximately 500. be done. By accessing eight such memory arrays MARY in parallel, color data consisting of x8 bits is stored as a unit. Therefore, by using two such multi-board memories, 1024X102
Color image data such as 256 colors can be stored at a high resolution such as 4th grade.

The address terminal consists of 10 bits AO to A9, and the row-related and column-related address signals are the row address strobe signal RAS and the column address strobe signal CAS.
are input in chronological order in synchronization with each other. The row address signal is taken into the row address buffer RAB, and the column address signal AYi is taken into the column address buffer CA.
B or serial address counter SAMAC. At this time, the address signal A9 of the most significant bit is
As mentioned above, since the column address is only 512, it is invalidated.

The serial address counter SAMAC performs a counting operation in synchronization with the serial clock, using the input column address as an initial value. This counting output is input to a Gray code counter GCC, although it is not particularly limited, and is converted into a Gray code here. The serial address signal converted into the gray code is used as a selection signal of the serial selector SS.

The serial access memory SAM is composed of a data latch circuit, and the serial selector SS is provided between its input/output node and a serial input/output line extending vertically in the figure. Further, the input/output node is connected to the 5th node of the memory array MARY via the transfer game (TRG).
Connected to 12 bit lines. Therefore, random
Data is mutually transferred in parallel between the access memory array MARY and the serial access memory SAM in units of 512 bits.

The serial main amplifier SM A is composed of eight unit circuits, and amplifies the serial data transmitted through the serial input/output line, and outputs the amplified data from the serial data terminals 5I100 to 5I7 through the serial output circuit AOB.

The serial write data input from the serial data terminals 51100 to 7 is sent to the serial input circuit SIB.
is transmitted to the serial input/output line through the serial selector SS, and written to each address of the serial access memory SAM specified by the serial selector SS.

The address signal taken into the row address buffer RAB is input to the row decoder RDEC, where it is decoded and one word line of the memory array MARY is selected.

The address signal taken into the column address buffer CAB is input to the column decoder CDEC, where it is decoded to form a selection signal for a pair of bins) fiil in the memory array MARY. Although not shown in the figure, a column switch circuit is provided in the column decoder CDEC, and the column switch is controlled by the selection signal to connect a pair of bit lines to a random input/output line. The main amplifier MA amplifies the signal of the random input/output line and inputs it to the random data output circuit DOB. Random data output circuit DO
B outputs the above read signal from the random data terminals R1100-7.

Random write data input from the random data terminals R1100 to R7 is transmitted to the random input/output line through the random input circuit DIB, and transmitted to the bit line pair of the memory array MARY through the selected column switch circuit.

Writing is performed because one memory cell is connected to the bit line pair by the word line selection operation.

In this embodiment, a signal path is provided for transmitting the output signal of the random main amplifier MA to the input of the serial data output circuit SOB. The reason for this is as follows. The first data when outputting serially is
If the data were transferred in parallel to the serial access memory SAM through the transfer gate TRG as described above and then transmitted to the input of the output circuit SOB through the serial selector SS and main amplifier SMA, the output of the first data would be delayed. Therefore, in this embodiment, the column address signal for specifying the start address is also taken into the column address buffer CAB, and the column decoder CDEC performs the column selection operation.

As a result, data at the designated start address is outputted at high speed through the random column switch circuit and main amplifier MA. This signal is transmitted to the input of the serial output circuit SOB via the signal path. As a result, serially output data is output at high speed.

Using this time, the serial circuit prepares to output the next data. Therefore, the selection operation of the leading data in the serial output operation is dummy or omitted.

In this embodiment, in order to realize high-speed serial output operation, pipeline transfer is performed between the serial address counter S_AMAC and the Gray code counter GCC which receives it and forms a bleed signal. That is, SAMAC sends out a binary address signal, and when GCC receives it, SAMAC immediately performs an increment operation of +1.

A decoder circuit is provided at the output section of the GCC to form a selection signal for selecting one serial selector SS. Although not shown, the serial main amplifier SM
A data latch circuit is provided at the output section of A. As a result, when the data output from the main amplifier SMA is captured in the data latch, the main amplifier SM
A immediately starts amplifying the serial data to be output next. In parallel with this amplification operation, the serial data output circuit SOB performs pipeline processing of outputting the data captured in the data latch. The breadline processing described above makes it possible to speed up the serial output operation.

When increasing the storage capacity as described above, the probability of defective bits occurring increases accordingly.

The row-based defective address storage circuit RRDC stores defective addresses depending on whether or not the fuse means is cut electrically or by a high-energy beam such as a laser beam. This defective address and the row address taken into the address buffer RAB are the address comparison circuit RA
It is input to MRA C. This address comparison circuit R
When AMRAC detects that a memory access is to a defective word line, its detection output is input to the row decoder RDEC, which prohibits the address selection operation of the defective word line and switches to the selection operation of a spare word line. . In this way, wax-based defect picks:・
can be rescued.

When attempting to increase the storage capacity of approximately 4 Mbits as described above, the probability of defective orders inevitably increases, and if this is left as is, the product yield will deteriorate. Therefore, in this embodiment, a redundant circuit is also provided in the column system.

In the column system defective address storage circuit CRDC, a defective address is programmed based on whether a fuse or the like is disconnected or not, as described above. In the serial mode, this defective address and the address signal generated by the serial address counter SAMAC are connected to the address comparison circuit SAMAC.
When a memory access to a defective bit line is detected as described above, it is input to the serial selector SS, and the selection of the serial access memory SAM corresponding to the defective bit line is prohibited. Select the SAM corresponding to the spare bit line.

In this case, in order to achieve high-speed operation, the address counter SAMAC has a latch circuit in its output section as described later, and when the output address is held, the next address is generated in advance, and the previous address and the defect The address is compared. By comparing with such a first address,
The output timing of the address counter SAMAC and the selection timing corresponding to the reserved bit can be made to match. As a result, serial access timing can be performed at high speed without impairing the regularity of the serial access timing at the time of relief and at the time of relief.

In random access mode, this defective address and the address taken into the address buffer CAB are input to the address comparison circuit RAMAC, and if the memory access is to a defective bit line, column selection corresponding to the defective bit line is prohibited. At the same time, a column switch corresponding to the spare bit line is selected. In this way, defect relief is performed even for bit line defects, thereby increasing the product yield of multi-board memories.

The timing generation circuit TG determines the supply voltage from the external terminal and generates an operation timing signal for the internal circuit in accordance with the determination.

Signal RAS is a row address strobe signal, and C
AS is a column address strobe signal, WE is a write enable signal, DTloE is a data transfer transition signal, SC is a serial clock signal, and SE is a serial enable signal.

FIG. 1 shows a block diagram of an embodiment for explaining a method of comparing the address counter and defective addresses.

In this embodiment, a start address input H and an address signal C passed through a latch circuit are selectively inputted via a multiplexer. The multiplexer is controlled by a manual switching signal G, and when setting an address, a column address signal A is input in synchronization with CAS as described above.
Yi is taken in, and thereafter the address output output through the latch circuit is taken in. The incrementer forms an address signal in which the address signal A input through the multiplexer is incremented by +1.Thereby, the initial value AYi is incremented by +1 by the incrementer and output as the first address output. It is possible to form an address signal for serial access that is compatible with high-speed serial access using the interleaving (or load-through) method in which the read signal from the RAM section as described above is output as the first data.

Incidentally, there is no particular restriction, and as will be described later, the incrementer can selectively perform +1 and 20 operations. This is true for cases other than serial output operation using the interleaving method, such as serial manual operation:
This is because it is necessary to access serially from the initial value address AYi. Further, by selectively causing the incrementer to perform the 1,000 operation as described above, it is also possible to perform a serial output operation that does not rely on the increment method as described above.

In this example, the incrementer as described above allows -
The address signal made ``1'' is input to a comparison circuit and compared with a defective address stored in a relief address ROM whose storage element is the fuse means.

A match/mismatch (repair/non-repair) output signal E of this comparison circuit is outputted as a redundancy selection signal F through a latch circuit. a latch circuit that holds the address output C;
The latch circuit that holds the redundancy selection signal F is one that performs the through/back/notch operation in synchronization with the same count-up signal. Therefore, the address output and the redundancy selection signal are output at the same timing.

FIG. 2 shows a timing diagram of an example of a defect relief operation using the address comparison method as in the embodiment shown in FIG.

At address N during the serial output operation, the latch circuit outputs address N from address output C. This address N is input to the incrementer via a multiplexer. When the latch circuit enters the holding state due to the count-up signal, the ink+ and jmentor perform a step operation of +1, and the output signal B of the incrementer becomes N+.
1 address signal is formed. This address signal N↓
1 is compared with the defective address stored in the relief address ROM by a comparison circuit. Both addresses match (relief)
If -1, the output signal E of the comparison circuit changes to high level as shown by the solid line in the figure. Then, at the timing when the next address is output by the count-up signal, both latch circuits enter the through state, and the next address N+1 formed by the incrementer and the redundancy selection signal are output at the same timing. As a result, the redundancy selection signal invalidates the Nil address and outputs data from the redundancy circuit.

Furthermore, if the output signal E of the address comparison circuit does not match (not taught), the signal E remains at a low level as shown by the dotted line in the figure, and accordingly, the redundancy selection signal F also remains at a low level. . In this case, the above address N
Serial data corresponding to =-1 is output.

In this embodiment, in parallel with the serial output operation using the current serial τ, 1 serial access address N, the next address N+1, which has been incremented by 1, is compared with the defective address, so switching to the redundant circuit can be done quickly. It becomes something that can be done.

FIG. 3 shows another embodiment of block interleaving for explaining the method of comparing the above-mentioned atto L-scanter and defective addresses.1. ing.

In this embodiment, the start address H and the address r multiplexed by the incrementer are selectively switched via the multiplexer and input to a latch circuit that holds the address output.

The multiplexer is controlled by the input switching signal G, and when setting the address, takes in the column address signal AYi input in synchronization with τAS as described above,
Thereafter, the incrementer switches to take in the next address incremented by 1. (In the embodiment shown in Fig. 1, the positions of the multiplexer and the incrementer are swapped. form.

In this embodiment, the initial value AYi is directly output as the first address output via the multiplexer. Therefore, as it is, serial output using the interleaving method that outputs the readout signal of the RAM section as the first data cannot be performed. For this purpose, it is sufficient to add a circuit that performs 〒1 to the start address input.

FIG. 4 shows a timing diagram of an example of a defect relief operation using the address comparison method as in the embodiment shown in FIG.

When the address is N during the serial output operation, the address output signal C of the latch circuit becomes the address N. When the latch circuit enters the holding state due to the count-up signal, the incrementer performs a +1 walk operation and an N+1 address signal is formed from the output signal I of the incrementer. This address signal N+1 is passed through a multiplexer to become a human input signal J for the slave circuit and comparison circuit. At this time, since the latch circuit is in a holding state, it outputs the address N without taking in (through) the next address N+1. The comparison circuit performs a comparison operation between the next address N volume 1 and the defective address stored in the relief address ROM.

When both addresses match (repair), the output signal E of the comparison circuit changes to high level as shown by the solid line in the figure.

Then, at the timing when the next address is output by the count-up signal, both latch circuits enter the through state, and the next address N↑1 formed by the incrementer and the redundancy selection signal are output at the same timing. As a result, the redundancy selection signal invalidates the N<1> addresses and outputs data from the redundancy circuit.

Further, if the output signal E of the address comparison circuit does not match (non-repair), the signal E remains at the low level as shown by the dotted line in the figure, and accordingly, the redundancy selection signal F also remains at the low level. In this case, the above address N
Serial data corresponding to +1 is output.

In this embodiment, in parallel with the serial output operation based on the current serial access address N, the next address N + 1, which has been incremented by 1, is compared with the defective address, so switching to the redundant circuit can be performed quickly. I understand that it will be possible.

FIG. 5 shows a block diagram of yet another embodiment for explaining the method of comparing the address counter and defective addresses.

In this example, the input switching signal is asserted late;
This is done in case address comparison cannot be completed in time until the Ranjishi point of the next cycle. That is, the following circuit is added to the embodiment shown in FIG. 1. In addition to being input to the multiplexer as described above, the start address input is also input to a dedicated incrementer so that a +1 step motion is performed. The output signal of this incrementer is inputted to a comparison circuit via a multiplexer together with the output of the incrementer.

That is, in this embodiment, if the address comparison at the start address cannot be completed in time as in 1), the next address of +1 is formed by the incrementer that receives the start address input, and when the multiplexer is switched by the input switching signal, the above The formed next address is input to the comparison circuit and immediately compared with the defective address of the relief address ROM. For addresses after the above start address, please refer to the above 2.
The address increment operation and address comparison operation similar to those in the embodiment shown in FIG. 1 are performed by switching two multiplexers.

FIG. 7 shows a specific circuit diagram of an embodiment of an address counter, an incrementer, etc.

In this embodiment, one unit circuit having the functions of the multiplexer, incrementer, and latch circuit as described above is exemplified as a representative. As mentioned above, when the address signal consists of 9 bits like AO-A8,
A total of 9 similar unit circuits are provided, and the counter section's carry power CiB and carry output C01B, the calculation section's carry power 5CiB and carry output CO5i B
and are connected in a cascade configuration.

The counter section consists of a master/slave binary counter circuit, and performs a binary counting operation using two clock pulses ACC1 and ACC2. In the least significant bit circuit, the carry input CiB is fixed at a low level. Count outputs ANi and Ai are clock pulse ACC2 as described above.
ANi with early timing that is output in synchronization with
The latch output signal Ai is output in synchronization with the clock pulse ACC1. Therefore, the above address signal AN
i is used for a comparison operation with a defective address, and address signal Ai is used for serial access.

The address set section is provided with an arithmetic section that selectively increments the start address AYi by +1 or 10. That is, the cent address signal ALC
When taking in the head address signal AYi, if the carry signal 5CiB of the arithmetic unit corresponding to the least significant bit is set to high level, the address AYi of the head (lowest via) is output as is through the path Pb. As a result, 20 address operations are performed on the first address. On the other hand, if the carry signal 5CiB of the arithmetic unit corresponding to the least significant bit is set to low level, an address that is subtracted by 1 from the first address corresponding to the least significant bit is formed through the bus pa. Become. In this way, by using the carry power of the arithmetic unit in the least significant bit, the carry power, which would normally be simply fixed at a high level or omitted, can be adjusted to the operating mode without adding a special circuit. Selective +1 when switching to level/low level
Actions can be performed.

This circuit is useful in the case of serial output by interleaving as described above, or in the case of immediately adding +1 to the start address input as in the embodiment of FIG. The address signal formed by such a calculation section is input as an initial value to the counter section through a clocked inverter circuit controlled by a timing signal ASC. In this embodiment, a series circuit of MOSFETs controlled by the signals ASC and ACC2 is provided in order to prevent malfunctions due to conflict between the timing signal ASC and the clock pulse ACC2.

The effects obtained from the above examples are as follows. That is, (1) In a semiconductor memory device equipped with a serial access function according to an address signal generated internally and a redundant circuit for defective political conditions, an address signal is generated in advance of an address signal for serial access. By making the timing of the redundant selection signal coincide with the address output timing for serial access, the next address and the defective address can be output in parallel with the address output for serial access. Since the comparison can be performed, the overhead caused by address comparison for defect relief can be eliminated, and the effect of enabling high-speed serial access can be obtained.

(2) By providing a latch circuit in the output section and forming a serial access output signal via this latch circuit,
After the address is held in the latch circuit, the next address can be generated and compared with the defective address in parallel with the serial access operation by outputting that address. By outputting the redundancy selection signal through the serial output operation, it is possible to achieve the effect that the output operation can be performed at the same timing even when switching between redundant circuits in the serial output operation.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, in the embodiment shown in FIG. 8, the storage capacity and address allocation can take various embodiments. Also, the gray code counter of the SAM section may be omitted and the selected address of the SAM section may be formed by the address counter as described above. Also, if the teaching address R0M,
A non-volatile memory element may also be used. Address comparison circuits include those that use match/mismatch circuits such as exclusive OR circuits, and those that use AND (A
ND) type may be used. Further, the incrementer can take various embodiments, such as one using an arithmetic circuit (adder) or one using a T-type frisobfrop circuit going to the D input. The start address input can be omitted if always starting from a fixed address.

That is, when used in an image processing device such as a television receiver or a video tape recorder, the starting address may be fixed.

The present invention may be applied to a multiport memory having a RAM section and a SAM section, as well as a semiconductor memory device having only a serial access port.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a semiconductor memory device that is equipped with a serial access function according to an address signal generated internally and a redundant circuit for defect recovery, an address signal that precedes an address signal for serial access is generated. By comparing the timing with the defective address and making the timing of the redundancy selection signal match the address output timing for serial access, the next address and the defective address can be output in parallel with the address output for serial access. Since the comparison can be performed, the overhead due to address comparison due to defective political conditions can be eliminated, and high-speed serial access becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an embodiment of a method for comparing a serial access address counter and a defective address according to the present invention, and FIG. 2 is a timing diagram illustrating an example of its operation. , FIG. 3 is a block diagram showing another implementation column for explaining the comparison method between the address counter for serial access and a defective address, and FIG. 4 shows a timing chart for explaining an example of its operation. FIG. 5 is a block diagram showing yet another embodiment for explaining the method of comparing the address counter for serial access and a defective address, and FIG. 6 is a block diagram for explaining an example of the prior art. A block diagram; FIG. 7 is a specific circuit diagram showing an embodiment of the address counter and incrementer, etc. according to the present invention; FIG. 8 is a specific circuit diagram showing an embodiment of the multi-port memory to which the present invention is applied. FIG. 3 is a circuit functional block diagram. M ARY...Memory array, SAM...Serial access memory, SAMAC...Serial address counter, GCC...Gray code counter, SS...Serial selector, TRG...Transfer gate, RAB...
・Row address buffer, CAB...Column address buffer, R4~MRAC...Random row address comparison circuit, RAMCAC...Random column address comparison circuit, CDEC...Column decoder, SA...Sense amplifier, MA...Main Amplifier, DOB...random data output circuit, DIB...random data input circuit, SMA...main amplifier for serial, SOB...serial output circuit, SIB...serial input circuit, CR
DC: Column defective address storage circuit, RRDC: Row defective address storage circuit, SAM CA'C: Serial address comparison circuit, TG: Timing generation circuit.

Claims (1)

[Scope of Claims] 1) It is equipped with a serial access function according to an address signal generated internally and a redundant circuit for defect relief, and generates an address signal preceding the address signal for serial access. Compare with the defective address,
A semiconductor memory device characterized in that the timing of the redundancy selection signal is made to substantially match the address output timing for the serial access. 2) The circuit that forms the address signal for serial access includes a multiplexer that switches between the start address and the output address or an incremented address signal, an incrementer that forms the next address signal, and a latch circuit that holds the output address. Claims characterized in that, when the output address is held in the latch circuit, an incrementer operates to generate a next address signal, which is compared with the defective address. 2. The semiconductor memory device according to item 1. 3) The semiconductor memory device according to claim 2, wherein the redundancy selection signal is output through a latch circuit that operates according to the same timing signal as a latch circuit that holds the output address.