JPH0447598A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce noises by turning a part of output transistors among plural output transistor to a nonconductive condition at the time of faster access timing. CONSTITUTION:In a normal reading mode, input signals OE/-OE become 'H' and 'L' levels respectively, and when a data signal Din becomes 'H' level, P-channel transistors 5/6 become an ON state, N channel transistors 7/8 become an OFF state, and an output Dout becomes 'H' level. On the other hand, input signals PF/-PR becomes 'H' level and 'L' level respectively in a high-speed reading mode, a point E and a point F become 'H' level and 'L' level respectively inspite of a data signal D1n, the P-channel transistor 6 and the N-channel transistor 8 become the OFF state, and only the P-channel transistor 5 becomes the ON state. Thus, the current driving capacity of the output transistor is decreased, and the generation of noises can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular to an R O device having two types of read modes with different access timings.
iJ ("<e&60nly Memory)".

[Conventional technology]

FIG. 2 is a circuit diagram showing an output sofa circuit of a conventional semiconductor memory device. In the figure (1) is the data signal Di
It is a NAND circuit that receives the input signal OK and the input signal OK.
(3) is N to which data signal Din and input signal i are input.
OR circuit, (5) is the source! (7) has its source connected to the ground level, its drain connected to the output terminal (9), and its gate connected to the output of the NAND circuit (1). are connected to the outputs of the NOR circuit (3) using N-channel transistors.

Next, the operation will be explained. First, when output is prohibited, the input signal 01C10 becomes もL' and ``H level, respectively, and the A shown in the figure is applied regardless of the signal of the data signal Din.
The ten thousand points become ゞH' and `L# level μ, respectively. Therefore, the P-channel transistor (5) and the N-channel transistor (7) are in the 0IFI/ state and the output Do
ot becomes a high impedance state.

Next, when reading, the input signals OK and OK are each %
H# 'h LI level becomes data signal D1n
The signal is transmitted to 10,000 points A. That is, the data signal Din
If is 'H#', the A point is Ll, therefore the P channel transistor (5) is in the ON state, the 3rd point is %L', therefore the N channel transistor (7) is in the OFF state, and the output DO1lt is at the %H# level. Become. If the data signal Din is L#, the A point is lk H11, so the P channel transistor (5) is in the o77 state, and the 1 point is H#, so N
The channel transistor (7) is in the ON state and the output Do
at becomes %L# level.

[Problem to be solved by the invention]

Conventional semiconductor memory devices are configured as described above, so in a ROM that has two types of read modes with different access timings, it is difficult to optimize the output buffer circuit for each of the above modes. There was a problem.

This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor memory device that can optimize the output 8777 circuit in each mode in two types of reading with different access timings. purpose.

[Means to solve the problem]

The semiconductor memory device according to the present invention has a plurality of output transistors, and at the time of faster access timing, some of the output transistors among the plurality of output transistors are rendered non-conductive. Semiconductor memory devices reduce the current drive capability of the output transistors by making some of the multiple output transistors non-conductive during faster access timing, and reduce noise during faster access timing. Control the outbreak.

〔Example〕

An embodiment of a semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the output x7a circuit. In the figure (1) s (3) t (5)
.

(7) and +9> are the same as those shown in the conventional example of FIG. 2, so their explanation will be omitted. (2) is the data signal Di
NANI inputs n, input signal OE, and input signal 11
) circuit, (4) is a NOR circuit that receives data signal D4m, input signal n, and input signal PR, (6) is a NOR circuit with the source as the power supply, the drain as the output terminal (9), and the gate as the NAND circuit.
P-channel transistor (8) is connected to the output of circuit (2), and N-channel transistor (8) has its source connected to the ground level, its drain connected to the output terminal (9), and its gate connected to the output of the NOR circuit (4). be.

Next, the operation will be explained. First, if output is prohibited,
The input signals 01C and 01li are respectively ゞL'%H level, and the 0 point and D point shown in the figure are reached regardless of the data signal Din and the input signals PR and PR.

Point 1 and point F are at the )IL and HL# levels, respectively, and the P channel transistors (5) and (6
), N-channel transistors (7) l (8) are all 0I
It becomes an FF state and the output Dont becomes a high impedance state.

Conversely, at the time of reading, the input signals OK and 01 are respectively at the H#4LI level, and the level of the output DOQt is determined by the data signal Din.

Here, in the normal read mode, that is, the mode with relatively slow read timing, t #
% 〃 The input signals PR and PR are at L and H levels, respectively, and if the data signal Din is 'H', the 0 point, D point, E point, and F point are all at the 'L test level, so the P channel transistor (5) , (6) is ON, N-channel transistor (7), (8) is 01! ? state and the output Doat? It becomes 11H Rubel. data signal D
If in is 1L#, 0 point, D point, E point, F point are all 4
H# level ~, P channel transistor (5) t
(6) is in 071 state, N-channel transistor (7
)? (8) is turned on and the output Dout becomes only level.

Next, in a high-speed read mode, that is, a mode with a faster read timing than the normal read mode, the input signals PR and PR are respectively ゞH#%
Regardless of the data signal D121, each point becomes 4F10'L# level, and P
Are channel transistor (6) and N-channel transistor (8) OF? state.

Therefore, in high-speed read mode, the output Dotx
When outputting the 2H# level at t, the P channel transistor (5) also outputs the L level output Dqt! When outputting t, only the N-channel transistor (7) is turned on.

Note that in the above embodiment, the output transistors include P-channel transistors (5), (6), and N-channel transistors (7) r (g);
Channel transistor (5) e N-channel transistor (7).

(8) alone is sufficient.

〔Effect of the invention〕

As described above, 1. According to the present invention, a plurality of output transistors are provided, and some of the output transistors are rendered non-conductive during faster access timing, so that during normal access timing and In either case when the access timing is faster, the output transistor can be optimized and noise can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an output balancing circuit according to an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing a conventional output balancing circuit. In the figure, (1) and (2) are NAND circuits, (3
), (4) is a NOR circuit% (5), (a+ is a P-channel transistor (7), (8) is an N-channel transistor, and (9) is an output terminal. In addition, in the figures, the same symbols are the same, or a corresponding portion.

Claims (1)

[Claims] A semiconductor memory device having two types of read modes with different access timings, including a plurality of output transistors, and at a faster access timing, some of the output transistors among the plurality of output transistors are rendered non-conductive. A semiconductor storage device.