JPH0447386U - - Google Patents
Info
- Publication number
- JPH0447386U JPH0447386U JP8993290U JP8993290U JPH0447386U JP H0447386 U JPH0447386 U JP H0447386U JP 8993290 U JP8993290 U JP 8993290U JP 8993290 U JP8993290 U JP 8993290U JP H0447386 U JPH0447386 U JP H0447386U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- switching regulator
- flop
- flip
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は本考案の一実施例の回路図、第２図は
メインスイツチを制御するＲＳフリツプフロツプ
の動作図、第３図はホトカプラを用いた従来のス
イツチングレギユレータの回路図、第４図はトラ
ンスとＰＡＭ回路とを用いた従来のスイツチング
レギユレータの回路図である。
１……直流入力電源、２……メインスイツチ、
３……トランス、４……整流回路、５……駆動回
路、６……ＰＷＭ制御回路、７……信号変換回路
。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an operational diagram of an RS flip-flop that controls the main switch, Fig. 3 is a circuit diagram of a conventional switching regulator using a photocoupler, and Fig. 4 is a circuit diagram of an embodiment of the present invention. The figure is a circuit diagram of a conventional switching regulator using a transformer and a PAM circuit. 1...DC input power supply, 2...Main switch,
3...Transformer, 4...Rectifier circuit, 5...Drive circuit, 6...PWM control circuit, 7...Signal conversion circuit.
Claims (1)
圧との差分を電圧増幅する誤差増幅器と、特定の
周波数の同期信号およびランプ波形信号を出力す
る発振器と、前記誤差増幅器の出力および前記ラ
ンプ波形信号を入力とする比較器と、前記同期信
号および前記比較器の出力信号とがそれぞれリセ
ツト信号およびセツト信号として入力されるＲＳ
フリツプフロツプと、前記ＲＳフリツプフロツプ
の出力状態によつてスイツチングレギユレータの
メインスイツチをオン・オフさせる駆動回路と、
起動時に前記ＲＳフリツプフロツプへ信号を送出
する起動回路とを備え、スイツチングレギユレー
タの１次側で制御を行うスイツチングレギユレー
タのＰＷＭ制御回路において、前記発振器の同期
信号および前記比較器の出力信号と前記ＲＳフリ
ツプフロツプのリセツト信号入力およびセツト信
号入力との間にホトカプラを挿入することを特徴
とするスイツチングレギユレータのＰＷＭ制御回
路。 An error amplifier that amplifies the difference between the output voltage of the switching regulator and a reference voltage, an oscillator that outputs a synchronization signal of a specific frequency and a ramp waveform signal, and inputs the output of the error amplifier and the ramp waveform signal. and an RS in which the synchronization signal and the output signal of the comparator are input as a reset signal and a set signal, respectively.
a flip-flop, and a drive circuit that turns on and off a main switch of a switching regulator depending on the output state of the RS flip-flop;
A PWM control circuit for a switching regulator, which includes a startup circuit that sends a signal to the RS flip-flop at startup, and performs control on the primary side of the switching regulator; A PWM control circuit for a switching regulator, characterized in that a photocoupler is inserted between an output signal and a reset signal input and a set signal input of the RS flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8993290U JPH0447386U (en) | 1990-08-28 | 1990-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8993290U JPH0447386U (en) | 1990-08-28 | 1990-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0447386U true JPH0447386U (en) | 1992-04-22 |
Family
ID=31824269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8993290U Pending JPH0447386U (en) | 1990-08-28 | 1990-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0447386U (en) |
-
1990
- 1990-08-28 JP JP8993290U patent/JPH0447386U/ja active Pending